BRPI0518265A2 - controle dinÂmico de velocidade de acesso À memària - Google Patents

controle dinÂmico de velocidade de acesso À memària

Info

Publication number
BRPI0518265A2
BRPI0518265A2 BRPI0518265-4A BRPI0518265A BRPI0518265A2 BR PI0518265 A2 BRPI0518265 A2 BR PI0518265A2 BR PI0518265 A BRPI0518265 A BR PI0518265A BR PI0518265 A2 BRPI0518265 A2 BR PI0518265A2
Authority
BR
Brazil
Prior art keywords
access speed
memory
speed control
memory access
dynamic memory
Prior art date
Application number
BRPI0518265-4A
Other languages
English (en)
Inventor
Robert Michael Walker
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI0518265A2 publication Critical patent/BRPI0518265A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Control Of Electric Motors In General (AREA)

Abstract

CONTROLE DINÂMICO DE VELOCIDADE DE ACESSO À MEMàRIA. Um sistema de memória é descrito no qual a velocidade de acesso pode ser ajustada. O sistema de memória pode incluir a memória e um controlador de memória. O controlador de memória pode ser configurado para gerar uma pluralidade de sinais de controle para acessar a memória e ajustar a temporízação entre os sinais de controle para mudar a velocidade de acesso à memória como uma função de um parâmetro relacionado com a operação do sistema de memória.
BRPI0518265-4A 2004-11-24 2005-11-22 controle dinÂmico de velocidade de acesso À memària BRPI0518265A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/997,140 US7650481B2 (en) 2004-11-24 2004-11-24 Dynamic control of memory access speed
PCT/US2005/042532 WO2006058115A1 (en) 2004-11-24 2005-11-22 Dynamic control of memory access speed

Publications (1)

Publication Number Publication Date
BRPI0518265A2 true BRPI0518265A2 (pt) 2008-11-11

Family

ID=36129981

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0518265-4A BRPI0518265A2 (pt) 2004-11-24 2005-11-22 controle dinÂmico de velocidade de acesso À memària

Country Status (8)

Country Link
US (1) US7650481B2 (pt)
EP (1) EP1836583B1 (pt)
JP (2) JP4805943B2 (pt)
KR (1) KR100953257B1 (pt)
CN (1) CN101103344B (pt)
BR (1) BRPI0518265A2 (pt)
IL (1) IL183411A0 (pt)
WO (1) WO2006058115A1 (pt)

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US20150363116A1 (en) * 2014-06-12 2015-12-17 Advanced Micro Devices, Inc. Memory controller power management based on latency
US10592122B2 (en) * 2015-03-31 2020-03-17 Sandisk Technologies Llc Inherent adaptive trimming
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JP6607069B2 (ja) * 2016-02-12 2019-11-20 日本電気株式会社 メモリアクセス制御装置、メモリアクセス制御方法、プログラム
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US10593409B2 (en) 2017-10-12 2020-03-17 Distech Controls Inc. Memory device comprising flash memory and method for controlling a write speed of a bus transmitting data for storage on the flash memory
US10642746B2 (en) * 2018-03-22 2020-05-05 Western Digital Technologies, Inc. Controlling cached/non-cached memory access decisions based on memory access queue fill levels
US11169583B2 (en) * 2018-08-07 2021-11-09 Western Digital Technologies, Inc. Methods and apparatus for mitigating temperature increases in a solid state device (SSD)
US11119665B2 (en) * 2018-12-06 2021-09-14 Advanced Micro Devices, Inc. Dynamic voltage and frequency scaling based on memory channel slack
CN111913651B (zh) * 2019-05-10 2024-03-01 技嘉科技股份有限公司 固态硬盘以及固态硬盘的效能优化方法
US11151043B2 (en) * 2019-08-12 2021-10-19 Micron Technology, Inc. Demand delay and data value correlated memory pre-fetching systems and methods
CN110927562B (zh) * 2019-12-19 2022-08-05 西安紫光国芯半导体有限公司 一种兼容老化测试的方法及其芯片
TWI801106B (zh) * 2022-01-24 2023-05-01 宜鼎國際股份有限公司 記憶體存取速度調整方法、控制裝置以及記憶體模組
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Also Published As

Publication number Publication date
KR20070086503A (ko) 2007-08-27
KR100953257B1 (ko) 2010-04-16
CN101103344A (zh) 2008-01-09
WO2006058115A1 (en) 2006-06-01
EP1836583A1 (en) 2007-09-26
CN101103344B (zh) 2011-12-14
IL183411A0 (en) 2007-09-20
US7650481B2 (en) 2010-01-19
JP5389865B2 (ja) 2014-01-15
JP2008522287A (ja) 2008-06-26
JP2011238256A (ja) 2011-11-24
EP1836583B1 (en) 2018-05-30
US20060112250A1 (en) 2006-05-25
JP4805943B2 (ja) 2011-11-02

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE AO NAO RECOLHIMENTO DA 7A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2208 DE 30/04/2013.