CA1026870A - Systeme informatique comportant une instruction de comparaison logique - Google Patents

Systeme informatique comportant une instruction de comparaison logique

Info

Publication number
CA1026870A
CA1026870A CA215,878A CA215878A CA1026870A CA 1026870 A CA1026870 A CA 1026870A CA 215878 A CA215878 A CA 215878A CA 1026870 A CA1026870 A CA 1026870A
Authority
CA
Canada
Prior art keywords
data processing
processing system
system incorporating
compare instruction
logical compare
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA215,878A
Other languages
English (en)
Other versions
CA215878S (en
Inventor
Charles W. Bachman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1026870A publication Critical patent/CA1026870A/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99941—Database schema or data structure
    • Y10S707/99942—Manipulating data structure, e.g. compression, compaction, compilation

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
CA215,878A 1973-12-13 1974-12-12 Systeme informatique comportant une instruction de comparaison logique Expired CA1026870A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/424,406 US4068299A (en) 1973-12-13 1973-12-13 Data processing system incorporating a logical compare instruction

Publications (1)

Publication Number Publication Date
CA1026870A true CA1026870A (fr) 1978-02-21

Family

ID=23682518

Family Applications (1)

Application Number Title Priority Date Filing Date
CA215,878A Expired CA1026870A (fr) 1973-12-13 1974-12-12 Systeme informatique comportant une instruction de comparaison logique

Country Status (7)

Country Link
US (1) US4068299A (fr)
JP (1) JPS584368B2 (fr)
CA (1) CA1026870A (fr)
DE (1) DE2458259A1 (fr)
FR (1) FR2254825B1 (fr)
GB (1) GB1494506A (fr)
IT (1) IT1035093B (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156926A (en) * 1976-06-01 1979-05-29 Texas Instruments Incorporated PROM circuit board programmer
US4214303A (en) * 1977-12-22 1980-07-22 Honeywell Information Systems Inc. Word oriented high speed buffer memory system connected to a system bus
US4268907A (en) * 1979-01-22 1981-05-19 Honeywell Information Systems Inc. Cache unit bypass apparatus
JP2844591B2 (ja) * 1987-01-16 1999-01-06 株式会社日立製作所 ディジタル信号処理装置
US5197141A (en) * 1988-01-30 1993-03-23 Nec Corporation Software controlled method of issuing hardware control commands to memory controller from prefetch unit by combining request code and address specified in program instructions
US5045992A (en) * 1988-10-19 1991-09-03 Hewlett-Packard Company Apparatus for executing instruction regardless of data types and thereafter selectively branching to other instruction upon determining of incompatible data type
US6292879B1 (en) 1995-10-25 2001-09-18 Anthony S. Fong Method and apparatus to specify access control list and cache enabling and cache coherency requirement enabling on individual operands of an instruction of a computer
US5907842A (en) * 1995-12-20 1999-05-25 Intel Corporation Method of sorting numbers to obtain maxima/minima values with ordering
US6557096B1 (en) 1999-10-25 2003-04-29 Intel Corporation Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types
US6732203B2 (en) 2000-01-31 2004-05-04 Intel Corporation Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus
JP3845814B2 (ja) * 2000-08-10 2006-11-15 株式会社テルミナス・テクノロジー 連想メモリとその検索方法及びルータとネットワークシステム
US9069547B2 (en) 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
US9195463B2 (en) * 2011-11-30 2015-11-24 International Business Machines Corporation Processing core with speculative register preprocessing in unused execution unit cycles

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE758811A (fr) * 1969-11-28 1971-04-16 Burroughs Corp Systeme de traitement d'information ayant un emmagasinage sans structure pour traitements emboites
US3805247A (en) * 1972-05-16 1974-04-16 Burroughs Corp Description driven microprogrammable multiprocessor system

Also Published As

Publication number Publication date
FR2254825A1 (fr) 1975-07-11
AU7607774A (en) 1976-06-10
JPS584368B2 (ja) 1983-01-26
GB1494506A (en) 1977-12-07
JPS50115440A (fr) 1975-09-10
US4068299A (en) 1978-01-10
IT1035093B (it) 1979-10-20
FR2254825B1 (fr) 1979-02-23
DE2458259A1 (de) 1975-06-19

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