CA1040749A - Method of manufacturing fine line conductors on semiconductors - Google Patents

Method of manufacturing fine line conductors on semiconductors

Info

Publication number
CA1040749A
CA1040749A CA227,266A CA227266A CA1040749A CA 1040749 A CA1040749 A CA 1040749A CA 227266 A CA227266 A CA 227266A CA 1040749 A CA1040749 A CA 1040749A
Authority
CA
Canada
Prior art keywords
layer
polycrystalline
diffused
region
masking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA227,266A
Other languages
English (en)
French (fr)
Other versions
CA227266S (en
Inventor
Keith H. Nicholas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of CA1040749A publication Critical patent/CA1040749A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/0133Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30Diffusion for doping of conductive or resistive layers
    • H10P32/302Doping polycrystalline silicon or amorphous silicon layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/60Wet etching
    • H10P50/66Wet etching of conductive or resistive materials
    • H10P50/663Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
CA227,266A 1974-05-21 1975-05-15 Method of manufacturing fine line conductors on semiconductors Expired CA1040749A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2258374A GB1477511A (en) 1974-05-21 1974-05-21 Methods of manufacturing semiconductor devices

Publications (1)

Publication Number Publication Date
CA1040749A true CA1040749A (en) 1978-10-17

Family

ID=10181779

Family Applications (1)

Application Number Title Priority Date Filing Date
CA227,266A Expired CA1040749A (en) 1974-05-21 1975-05-15 Method of manufacturing fine line conductors on semiconductors

Country Status (6)

Country Link
JP (1) JPS5617826B2 (2)
CA (1) CA1040749A (2)
DE (1) DE2522448A1 (2)
FR (1) FR2272486B1 (2)
GB (1) GB1477511A (2)
NL (1) NL7505698A (2)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit
JPS598855Y2 (ja) * 1978-09-01 1984-03-19 大阪電気株式会社 ワイヤ送給装置
JPS5546570A (en) * 1978-09-30 1980-04-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Method of fabricating mos semiconductor device
US4298402A (en) * 1980-02-04 1981-11-03 Fairchild Camera & Instrument Corp. Method of fabricating self-aligned lateral bipolar transistor utilizing special masking techniques
JPS6070401U (ja) * 1983-10-24 1985-05-18 株式会社月星製作所 車輪用スポ−ク
CN105824160B (zh) * 2015-01-08 2020-06-16 群创光电股份有限公司 显示面板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5542501B2 (2) * 1974-01-29 1980-10-31

Also Published As

Publication number Publication date
JPS51282A (2) 1976-01-05
DE2522448A1 (de) 1975-12-04
FR2272486B1 (2) 1979-01-19
GB1477511A (en) 1977-06-22
FR2272486A1 (2) 1975-12-19
NL7505698A (nl) 1975-11-25
JPS5617826B2 (2) 1981-04-24

Similar Documents

Publication Publication Date Title
US4124933A (en) Methods of manufacturing semiconductor devices
CA1159953A (en) V-mos device with self-aligned multiple electrodes
US4688323A (en) Method for fabricating vertical MOSFETs
US4285116A (en) Method of manufacturing high voltage MIS type semiconductor device
US5008209A (en) Method of manufacturing a semiconductor device including outdiffusion from polysilicon rims
EP0067206A4 (en) Method for fabricating complementary semiconductor devices.
GB1567197A (en) Methods of manufacturing semiconductor devices
US5030584A (en) Method for fabricating MOS semiconductor device operable in a high voltage range using polysilicon outdiffusion
JPS622708B2 (2)
JPS6140146B2 (2)
US4287660A (en) Methods of manufacturing semiconductor devices
US3789503A (en) Insulated gate type field effect device and method of making the same
CA1040749A (en) Method of manufacturing fine line conductors on semiconductors
US5654241A (en) Method for manufacturing a semiconductor device having reduced resistance of diffusion layers and gate electrodes
EP0030147A1 (en) Method for manufacturing a semiconductor integrated circuit
US4280271A (en) Three level interconnect process for manufacture of integrated circuit devices
KR940002834B1 (ko) 반도체 집적회로와 그 제조방법
US4377903A (en) Method for manufacturing an I2 L semiconductor device
US4216038A (en) Semiconductor device and manufacturing process thereof
KR890005817A (ko) 반도체 바이씨 모오스 장치의 제조방법
JPH0116018B2 (2)
US4416055A (en) Method of fabricating a monolithic integrated circuit structure
JPH04258160A (ja) 半導体装置
KR0155580B1 (ko) 캐패시터 제조방법
JPH04133423A (ja) 半導体装置の製造方法