CA1118892A - Dispositif a semiconducteur utilisant des cellules de memoire a regions murales de stockage de charge - Google Patents

Dispositif a semiconducteur utilisant des cellules de memoire a regions murales de stockage de charge

Info

Publication number
CA1118892A
CA1118892A CA000308013A CA308013A CA1118892A CA 1118892 A CA1118892 A CA 1118892A CA 000308013 A CA000308013 A CA 000308013A CA 308013 A CA308013 A CA 308013A CA 1118892 A CA1118892 A CA 1118892A
Authority
CA
Canada
Prior art keywords
recess
forming
layer
substrate
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000308013A
Other languages
English (en)
Inventor
John R. Edwards
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
American Microsystems Holding Corp
Original Assignee
American Microsystems Holding Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Microsystems Holding Corp filed Critical American Microsystems Holding Corp
Application granted granted Critical
Publication of CA1118892A publication Critical patent/CA1118892A/fr
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
CA000308013A 1977-12-27 1978-07-24 Dispositif a semiconducteur utilisant des cellules de memoire a regions murales de stockage de charge Expired CA1118892A (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US86453677A 1977-12-27 1977-12-27
US864,536 1977-12-27

Publications (1)

Publication Number Publication Date
CA1118892A true CA1118892A (fr) 1982-02-23

Family

ID=25343489

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000308013A Expired CA1118892A (fr) 1977-12-27 1978-07-24 Dispositif a semiconducteur utilisant des cellules de memoire a regions murales de stockage de charge

Country Status (7)

Country Link
JP (1) JPS5492077A (fr)
CA (1) CA1118892A (fr)
DE (1) DE2842334A1 (fr)
FR (1) FR2413789A1 (fr)
GB (1) GB2011175B (fr)
IT (1) IT7869937A0 (fr)
NL (1) NL7808079A (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2909820A1 (de) * 1979-03-13 1980-09-18 Siemens Ag Halbleiterspeicher mit eintransistorzellen in v-mos-technologie
US4252579A (en) * 1979-05-07 1981-02-24 International Business Machines Corporation Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition
US4335450A (en) * 1980-01-30 1982-06-15 International Business Machines Corporation Non-destructive read out field effect transistor memory cell system
US4423490A (en) * 1980-10-27 1983-12-27 Burroughs Corporation JFET Dynamic memory
JPS6135554A (ja) * 1984-07-28 1986-02-20 Nippon Telegr & Teleph Corp <Ntt> 読出し専用メモリ−およびその製造方法
US4997783A (en) * 1987-07-02 1991-03-05 Integrated Device Technology, Inc. Static ram cell with trench pull-down transistors and buried-layer ground plate
US4987090A (en) * 1987-07-02 1991-01-22 Integrated Device Technology, Inc. Static ram cell with trench pull-down transistors and buried-layer ground plate
US6963108B1 (en) * 2003-10-10 2005-11-08 Advanced Micro Devices, Inc. Recessed channel

Also Published As

Publication number Publication date
DE2842334A1 (de) 1979-07-05
FR2413789A1 (fr) 1979-07-27
GB2011175B (en) 1982-02-10
JPS5492077A (en) 1979-07-20
GB2011175A (en) 1979-07-04
NL7808079A (nl) 1979-06-29
IT7869937A0 (it) 1978-12-22

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Legal Events

Date Code Title Description
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