CA1197323A - Appareil de verification dynamique en circuit d'elements de circuits numeriques - Google Patents
Appareil de verification dynamique en circuit d'elements de circuits numeriquesInfo
- Publication number
- CA1197323A CA1197323A CA000444462A CA444462A CA1197323A CA 1197323 A CA1197323 A CA 1197323A CA 000444462 A CA000444462 A CA 000444462A CA 444462 A CA444462 A CA 444462A CA 1197323 A CA1197323 A CA 1197323A
- Authority
- CA
- Canada
- Prior art keywords
- test
- signals
- terminal
- signal
- library
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 153
- 230000015654 memory Effects 0.000 claims description 26
- 230000002457 bidirectional effect Effects 0.000 claims description 13
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000005070 sampling Methods 0.000 claims 4
- 230000000875 corresponding effect Effects 0.000 abstract description 19
- 238000010586 diagram Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 6
- 238000003825 pressing Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 5
- 230000001934 delay Effects 0.000 description 4
- 239000000872 buffer Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 101150087426 Gnal gene Proteins 0.000 description 1
- 102100023696 Histone-lysine N-methyltransferase SETDB1 Human genes 0.000 description 1
- 101710168120 Histone-lysine N-methyltransferase SETDB1 Proteins 0.000 description 1
- 239000007983 Tris buffer Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- MPHPHYZQRGLTBO-UHFFFAOYSA-N apazone Chemical compound CC1=CC=C2N=C(N(C)C)N3C(=O)C(CCC)C(=O)N3C2=C1 MPHPHYZQRGLTBO-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012956 testing procedure Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000444462A CA1197323A (fr) | 1983-12-29 | 1983-12-29 | Appareil de verification dynamique en circuit d'elements de circuits numeriques |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000444462A CA1197323A (fr) | 1983-12-29 | 1983-12-29 | Appareil de verification dynamique en circuit d'elements de circuits numeriques |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000358461A Division CA1163721A (fr) | 1980-08-18 | 1980-08-18 | Appareil de verification dynamique en circuit de dispositifs electroniques numeriques |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1197323A true CA1197323A (fr) | 1985-11-26 |
Family
ID=4126843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000444462A Expired CA1197323A (fr) | 1983-12-29 | 1983-12-29 | Appareil de verification dynamique en circuit d'elements de circuits numeriques |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1197323A (fr) |
-
1983
- 1983-12-29 CA CA000444462A patent/CA1197323A/fr not_active Expired
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |