CA1204510A - Memory using multiplexed row and column address lines - Google Patents

Memory using multiplexed row and column address lines

Info

Publication number
CA1204510A
CA1204510A CA000441761A CA441761A CA1204510A CA 1204510 A CA1204510 A CA 1204510A CA 000441761 A CA000441761 A CA 000441761A CA 441761 A CA441761 A CA 441761A CA 1204510 A CA1204510 A CA 1204510A
Authority
CA
Canada
Prior art keywords
memory
row
coupled
decoders
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000441761A
Other languages
English (en)
French (fr)
Inventor
Austin C. Dumbri
Frank J. Procyk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Application granted granted Critical
Publication of CA1204510A publication Critical patent/CA1204510A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
CA000441761A 1982-12-22 1983-11-23 Memory using multiplexed row and column address lines Expired CA1204510A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/452,155 US4541078A (en) 1982-12-22 1982-12-22 Memory using multiplexed row and column address lines
US452,155 1982-12-22

Publications (1)

Publication Number Publication Date
CA1204510A true CA1204510A (en) 1986-05-13

Family

ID=23795276

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000441761A Expired CA1204510A (en) 1982-12-22 1983-11-23 Memory using multiplexed row and column address lines

Country Status (8)

Country Link
US (1) US4541078A (de)
EP (1) EP0129578A1 (de)
KR (1) KR840007196A (de)
CA (1) CA1204510A (de)
ES (1) ES8407615A1 (de)
GB (1) GB2132799A (de)
IT (1) IT1173689B (de)
WO (1) WO1984002608A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5954096A (ja) * 1982-09-22 1984-03-28 Hitachi Ltd ダイナミツク型ｍｏｓｒａｍ
US4675808A (en) * 1983-08-08 1987-06-23 American Telephone And Telegraph Company At&T Bell Laboratories Multiplexed-address interface for addressing memories of various sizes
US5191555A (en) * 1990-07-31 1993-03-02 Texas Instruments, Incorporated Cmos single input buffer for multiplexed inputs
KR930008838A (ko) * 1991-10-31 1993-05-22 김광호 어드레스 입력 버퍼
US6072735A (en) * 1998-06-22 2000-06-06 Lucent Technologies, Inc. Built-in redundancy architecture for computer memories
KR100382555B1 (ko) * 2001-03-09 2003-05-09 주식회사 하이닉스반도체 반도체 메모리 소자의 데이터 입출력 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760384A (en) * 1970-10-27 1973-09-18 Cogar Corp Fet memory chip including fet devices therefor and fabrication method
US3806880A (en) * 1971-12-02 1974-04-23 North American Rockwell Multiplexing system for address decode logic
US4050061A (en) * 1976-05-03 1977-09-20 Texas Instruments Incorporated Partitioning of MOS random access memory array
JPS6023432B2 (ja) * 1977-12-09 1985-06-07 株式会社日立製作所 Ｍｏｓメモリ
US4200917A (en) * 1979-03-12 1980-04-29 Motorola, Inc. Quiet column decoder
DE2948159C2 (de) * 1979-11-29 1983-10-27 Siemens AG, 1000 Berlin und 8000 München Integrierter Speicherbaustein mit wählbaren Betriebsfunktionen
JPS57118599U (de) * 1981-01-14 1982-07-23

Also Published As

Publication number Publication date
GB2132799A (en) 1984-07-11
KR840007196A (ko) 1984-12-05
IT8324251A1 (it) 1985-06-19
IT1173689B (it) 1987-06-24
IT8324251A0 (it) 1983-12-19
US4541078A (en) 1985-09-10
ES528170A0 (es) 1984-10-01
ES8407615A1 (es) 1984-10-01
EP0129578A1 (de) 1985-01-02
GB8332967D0 (en) 1984-01-18
WO1984002608A1 (en) 1984-07-05

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Legal Events

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