CA1297992C - Bus d'ordinateur - Google Patents

Bus d'ordinateur

Info

Publication number
CA1297992C
CA1297992C CA000541534A CA541534A CA1297992C CA 1297992 C CA1297992 C CA 1297992C CA 000541534 A CA000541534 A CA 000541534A CA 541534 A CA541534 A CA 541534A CA 1297992 C CA1297992 C CA 1297992C
Authority
CA
Canada
Prior art keywords
path
bus
module
signals
acquisition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA000541534A
Other languages
English (en)
Inventor
Kenneth Charles Yeager
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Concurrent Computer Corp
Original Assignee
Concurrent Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Concurrent Computer Corp filed Critical Concurrent Computer Corp
Application granted granted Critical
Publication of CA1297992C publication Critical patent/CA1297992C/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
CA000541534A 1986-07-07 1987-07-07 Bus d'ordinateur Expired - Lifetime CA1297992C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88230086A 1986-07-07 1986-07-07
US882,300 1986-07-07

Publications (1)

Publication Number Publication Date
CA1297992C true CA1297992C (fr) 1992-03-24

Family

ID=25380295

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000541534A Expired - Lifetime CA1297992C (fr) 1986-07-07 1987-07-07 Bus d'ordinateur

Country Status (6)

Country Link
JP (1) JPS6388665A (fr)
KR (1) KR880002084A (fr)
AU (1) AU612582B2 (fr)
CA (1) CA1297992C (fr)
DE (1) DE3722458A1 (fr)
GB (1) GB2193066B (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008682A (en) * 1996-06-14 1999-12-28 Sun Microsystems, Inc. Circuit and method for selectively enabling ECL type outputs

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4459665A (en) * 1979-01-31 1984-07-10 Honeywell Information Systems Inc. Data processing system having centralized bus priority resolution
GB2060960A (en) * 1979-10-10 1981-05-07 Magnuson Computer Systems Inc Data processing apparatus with parallel encoded priority
CA1179069A (fr) * 1981-04-10 1984-12-04 Yasushi Fukunaga Appareil de transmission de donnees pour systeme multiprocesseur
AU564271B2 (en) * 1983-09-22 1987-08-06 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in a digital computer system
FR2552609B1 (fr) * 1983-09-27 1985-10-25 Cit Alcatel Procede et dispositif de selection d'une station d'un ensemble de stations dialoguant avec une station principale

Also Published As

Publication number Publication date
AU612582B2 (en) 1991-07-18
GB8715422D0 (en) 1987-08-05
JPS6388665A (ja) 1988-04-19
GB2193066A (en) 1988-01-27
GB2193066B (en) 1990-07-04
KR880002084A (ko) 1988-04-29
DE3722458A1 (de) 1988-01-21
AU7525787A (en) 1988-01-14

Similar Documents

Publication Publication Date Title
US4785394A (en) Fair arbitration technique for a split transaction bus in a multiprocessor computer system
US4030075A (en) Data processing system having distributed priority network
US4630193A (en) Time multiplexed processor bus
US4604689A (en) Bus repeater
US3997896A (en) Data processing system providing split bus cycle operation
US4769768A (en) Method and apparatus for requesting service of interrupts by selected number of processors
US3993981A (en) Apparatus for processing data transfer requests in a data processing system
CA1218467A (fr) Mecanisme d'arbitrage pour affecter le controle d'un trajet de communication dans un ordinateur numerique
US4000485A (en) Data processing system providing locked operation of shared resources
US6173349B1 (en) Shared bus system with transaction and destination ID
US4001790A (en) Modularly addressable units coupled in a data processing system over a common bus
US3995258A (en) Data processing system having a data integrity technique
EP0441840B1 (fr) Dispositif pour le partage des ressources d'un ordinateur serveur avec une pluralite d'ordinateurs peripheriques
EP0576240B1 (fr) Système d'ordinateur et unité d'extension de système
EP0524684A2 (fr) Interface universelle à tampon pour le couplage entre plusieurs processeurs, unités de mémoire et interfaces d'entrée/sortie et un bus commun
GB2171542A (en) System employing tightly coupled processors
EP0321628B1 (fr) Interface pour une mémoire commune d'un système de traitement de données
EP0139563A2 (fr) Mécanisme de commande pour système multi-processeur
EP0380926A2 (fr) Dispositif de commande d'arbitrage d'une mémoire à accès libre pour microprocesseurs asynchrones
US4612542A (en) Apparatus for arbitrating between a plurality of requestor elements
KR900001120B1 (ko) 우선도가 낮은 유니트를 우선도가 높은 위치에 위치시키기 위한 분배된 우선도 회로망 로직을 가진 데이타 처리 시스템
Borrill et al. An advanced communication protocol for the proposed IEEE 896 Futurebus
CA1297992C (fr) Bus d'ordinateur
US5590372A (en) VME bus transferring system broadcasting modifiers to multiple devices and the multiple devices simultaneously receiving data synchronously to the modifiers without acknowledging the modifiers
EP0139568B1 (fr) Mécanisme d'interruption à format de messages pour systèmes multi-processeur

Legal Events

Date Code Title Description
MKLA Lapsed
MKLA Lapsed

Effective date: 20030324