JPS6388665A - コンピユ−タバスシステム - Google Patents
コンピユ−タバスシステムInfo
- Publication number
- JPS6388665A JPS6388665A JP62167981A JP16798187A JPS6388665A JP S6388665 A JPS6388665 A JP S6388665A JP 62167981 A JP62167981 A JP 62167981A JP 16798187 A JP16798187 A JP 16798187A JP S6388665 A JPS6388665 A JP S6388665A
- Authority
- JP
- Japan
- Prior art keywords
- route
- module
- signal
- bus
- capture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88230086A | 1986-07-07 | 1986-07-07 | |
| US882300 | 1986-07-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6388665A true JPS6388665A (ja) | 1988-04-19 |
Family
ID=25380295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62167981A Pending JPS6388665A (ja) | 1986-07-07 | 1987-07-07 | コンピユ−タバスシステム |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS6388665A (fr) |
| KR (1) | KR880002084A (fr) |
| AU (1) | AU612582B2 (fr) |
| CA (1) | CA1297992C (fr) |
| DE (1) | DE3722458A1 (fr) |
| GB (1) | GB2193066B (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008682A (en) * | 1996-06-14 | 1999-12-28 | Sun Microsystems, Inc. | Circuit and method for selectively enabling ECL type outputs |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4459665A (en) * | 1979-01-31 | 1984-07-10 | Honeywell Information Systems Inc. | Data processing system having centralized bus priority resolution |
| GB2060960A (en) * | 1979-10-10 | 1981-05-07 | Magnuson Computer Systems Inc | Data processing apparatus with parallel encoded priority |
| CA1179069A (fr) * | 1981-04-10 | 1984-12-04 | Yasushi Fukunaga | Appareil de transmission de donnees pour systeme multiprocesseur |
| AU564271B2 (en) * | 1983-09-22 | 1987-08-06 | Digital Equipment Corporation | Retry mechanism for releasing control of a communications path in a digital computer system |
| FR2552609B1 (fr) * | 1983-09-27 | 1985-10-25 | Cit Alcatel | Procede et dispositif de selection d'une station d'un ensemble de stations dialoguant avec une station principale |
-
1987
- 1987-07-01 GB GB8715422A patent/GB2193066B/en not_active Expired - Lifetime
- 1987-07-06 AU AU75257/87A patent/AU612582B2/en not_active Ceased
- 1987-07-07 CA CA000541534A patent/CA1297992C/fr not_active Expired - Lifetime
- 1987-07-07 DE DE19873722458 patent/DE3722458A1/de not_active Withdrawn
- 1987-07-07 KR KR1019870007223A patent/KR880002084A/ko not_active Ceased
- 1987-07-07 JP JP62167981A patent/JPS6388665A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| AU612582B2 (en) | 1991-07-18 |
| GB8715422D0 (en) | 1987-08-05 |
| GB2193066A (en) | 1988-01-27 |
| GB2193066B (en) | 1990-07-04 |
| KR880002084A (ko) | 1988-04-29 |
| DE3722458A1 (de) | 1988-01-21 |
| CA1297992C (fr) | 1992-03-24 |
| AU7525787A (en) | 1988-01-14 |
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| JPS6218949B2 (fr) | ||
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| WO1981002798A1 (fr) | Systeme d'ordinateur et interface pour celui-ci |