CA1299768C - Systeme de commande d'acces memoire - Google Patents

Systeme de commande d'acces memoire

Info

Publication number
CA1299768C
CA1299768C CA000560407A CA560407A CA1299768C CA 1299768 C CA1299768 C CA 1299768C CA 000560407 A CA000560407 A CA 000560407A CA 560407 A CA560407 A CA 560407A CA 1299768 C CA1299768 C CA 1299768C
Authority
CA
Canada
Prior art keywords
cache memory
mmu
cache
level
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CA000560407A
Other languages
English (en)
Inventor
Ikuo Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to CA000616218A priority Critical patent/CA1313423C/fr
Application granted granted Critical
Publication of CA1299768C publication Critical patent/CA1299768C/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CA000560407A 1987-03-04 1988-03-03 Systeme de commande d'acces memoire Expired - Lifetime CA1299768C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA000616218A CA1313423C (fr) 1987-03-04 1991-11-04 Dispositif de controle de l'acces memoire

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP47705/'87 1987-03-04
JP47706/'87 1987-03-04
JP4770587 1987-03-04
JP4770687 1987-03-04

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CA000616218A Division CA1313423C (fr) 1987-03-04 1991-11-04 Dispositif de controle de l'acces memoire

Publications (1)

Publication Number Publication Date
CA1299768C true CA1299768C (fr) 1992-04-28

Family

ID=26387867

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000560407A Expired - Lifetime CA1299768C (fr) 1987-03-04 1988-03-03 Systeme de commande d'acces memoire

Country Status (2)

Country Link
CA (1) CA1299768C (fr)
FR (1) FR2611938B1 (fr)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4197580A (en) * 1978-06-08 1980-04-08 Bell Telephone Laboratories, Incorporated Data processing system including a cache memory
JPS58189890A (ja) * 1982-04-30 1983-11-05 Hitachi Ltd 階層記憶装置

Also Published As

Publication number Publication date
FR2611938A1 (fr) 1988-09-09
FR2611938B1 (fr) 1994-04-08

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Legal Events

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