CA1313423C - Dispositif de controle de l'acces memoire - Google Patents

Dispositif de controle de l'acces memoire

Info

Publication number: CA1313423C
Authority: CA; Canada
Prior art keywords: cache memory; cache; mmu; address; level
Prior art date: 1987-03-04
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

CA000616218A

Other languages

English (en)

Inventor

Ikuo Yamada

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Corp

Original Assignee

NEC Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1987-03-04

Filing date

1991-11-04

Publication date

1993-02-02

1988-03-03 Priority claimed from CA000560407A external-priority patent/CA1299768C/fr

1991-11-04 Application filed by NEC Corp filed Critical NEC Corp

1993-02-02 Application granted granted Critical

1993-02-02 Publication of CA1313423C publication Critical patent/CA1313423C/fr

2008-03-03 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

238000012545 processing Methods 0.000 abstract description 10
238000012546 transfer Methods 0.000 description 28
238000010586 diagram Methods 0.000 description 6
230000004044 response Effects 0.000 description 4
238000003491 array Methods 0.000 description 2
238000007796 conventional method Methods 0.000 description 1
238000001514 detection method Methods 0.000 description 1
230000006870 function Effects 0.000 description 1
238000012986 modification Methods 0.000 description 1
230000004048 modification Effects 0.000 description 1
238000012544 monitoring process Methods 0.000 description 1
230000002194 synthesizing effect Effects 0.000 description 1

Landscapes

Memory System Of A Hierarchy Structure (AREA)

CA000616218A 1987-03-04 1991-11-04 Dispositif de controle de l'acces memoire Expired - Fee Related CA1313423C (fr)

Applications Claiming Priority (5)

Application Number	Priority Date	Filing Date	Title
JP47706/`87		1987-03-04
JP4770687		1987-03-04
JP47705/`87		1987-03-04
JP4770587		1987-03-04
CA000560407A CA1299768C (fr)	1987-03-04	1988-03-03	Systeme de commande d'acces memoire

Related Parent Applications (1)

Application Number	Title	Priority Date	Filing Date
CA000560407A Division CA1299768C (fr)	1987-03-04	1988-03-03	Systeme de commande d'acces memoire

Publications (1)

Publication Number	Publication Date
CA1313423C true CA1313423C (fr)	1993-02-02

Family

ID=27167892

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
CA000616218A Expired - Fee Related CA1313423C (fr)	1987-03-04	1991-11-04	Dispositif de controle de l'acces memoire

Country Status (1)

Country	Link
CA (1)	CA1313423C (fr)

1991
- 1991-11-04 CA CA000616218A patent/CA1313423C/fr not_active Expired - Fee Related

Similar Documents

Publication	Publication Date	Title
CA1120599A (fr)	1982-03-23	Algorithme de remplacement du bloc utilise le moins recemment
US4996641A (en)	1991-02-26	Diagnostic mode for a cache
US4142234A (en)	1979-02-27	Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system
US5056002A (en)	1991-10-08	Cache memory for use with multiprocessor systems
US4056844A (en)	1977-11-01	Memory control system using plural buffer address arrays
US4626988A (en)	1986-12-02	Instruction fetch look-aside buffer with loop mode control
US5140681A (en)	1992-08-18	Multi-processing system and cache apparatus for use in the same
US4916604A (en)	1990-04-10	Cache storage apparatus
US5778432A (en)	1998-07-07	Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register
US4967414A (en)	1990-10-30	LRU error detection using the collection of read and written LRU bits
US6647463B2 (en)	2003-11-11	Cache update method and cache update control system employing non-blocking type cache
US5206941A (en)	1993-04-27	Fast store-through cache memory
EP0342631A2 (fr)	1989-11-23	Mémoire tampon capable de mémoriser des blocs d'instruction et de données à des dimensions de blocs différentes
KR100758185B1 (ko)	2007-09-13	데이터 처리 장치
JPS6049950B2 (ja)	1985-11-06	Ｌｒｕエラ−処理方式
US5276829A (en)	1994-01-04	Data processing system including cache memory for rapidly converting a logical address into a physical address using shared memory flag
US5692150A (en)	1997-11-25	Cache flash controlling method for cache memory system
US4698754A (en)	1987-10-06	Error detection of scan-out in a diagnostic circuit of a computer
US6240532B1 (en)	2001-05-29	Programmable hit and write policy for cache memory test
JPH0786848B2 (ja)	1995-09-20	キャッシュメモリ
EP0439952A2 (fr)	1991-08-07	Mémoire d'étiquettes d'antémémoire à double porte
CA1313423C (fr)	1993-02-02	Dispositif de controle de l'acces memoire
US6594732B1 (en)	2003-07-15	Computer system with memory system in which cache memory is kept clean
EP0498520A2 (fr)	1992-08-12	Antémémoire de données et procédé de traitement d'erreurs de mémoire pendant réécriture
US4803616A (en)	1989-02-07	Buffer memory

Legal Events

Date	Code	Title	Description
2001-02-02	MKLA	Lapsed