CA2009247A1 - Connexion intermetallique multicouche pour dispositifs a semiconducteur - Google Patents

Connexion intermetallique multicouche pour dispositifs a semiconducteur

Info

Publication number
CA2009247A1
CA2009247A1 CA2009247A CA2009247A CA2009247A1 CA 2009247 A1 CA2009247 A1 CA 2009247A1 CA 2009247 A CA2009247 A CA 2009247A CA 2009247 A CA2009247 A CA 2009247A CA 2009247 A1 CA2009247 A1 CA 2009247A1
Authority
CA
Canada
Prior art keywords
multilayered
semiconductor devices
layer
intermetallic
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2009247A
Other languages
English (en)
Inventor
Kenneth P. Rodbell
Paul A. Totta
James F. White
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2009247A1 publication Critical patent/CA2009247A1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12528—Semiconductor component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12736—Al-base component
    • Y10T428/12743—Next to refractory [Group IVB, VB, or VIB] metal-base component

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
CA2009247A 1989-04-17 1990-02-02 Connexion intermetallique multicouche pour dispositifs a semiconducteur Granted CA2009247A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/339,533 US5071714A (en) 1989-04-17 1989-04-17 Multilayered intermetallic connection for semiconductor devices
US339,533 1989-04-17

Publications (1)

Publication Number Publication Date
CA2009247A1 true CA2009247A1 (fr) 1990-10-17

Family

ID=23329454

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2009247A Granted CA2009247A1 (fr) 1989-04-17 1990-02-02 Connexion intermetallique multicouche pour dispositifs a semiconducteur

Country Status (5)

Country Link
US (1) US5071714A (fr)
EP (1) EP0395560B1 (fr)
JP (1) JPH0752733B2 (fr)
CA (1) CA2009247A1 (fr)
DE (1) DE69014149T2 (fr)

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US5518805A (en) * 1994-04-28 1996-05-21 Xerox Corporation Hillock-free multilayer metal lines for high performance thin film structures
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KR0186206B1 (ko) * 1995-11-21 1999-05-01 구자홍 액정표시소자 및 그의 제조방법
US5582881A (en) * 1996-02-16 1996-12-10 Advanced Micro Devices, Inc. Process for deposition of a Ti/TiN cap layer on aluminum metallization and apparatus
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EP0895278A3 (fr) * 1997-08-01 2000-08-23 Siemens Aktiengesellschaft Procédé de structuration
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US20060252265A1 (en) * 2002-03-06 2006-11-09 Guangxiang Jin Etching high-kappa dielectric materials with good high-kappa foot control and silicon recess control
US6806095B2 (en) 2002-03-06 2004-10-19 Padmapani C. Nallan Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers
US7094704B2 (en) * 2002-05-09 2006-08-22 Applied Materials, Inc. Method of plasma etching of high-K dielectric materials
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US20040007561A1 (en) * 2002-07-12 2004-01-15 Applied Materials, Inc. Method for plasma etching of high-K dielectric materials
US6855643B2 (en) * 2002-07-12 2005-02-15 Padmapani C. Nallan Method for fabricating a gate structure
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JP2009021584A (ja) * 2007-06-27 2009-01-29 Applied Materials Inc 高ｋ材料ゲート構造の高温エッチング方法
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JP6455335B2 (ja) * 2015-06-23 2019-01-23 三菱電機株式会社 半導体装置
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US10761058B2 (en) 2017-02-01 2020-09-01 Seagate Technology Llc Nanostructures to control DNA strand orientation and position location for transverse DNA sequencing
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Also Published As

Publication number Publication date
US5071714A (en) 1991-12-10
EP0395560A2 (fr) 1990-10-31
DE69014149T2 (de) 1995-05-24
JPH0752733B2 (ja) 1995-06-05
EP0395560A3 (fr) 1991-01-02
DE69014149D1 (de) 1994-12-22
JPH02296334A (ja) 1990-12-06
EP0395560B1 (fr) 1994-11-17

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