CA2009472A1 - Systeme de conversion de format pour reseau optique synchrone - Google Patents

Systeme de conversion de format pour reseau optique synchrone

Info

Publication number
CA2009472A1
CA2009472A1 CA2009472A CA2009472A CA2009472A1 CA 2009472 A1 CA2009472 A1 CA 2009472A1 CA 2009472 A CA2009472 A CA 2009472A CA 2009472 A CA2009472 A CA 2009472A CA 2009472 A1 CA2009472 A1 CA 2009472A1
Authority
CA
Canada
Prior art keywords
signals
parallel
signal
stuff bits
latched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2009472A
Other languages
English (en)
Other versions
CA2009472C (fr
Inventor
Hitoshi Eda
Kazumaro Takaiwa
Akihiro Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2009472A1 publication Critical patent/CA2009472A1/fr
Application granted granted Critical
Publication of CA2009472C publication Critical patent/CA2009472C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
CA002009472A 1989-02-08 1990-02-07 Systeme de conversion de format pour reseau optique synchrone Expired - Fee Related CA2009472C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP27488/1989 1989-02-08
JP1027488A JPH0654901B2 (ja) 1989-02-08 1989-02-08 フォーマット変換制御方式

Publications (2)

Publication Number Publication Date
CA2009472A1 true CA2009472A1 (fr) 1990-08-08
CA2009472C CA2009472C (fr) 1993-12-07

Family

ID=12222517

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002009472A Expired - Fee Related CA2009472C (fr) 1989-02-08 1990-02-07 Systeme de conversion de format pour reseau optique synchrone

Country Status (5)

Country Link
US (1) US5030951A (fr)
EP (1) EP0386483B1 (fr)
JP (1) JPH0654901B2 (fr)
CA (1) CA2009472C (fr)
DE (1) DE69002660T2 (fr)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860445A (en) * 1989-02-09 1989-08-29 Gte Products Corporation Method of mounting electrical contacts in connector body
JPH0756968B2 (ja) * 1989-06-23 1995-06-14 日本電気株式会社 多重スタッフ処理回路
US5287360A (en) * 1989-12-27 1994-02-15 Alcatel Cit Device for inserting information bits into a specific frame structure
US5331641A (en) * 1990-07-27 1994-07-19 Transwitch Corp. Methods and apparatus for retiming and realignment of STS-1 signals into STS-3 type signal
US5341376A (en) * 1990-07-27 1994-08-23 Nec Corporation ATM cell format conversion system
DE4035438A1 (de) * 1990-11-08 1992-05-14 Philips Patentverwaltung Schaltungsanordnung zum entfernen von stopfbits
JP2576965Y2 (ja) * 1991-02-08 1998-07-23 日本電気株式会社 通信制御装置
US5638411A (en) * 1991-05-23 1997-06-10 Mitsubishi Denki Kabushiki Kaisha Stuff bit synchronization system
JP2725486B2 (ja) * 1991-06-28 1998-03-11 日本電気株式会社 ポインタ処理回路
CA2078632C (fr) * 1991-09-19 1997-12-30 Tatsuhiko Nakagawa Methode et dispositif de traitement de signaux sts-1 pouvant empecher les equipements terminaux de declencher de fausses alarmes
US5357249A (en) * 1991-10-21 1994-10-18 Trw Inc. Apparatus and method for high speed flexible multiplexing for fiber optic data transmissions
US5272703A (en) * 1991-12-16 1993-12-21 Alcatel Network Systems, Inc. N-bit parallel input to variable-bit parallel output shift register
US5267236A (en) * 1991-12-16 1993-11-30 Alcatel Network Systems, Inc. Asynchronous parallel data formatter
US5235332A (en) * 1991-12-16 1993-08-10 Alcatel Network Systems, Inc. Parallel ds3 aid/idle code generator
JPH05199199A (ja) * 1992-01-20 1993-08-06 Fujitsu Ltd スタッフ同期制御方式
US5327126A (en) * 1992-06-26 1994-07-05 Hewlett-Packard Company Apparatus for and method of parallel justifying and dejustifying data in accordance with a predetermined mapping
AU664097B2 (en) * 1992-06-26 1995-11-02 Hewlett-Packard Australia Limited A justifier and de-justifier
US5285206A (en) * 1992-08-25 1994-02-08 Alcatel Network Systems, Inc. Phase detector for elastic store
US5784377A (en) 1993-03-09 1998-07-21 Hubbell Incorporated Integrated digital loop carrier system with virtual tributary mapper circuit
JPH06334537A (ja) * 1993-05-21 1994-12-02 Fujitsu Ltd 不確定性除去機能付きシリアル／パラレル変換回路
US5548534A (en) * 1994-07-08 1996-08-20 Transwitch Corporation Two stage clock dejitter circuit for regenerating an E4 telecommunications signal from the data component of an STS-3C signal
US5926120A (en) * 1996-03-28 1999-07-20 National Semiconductor Corporation Multi-channel parallel to serial and serial to parallel conversion using a RAM array
US5946327A (en) * 1997-09-09 1999-08-31 3Com Corporation Method and apparatus for converting between a multi-bit TDM bus and a single-bit TDM bus using digital logic
US6128628A (en) * 1998-02-27 2000-10-03 Mci Communication Corporation Meta data processing for converting performance data into a generic format
US7002986B1 (en) * 1999-07-08 2006-02-21 Nortel Networks Limited Mapping arbitrary signals into SONET
US6804265B1 (en) * 2000-05-19 2004-10-12 Cisco Technology, Inc. Apparatus and method interface improvement for digital circuits
US20020103926A1 (en) * 2000-12-19 2002-08-01 Alcatel Usa Sourcing, L.P. Method of transparently transporting sonet STS-3C frame information across a network
US7379723B2 (en) * 2004-07-29 2008-05-27 Silicon Laboratories Inc. Local oscillator and mixer for transceiver
US7349444B2 (en) * 2004-08-23 2008-03-25 Transwitch Corporation SONET/SDH SPE/virtual container retiming with adaptive dual pointer leak rate computation
US7605723B2 (en) * 2004-12-14 2009-10-20 Cirrus Logic, Inc. Circuits and methods for implementing mode selection in multiple-mode integrated circuits
US7372381B2 (en) * 2005-07-01 2008-05-13 Texas Instruments Incorporated Programmable serializer for a video display
JP4729049B2 (ja) * 2005-12-22 2011-07-20 日本電信電話株式会社 光送信器
JP4593677B2 (ja) * 2007-12-21 2010-12-08 富士通株式会社 クロック乗せ換え装置及びクロック乗せ換え方法
KR101691568B1 (ko) * 2009-12-11 2016-12-30 삼성전자주식회사 플립-플롭 회로

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4095053A (en) * 1977-09-01 1978-06-13 Bell Telephone Laboratories, Incorporated Quasi-pulse stuffing synchronization
DE2814081C2 (de) * 1978-04-01 1982-09-30 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Schaltungsanordnung zur Übergabe von seriellen Datenströmen zwischen zwei plesiochron getakteten Systemen
US4347620A (en) * 1980-09-16 1982-08-31 Northern Telecom Limited Method of and apparatus for regenerating a signal frequency in a digital signal transmission system
US4710922A (en) * 1985-12-18 1987-12-01 Advanced Micro Devices, Inc. Apparatus and associated methods for converting serial data pattern signals transmitted or suitable for transmission over a high speed synchronous serial transmission media, to parallel pattern output signals
US4764941A (en) * 1987-05-22 1988-08-16 American Telephone And Telegraph Company, At&T Bell Laboratories Digital frame synchronizer
US4885583A (en) * 1988-11-14 1989-12-05 Chrysler Motors Corporation Serial to parallel data conversion system

Also Published As

Publication number Publication date
US5030951A (en) 1991-07-09
DE69002660D1 (de) 1993-09-16
JPH02207629A (ja) 1990-08-17
CA2009472C (fr) 1993-12-07
EP0386483A1 (fr) 1990-09-12
DE69002660T2 (de) 1993-12-16
EP0386483B1 (fr) 1993-08-11
JPH0654901B2 (ja) 1994-07-20

Similar Documents

Publication Publication Date Title
CA2009472A1 (fr) Systeme de conversion de format pour reseau optique synchrone
EP0477582B1 (fr) Multiplication digitale de la fréquence et circuit pour la conversion en données sérielles
US6150965A (en) Serial to parallel converter enabled by multiplexed flip-flop counters
EP0313875A3 (fr) Circuit convertisseur parallèle/série et série/parallèle
TW357488B (en) Glitch-free clock enable circuit and method for providing a glitch-free clock signal
CA2024809A1 (fr) Appareil de multiplexage et appareil de demultiplexage de signaux numeriques
EP0266790A3 (fr) Interface pour bus série permettant le transfert des données en formats différents
AU3010492A (en) N-bit parallel input to variable-bit parallel output shift register
DE69016063D1 (de) PCM-Übertragungssystem.
EP0548649B1 (fr) Générateur de code DS3 AIS/Repos parallèle
EP0196044A3 (fr) Système d'entrée d'images
CA1120120A (fr) Commande de recherche de cadres pour systeme de transmission digital
US5235603A (en) System for determining loss of activity on a plurality of data lines
GB2146506A (en) Telephone conference bridge circuit arrangements
EP0294614B1 (fr) Circuit pour la conversion d'un code à m bit en un code à n bit
DE3464998D1 (en) Interface arrangement for a telephone system or the like
JPS61140241A (ja) フレ−ム同期復帰方式
KR900001028Y1 (ko) 펄스부호 변조 다중장치의 동기패턴 삽입회로
JPS62112430A (ja) チヤネルパルス発生装置
JPH05292052A (ja) ビット多重／バイト多重変換回路
KR950005611B1 (ko) 비트 인터리빙 다중화된 신호에 대한 채널 번호와 스킵 펄스를 이용한 리프레임 회로
JPS55136907A (en) Sample holding circuit
JPS58131816A (ja) 同期パタ−ン発生回路
JPS5619144A (en) Digital comparison circuit
JPS6471348A (en) Signal processing circuit

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed