CA2024784A1 - Substrat multicouche empilable pour le montage des circuits integres - Google Patents

Substrat multicouche empilable pour le montage des circuits integres

Info

Publication number
CA2024784A1
CA2024784A1 CA2024784A CA2024784A CA2024784A1 CA 2024784 A1 CA2024784 A1 CA 2024784A1 CA 2024784 A CA2024784 A CA 2024784A CA 2024784 A CA2024784 A CA 2024784A CA 2024784 A1 CA2024784 A1 CA 2024784A1
Authority
CA
Canada
Prior art keywords
substrate
ics
integrated circuits
multilayer substrate
mounting integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2024784A
Other languages
English (en)
Other versions
CA2024784C (fr
Inventor
Keith O. Warren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northrop Grumman Guidance and Electronics Co Inc
Original Assignee
Litton Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Litton Systems Inc filed Critical Litton Systems Inc
Publication of CA2024784A1 publication Critical patent/CA2024784A1/fr
Application granted granted Critical
Publication of CA2024784C publication Critical patent/CA2024784C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
CA002024784A 1989-09-14 1990-09-06 Substrat multicouche empilable pour le montage des circuits integres Expired - Fee Related CA2024784C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US407,045 1989-09-14
US07/407,045 US5006923A (en) 1989-09-14 1989-09-14 Stackable multilayer substrate for mounting integrated circuits

Publications (2)

Publication Number Publication Date
CA2024784A1 true CA2024784A1 (fr) 1991-03-15
CA2024784C CA2024784C (fr) 1994-01-04

Family

ID=23610383

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002024784A Expired - Fee Related CA2024784C (fr) 1989-09-14 1990-09-06 Substrat multicouche empilable pour le montage des circuits integres

Country Status (5)

Country Link
US (1) US5006923A (fr)
EP (1) EP0417992B1 (fr)
JP (1) JP2796886B2 (fr)
CA (1) CA2024784C (fr)
DE (1) DE69030223T2 (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227338A (en) * 1990-04-30 1993-07-13 International Business Machines Corporation Three-dimensional memory card structure with internal direct chip attachment
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
WO1992022090A1 (fr) * 1991-06-03 1992-12-10 Motorola, Inc. Ensemble electronique thermoconducteur
US5285108A (en) * 1991-06-21 1994-02-08 Compaq Computer Corporation Cooling system for integrated circuits
US5241454A (en) * 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package
US6080596A (en) * 1994-06-23 2000-06-27 Cubic Memory Inc. Method for forming vertical interconnect process for silicon segments with dielectric isolation
US6124633A (en) * 1994-06-23 2000-09-26 Cubic Memory Vertical interconnect process for silicon segments with thermally conductive epoxy preform
US5698895A (en) * 1994-06-23 1997-12-16 Cubic Memory, Inc. Silicon segment programming method and apparatus
US6255726B1 (en) 1994-06-23 2001-07-03 Cubic Memory, Inc. Vertical interconnect process for silicon segments with dielectric isolation
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US6486528B1 (en) 1994-06-23 2002-11-26 Vertical Circuits, Inc. Silicon segment programming apparatus and three terminal fuse configuration
DE19627543B9 (de) * 1996-05-18 2004-10-14 Thomas Hofmann Multi-Layer-Substrat sowie Verfahren zu seiner Herstellung
US5801108A (en) * 1996-09-11 1998-09-01 Motorola Inc. Low temperature cofireable dielectric paste
US6016005A (en) * 1998-02-09 2000-01-18 Cellarosi; Mario J. Multilayer, high density micro circuit module and method of manufacturing same
US20030041966A1 (en) * 2001-08-31 2003-03-06 International Business Machines Corporation Method of joining laminates for z-axis interconnection
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7705432B2 (en) * 2004-04-13 2010-04-27 Vertical Circuits, Inc. Three dimensional six surface conformal die coating
US9109831B2 (en) 2007-07-11 2015-08-18 AIR LIQUIDE GLOBAL E&C SOLUTIONS US Inc. Process and apparatus for the separation of a gaseous mixture

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3704455A (en) * 1971-02-01 1972-11-28 Alfred D Scarbrough 3d-coaxial memory construction and method of making
CA977451A (en) * 1972-04-27 1975-11-04 Bunker Ramo Corporation Electrical circuit packaging structure and method of fabrication thereof
JPS5990183A (ja) * 1982-11-15 1984-05-24 Sony Corp カ−ド
JPS60164959A (ja) * 1984-02-08 1985-08-28 Teac Co 磁気デイスク装置
US4680617A (en) * 1984-05-23 1987-07-14 Ross Milton I Encapsulated electronic circuit device, and method and apparatus for making same
JPS60252992A (ja) * 1984-05-30 1985-12-13 Toshiba Corp Ｉｃカ−ド
JPS6134990A (ja) * 1984-07-25 1986-02-19 イビデン株式会社 電子部品搭載用基板およびその製造方法
US4709468A (en) * 1986-01-31 1987-12-01 Texas Instruments Incorporated Method for producing an integrated circuit product having a polyimide film interconnection structure
JPS635999A (ja) * 1986-06-27 1988-01-11 株式会社東芝 カ−ド型電子回路ユニツト
JPS6457653A (en) * 1987-08-27 1989-03-03 Fujitsu Ltd Mounting structure of hybrid integrated circuit component

Also Published As

Publication number Publication date
EP0417992A3 (en) 1991-08-07
JPH03183195A (ja) 1991-08-09
US5006923A (en) 1991-04-09
DE69030223D1 (de) 1997-04-24
EP0417992B1 (fr) 1997-03-19
EP0417992A2 (fr) 1991-03-20
JP2796886B2 (ja) 1998-09-10
CA2024784C (fr) 1994-01-04
DE69030223T2 (de) 1997-07-03

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed