CA2056046A1 - Circuit d'interfacage d'une multiplicite de lignes de transmission et d'un equipement terminal de transmission de donnees a debit binaire eleve - Google Patents

Circuit d'interfacage d'une multiplicite de lignes de transmission et d'un equipement terminal de transmission de donnees a debit binaire eleve

Info

Publication number
CA2056046A1
CA2056046A1 CA2056046A CA2056046A CA2056046A1 CA 2056046 A1 CA2056046 A1 CA 2056046A1 CA 2056046 A CA2056046 A CA 2056046A CA 2056046 A CA2056046 A CA 2056046A CA 2056046 A1 CA2056046 A1 CA 2056046A1
Authority
CA
Canada
Prior art keywords
channels
receiving
data
clock signals
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2056046A
Other languages
English (en)
Other versions
CA2056046C (fr
Inventor
Keisuke Okuzono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2327303A external-priority patent/JPH04175028A/ja
Application filed by Individual filed Critical Individual
Publication of CA2056046A1 publication Critical patent/CA2056046A1/fr
Application granted granted Critical
Publication of CA2056046C publication Critical patent/CA2056046C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)
CA002056046A 1990-11-27 1991-11-22 Circuit d'interfacage d'une multiplicite de lignes de transmission et d'un equipement terminal de transmission de donnees a debit binaire eleve Expired - Fee Related CA2056046C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2327303A JPH04175028A (ja) 1990-07-23 1990-11-27 多チャネル接続装置の伝送路インタフェース回路
JP02-327303 1990-11-27

Publications (2)

Publication Number Publication Date
CA2056046A1 true CA2056046A1 (fr) 1992-05-28
CA2056046C CA2056046C (fr) 1996-02-27

Family

ID=18197625

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002056046A Expired - Fee Related CA2056046C (fr) 1990-11-27 1991-11-22 Circuit d'interfacage d'une multiplicite de lignes de transmission et d'un equipement terminal de transmission de donnees a debit binaire eleve

Country Status (3)

Country Link
US (1) US5268932A (fr)
EP (1) EP0488212A3 (fr)
CA (1) CA2056046C (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5832047A (en) * 1994-06-17 1998-11-03 International Business Machines Corporation Self timed interface
JP3681225B2 (ja) * 1996-07-31 2005-08-10 富士通株式会社 シンクロナイゼイション・メッセージ送信装置
US6765954B1 (en) * 1999-08-16 2004-07-20 Globespanvirata, Inc. System and method for implementing a delta-sigma modulator integrity supervisor
US6577649B1 (en) * 1999-11-12 2003-06-10 International Business Machines Corporation Multiplexer for asynchronous data
US6901526B1 (en) * 2000-11-08 2005-05-31 Intel Corporation Digital bus synchronizer for generating read reset signal
US6807232B2 (en) * 2000-12-21 2004-10-19 National Instruments Corporation System and method for multiplexing synchronous digital data streams
WO2003047134A2 (fr) * 2001-11-28 2003-06-05 Bridgeco Ag Procede de synchronisation dans des reseaux
US7593288B2 (en) * 2007-12-19 2009-09-22 International Business Machines Corporation System for providing read clock sharing between memory devices
JP6467159B2 (ja) * 2014-07-25 2019-02-06 ローム株式会社 パラレルインタフェースおよび集積回路
FR3094593B1 (fr) * 2019-03-29 2021-02-19 Teledyne E2V Semiconductors Sas Procédé de synchronisation de données numériques envoyées en série

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4811642B1 (fr) * 1966-11-19 1973-04-14
US4133981A (en) * 1977-12-19 1979-01-09 Bell Telephone Laboratories, Incorporated Time correction circuit for a digital multiplexer
JPS5841019B2 (ja) * 1979-06-06 1983-09-09 富士通株式会社 回線多重化装置の２重化切替方式
US4943942A (en) * 1986-09-19 1990-07-24 Advanced Micro Devices Full-duplex modem using a single processor
EP0343156A1 (fr) * 1987-01-12 1989-11-29 Motorola, Inc. Systeme radio a frequences multiples utilisant des translateurs d'impulsions
JPH0817374B2 (ja) * 1987-11-25 1996-02-21 日本電気株式会社 クロツク伝送方法
JPH0440030A (ja) * 1990-06-05 1992-02-10 Mitsubishi Electric Corp 信号送受信装置

Also Published As

Publication number Publication date
EP0488212A2 (fr) 1992-06-03
EP0488212A3 (en) 1993-03-17
CA2056046C (fr) 1996-02-27
US5268932A (en) 1993-12-07

Similar Documents

Publication Publication Date Title
CA2024809A1 (fr) Appareil de multiplexage et appareil de demultiplexage de signaux numeriques
CA2271046A1 (fr) Synchronisation multi-trames pour transmissions par voies paralleles
ES8602328A1 (es) Una instalacion de lectura de medida de servicios publicos, de aplicacion especial a lineas telefonicas
US5550874A (en) Clock synchronizing circuit of data transmission system
CA2056046A1 (fr) Circuit d'interfacage d'une multiplicite de lignes de transmission et d'un equipement terminal de transmission de donnees a debit binaire eleve
US4757521A (en) Synchronization method and apparatus for a telephone switching system
ZA803661B (en) Synchronisation in communication systems
US4791628A (en) High-speed demultiplexer circuit
US4451917A (en) Method and apparatus for pulse train synchronization in PCM transceivers
CA2330012A1 (fr) Port de concentrateur ne transferant pas la gigue
US4105869A (en) Time-division multiplex digital transmission system with intermediate stations adapted to transit insert and extract digital channels
US4792949A (en) Service channel circuit for multiplexed telecommunications transmission systems
EP0112697A2 (fr) Système de codage prioritaire
US5260977A (en) Communication terminal equipment
CA2243450A1 (fr) Synchronisation avec un systeme externe
TW347621B (en) Method and arrangement for increasing data transmisssion rate over telephone cable
US4847836A (en) Circuit arrangement for synchronizing the units in the switching exchanges and repeaters of a time-division multiplex transmission system
US4730309A (en) Data transmission station
US4107468A (en) Digital train processing device
JP2669844B2 (ja) 多重アクセス制御方式
JPS59502009A (ja) パケツト形式の高速デ−タを受信する装置
KR950014624B1 (ko) 피씨엠 음성신호 교환장치
CA2014489A1 (fr) Dispositif d'acces a des canaux
JPH02121541A (ja) チャンネルアクセス方式
KR0111694Y1 (ko) 다수채널 pcm데이타 제어회로

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed
MKLA Lapsed

Effective date: 19971124