CA2088779A1 - Performance d'ordinateur obtenue par simulation d'associativite d'antememoire - Google Patents

Performance d'ordinateur obtenue par simulation d'associativite d'antememoire

Info

Publication number
CA2088779A1
CA2088779A1 CA2088779A CA2088779A CA2088779A1 CA 2088779 A1 CA2088779 A1 CA 2088779A1 CA 2088779 A CA2088779 A CA 2088779A CA 2088779 A CA2088779 A CA 2088779A CA 2088779 A1 CA2088779 A1 CA 2088779A1
Authority
CA
Canada
Prior art keywords
cache
addresses
thrashing
page
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2088779A
Other languages
English (en)
Other versions
CA2088779C (fr
Inventor
Richard L. Sites
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2088779A1 publication Critical patent/CA2088779A1/fr
Application granted granted Critical
Publication of CA2088779C publication Critical patent/CA2088779C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/653—Page colouring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L'invention est un système informatique utilisant l'adressage en mémoire virtuelle et comportant une antémémoire à correspondance directe qui est exploitée de façon à simuler l'effet d'une antémémoire associative en détectant les ratés et les pages de remise en correspondance dans la mémoire principale de façon que les références mémoire qui auraient causé un emballement puissent coexister dans l'antémémoire. Deux adresses mémoire se trouvant sur des pages différentes, mais en correspondance avec le même emplacement dans l'antémémoire ne peuvent résider simultanément dans l'antémémoire à correspondance directe, de sorte que des renvois à ces deux adresses par une tâche exécutée sur l'unité centrale causeraient un emballement. Toutefois, si l'emplacement de l'une de ces adresses dans la mémoire principale est modifié, les données qui ont ces adresses peuvent coexister dans l'antémémoire et la performance sera sensiblement améliorée parce qu'il n'y aura pas d'emballement. Dans une unité centrale à système d'exploitation à mémoire virtuelle, une page de données ou d'instructions peut être transportée sur un cadre de page physique différent, et conserver la même adresse virtuelle. Ceci se fait simplement en mettant à jour les tables de mise en correspondance des pages avec le nouvel emplacement physique de la page en cause et en copiant les données de l'ancien cadre de page dans le nouveau. La condition d'emballement est détectée et est corrigée dynamiquement en introduisant dans une bascule les adresses des ratés dans l'antémémoire et en échantillonnant périodiquement cette bascule, les pages de remise en correspondance contenant les adresses trouvées au moment de l'échantillonnage. L'antémémoire à correspondance directe doit avoir une capacité suffisante pour recevoir deux pages ou plus.
CA002088779A 1991-06-17 1992-05-21 Performance d'ordinateur obtenue par simulation d'associativite d'antememoire Expired - Fee Related CA2088779C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71639791A 1991-06-17 1991-06-17
US716,397 1991-06-17

Publications (2)

Publication Number Publication Date
CA2088779A1 true CA2088779A1 (fr) 1992-12-18
CA2088779C CA2088779C (fr) 1998-09-01

Family

ID=24877837

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002088779A Expired - Fee Related CA2088779C (fr) 1991-06-17 1992-05-21 Performance d'ordinateur obtenue par simulation d'associativite d'antememoire

Country Status (12)

Country Link
US (1) US5442571A (fr)
EP (1) EP0543991B1 (fr)
JP (1) JPH07104816B2 (fr)
KR (1) KR960005443B1 (fr)
AU (1) AU658914B2 (fr)
CA (1) CA2088779C (fr)
DE (1) DE69229667T2 (fr)
IE (1) IE921691A1 (fr)
IL (1) IL102001A (fr)
MX (1) MX9202907A (fr)
TW (1) TW219986B (fr)
WO (1) WO1992022867A1 (fr)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
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FR2688612A1 (fr) * 1992-03-13 1993-09-17 Inst Nat Rech Inf Automat Dispositif d'antememoire.
US5732409A (en) * 1994-03-21 1998-03-24 Legend Research Limited Caching disk controller implemented by hardwired logic
US6129458A (en) * 1994-03-23 2000-10-10 At&T Global Information Solutions Company Cache optimization method
US6223255B1 (en) 1995-02-03 2001-04-24 Lucent Technologies Microprocessor with an instruction level reconfigurable n-way cache
US5845106A (en) * 1996-01-26 1998-12-01 Advanced Micro Devices, Inc. Method for simulating cache operation
US5752261A (en) * 1996-11-07 1998-05-12 Ncr Corporation Method and apparatus for detecting thrashing in a cache memory
US6301641B1 (en) * 1997-02-27 2001-10-09 U.S. Philips Corporation Method for reducing the frequency of cache misses in a computer
KR100231707B1 (ko) * 1997-08-04 2000-01-15 정선종 통신 장비의 디엠에이 처리 방법 및 그 장치
US6209062B1 (en) * 1997-11-24 2001-03-27 Intel Corporation Method for holding cache pages that are not invalidated within normal time duration for a second access or that are likely to be accessed again soon
US6446170B1 (en) * 1999-01-19 2002-09-03 International Business Machines Corporation Efficient store machine in cache based microprocessor
US6408368B1 (en) 1999-06-15 2002-06-18 Sun Microsystems, Inc. Operating system page placement to maximize cache data reuse
US6366994B1 (en) * 1999-06-22 2002-04-02 Sun Microsystems, Inc. Cache aware memory allocation
JP2001109661A (ja) 1999-10-14 2001-04-20 Hitachi Ltd キャッシュメモリの割当方法及びオペレーティングシステム及びそのオペレーティングシステムを有するコンピュータシステム
US6523092B1 (en) * 2000-09-29 2003-02-18 Intel Corporation Cache line replacement policy enhancement to avoid memory page thrashing
US6947052B2 (en) * 2001-07-13 2005-09-20 Texas Instruments Incorporated Visual program memory hierarchy optimization
GB2381886B (en) * 2001-11-07 2004-06-23 Sun Microsystems Inc Computer system with virtual memory and paging mechanism
US7373480B2 (en) * 2004-11-18 2008-05-13 Sun Microsystems, Inc. Apparatus and method for determining stack distance of running software for estimating cache miss rates based upon contents of a hash table
US7366871B2 (en) 2004-11-18 2008-04-29 Sun Microsystems, Inc. Apparatus and method for determining stack distance including spatial locality of running software for estimating cache miss rates based upon contents of a hash table
JP2007272691A (ja) * 2006-03-31 2007-10-18 Fujitsu Ltd プロセッサ装置およびスラッシング回避方法
US8806461B2 (en) * 2007-06-21 2014-08-12 Microsoft Corporation Using memory usage to pinpoint sub-optimal code for gaming systems
US9619396B2 (en) * 2015-03-27 2017-04-11 Intel Corporation Two level memory full line writes
US10310811B2 (en) 2017-03-31 2019-06-04 Hewlett Packard Enterprise Development Lp Transitioning a buffer to be accessed exclusively by a driver layer for writing immediate data stream
CN111666230B (zh) * 2020-05-27 2023-08-01 江苏华创微系统有限公司 在组相联tlb中支持巨页的方法
US12271318B2 (en) * 2020-12-28 2025-04-08 Advanced Micro Devices, Inc. Method and apparatus for managing a cache directory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5119290A (en) * 1987-10-02 1992-06-02 Sun Microsystems, Inc. Alias address support
US5210843A (en) * 1988-03-25 1993-05-11 Northern Telecom Limited Pseudo set-associative memory caching arrangement
JPH02273843A (ja) * 1989-04-14 1990-11-08 Nec Corp スワッピング装置
US5101485B1 (en) * 1989-06-29 1996-12-10 Frank L Perazzoli Jr Virtual memory page table paging apparatus and method

Also Published As

Publication number Publication date
AU658914B2 (en) 1995-05-04
IE921691A1 (en) 1992-12-30
CA2088779C (fr) 1998-09-01
TW219986B (fr) 1994-02-01
IL102001A0 (en) 1992-12-30
WO1992022867A1 (fr) 1992-12-23
EP0543991B1 (fr) 1999-07-28
US5442571A (en) 1995-08-15
DE69229667T2 (de) 2000-02-10
AU2247492A (en) 1993-01-12
JPH05509189A (ja) 1993-12-16
EP0543991A1 (fr) 1993-06-02
JPH07104816B2 (ja) 1995-11-13
KR960005443B1 (ko) 1996-04-25
MX9202907A (es) 1993-03-01
IL102001A (en) 1996-01-31
DE69229667D1 (de) 1999-09-02

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