CA2189733A1 - Integrated circuit leadframe with reduced inductance pin connections - Google Patents
Integrated circuit leadframe with reduced inductance pin connectionsInfo
- Publication number
- CA2189733A1 CA2189733A1 CA002189733A CA2189733A CA2189733A1 CA 2189733 A1 CA2189733 A1 CA 2189733A1 CA 002189733 A CA002189733 A CA 002189733A CA 2189733 A CA2189733 A CA 2189733A CA 2189733 A1 CA2189733 A1 CA 2189733A1
- Authority
- CA
- Canada
- Prior art keywords
- die attach
- integrated circuit
- attach paddle
- leadframe
- down bond
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
An integrated circuit leadframe having a die attach paddle which is perforated at each wire down bond site. The plastic molding compound used to encapsulate the IC flows through the perforation(s). The solidified molding compound extends through the die attach paddle to resist potential delamination and consequential breakage of the down bond. The die attach paddle's surface may alternatively be dimpled, serrated, or otherwise roughened to improve adhesion of the molding compound at each down bond site and thereby resist delamination of the molding compound at such sites. As a further alternative, each leadframe lead selected for use as a power or ground connection may be directly connected to the die attach paddle, and a wire bonded from each such lead to the integrated circuit in order to form a low inductance electrical connection between the integrated circuit and each power or ground lead.
Description
INTEGRATED CIRCUIT LEADFRAME
WITH R~ N~lANcE PIN CONNECTIONS
Field of the Invention This application is directed to prevention of delamination of plastic molding compound at specific sites on an integrated circuit (IC) leadframe. Sites of particu-lar concern are those at which wire bonds are formed on the die attach paddle to provide a low inductance path from the IC to external ground.
Background of the Invention Mixed signal integrated circuits (ICs) are subject to switching noise, which affects the digital ground and power supply signals. Such noise can be coupled into analog portions of the circuitry, which are especially sensitive to noise. To reduce such coupling, circuit designers commonly provide an extremely low inductance path for conducting digital switching currents to an external ground plane.
The self-inductance of the leads in a typical IC
package can range from 5 to 10 nH per lead. To minimize noise levels within an acceptable range, a large number of leads must typically be dedicated to power and ground functions. Moreover, these leads must be allocated in a specific geometric pattern to avoid reductions in perform-ance, thus limiting flexibility in pin assignment.
In many plastic IC packages, the die attach paddle or "DAP" (the portion of the leadframe to which the IC chip is attached) is connected with thick tie bars to a number of corner leads to improve the thermal performance of the package. The tie bars are normally connected to an external ground plane. The symmetry of the configuration and the width of the tie bars ensures a very low inductance between the DAP and the external ground plane (typically less than 2 nH). Bond wires are then used to connect the IC bond pads to the DAP. These "down bonds" provide a more direct, lower inductance path from the IC to external ground, without requiring a large number of dedicated leads on the package, and without seriously restricting the pin assignment.
Modern, plastic encapsulated IC packages suffer from moisture absorption and retention, which can cause the molding compound to delaminate from the leadframe during board assembly. Such delamination does not affect relia-bility of standard packages if the delamination does not occur at a down bond site. However, delamination most often occurs at relatively large, unbroken areas of plated leadframe, due to the relatively low shear strength of the molding compound at the plated leadframe surfaces. The DAP
outside of the IC die periphery (the area in which down bonds are made) is such an area. Down bonds are thus at high risk from a reliability perspective, since delamina-tion of the molding compound from the DAP in the vicinityof a down bond may cause delamination of the down bond as well, thus breaking the down bond connection.
The present invention improves down bond relia-bility by enhancing the resistance of down bond sites to delamination of the molding compound from the leadframe.
Summary of the Invention In accordance with a first embodiment, the invention provides a leadframe in which the DAP is perfor-ated at each down bond site. The plastic molding compoundused to encapsulate the IC flows through the perfora-tion(s). The solidified molding compound extends through the DAP in the region of reliability concern to resist potential delamination and consequential breakage of the down bond.
Instead of perforating the DAP, one may alterna-tively dimple, serrate, or otherwise roughen the DAP's surface to improve adhesion of the molding compound at each down bond site and thereby resist delamination of the molding compound at such sites.
In accordance with a further embodiment of the invention, each leadframe lead selected for use as a power 21897~3 or ground connection is directly connected to the DAP via leadframe metal. A wire is bonded from each such lead to the IC in order to form a low inductance electrical connec-tion between the IC and the power/ground leads.
Brief Description of the Drawinqs Figure 1 is an enlarged, plan view of a portion of a prior art integrated circuit leadframe.
Figure 2 is a greatly enlarged side elevation~0 view of a typical prior art two wire down bond connection.
Figure 3 iS an enlarged, plan view of a portion of an integrated circuit leadframe constructed in accord-ance with a first embodiment of the invention.
Figures 4(a) and 4 (b) are respectively top plan 15 and side elevation views (both on a greatly enlarged scale) of a two wire down bond connection according to the first embodiment of the invention.
Figure 5 is a greatly enlarged side elevation view of a single wire down bond connection according to a 20 second embodiment of the invention.
Detailed Description of the Preferred Embodiment Figures 1 and 2 depict a typical bonding diagram for a thermally enhanced prior art leadframe. IC 10 is 25 coupled to package leads (i.e. leadframe) 12 by wires 14 which are connected between respective pairs of leads 12 and IC bond pads 16. Corner tie bar 18 connects DAP 20 to an external ground plane (not shown). Figure 1 shows two prior art down bonds 22, one of which appears in Figure 2 30 in side elevation and on a greatly magnified scale.
As best seen in Figure 2, each down bond 22 incorporates first and second bonding wires 26, 24. First wire 26 is bonded at one end to IC bond pad 16 and at its opposite end to DAP 20. Second wire 24 is bonded at one 35 end to leadframe 12 and at its opposite end to DAP 20.
From a reliability standpoint, the region of concern is the portion of DAP to which wires 24, 26 are bonded. If the 21897~
plastic molding compound which encapsulates IC 10, lead-frame 12 and DAP 20 delaminates in this region then the bonding of either or both of wires 24, 26 to DAP 20 may be broken, thus breaking the electrical connection between IC
bond pad 16 and leadframe 12.
Figures 3, 4 (a) and 4 (b) depict a leadframe modified in accordance with one embodiment of the present invention. A plurality of perforations 28 are provided in DAP 20 at each down bond site, before attachment of the bonding wires. When IC 10, leadframe 12 and DAP 20 are encapsulated with plastic molding compound, the compound flows through perforations 28 and solidifies. The molding compound thus extends through DAP 20 in the region of reliability concern, significantly improving that region's resistance to potential delamination of the molding com-pound and consequential breakage of the down bond. Perfor-ations 28 may be made on either stamped or etched lead-frames through simple tooling changes.
Figure 5 depicts a second embodiment of the invention in which the leadframe is modified by bridging additional leadframe material 30 between package lead 12 and DAP 20. In other words, package lead 12 is connected directly to DAP 20 with low inductance. A single bonding wire 32 iS bonded at one end to IC bond pad 16 and at its opposite end to package lead 12.
Note that either lower inductance or fewer required ground connections or a trade off between both goals may be achieved with any of these techniques.
As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. For example, instead of providing perforations 28 in the first embodiment of the invention, one could alter-natively provide dimples, serrations, protrusions, orsimilar surface roughening characteristics on DAP 20 in the down bond region in order to improve adhesion of the 21897~3 molding compound and resist delamination of the compound from the leadframe. Such surface modifications may be made either chemically (i.e. etching or roughening) or mechan-ically (i.e. stamping, cutting, scratching, etc.). As a further alternative, one may provide additional wire bonds made directly to the thermal leads at the tie bar, if the chip has power and ground pads located in immediate proxim-ity. Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims.
WITH R~ N~lANcE PIN CONNECTIONS
Field of the Invention This application is directed to prevention of delamination of plastic molding compound at specific sites on an integrated circuit (IC) leadframe. Sites of particu-lar concern are those at which wire bonds are formed on the die attach paddle to provide a low inductance path from the IC to external ground.
Background of the Invention Mixed signal integrated circuits (ICs) are subject to switching noise, which affects the digital ground and power supply signals. Such noise can be coupled into analog portions of the circuitry, which are especially sensitive to noise. To reduce such coupling, circuit designers commonly provide an extremely low inductance path for conducting digital switching currents to an external ground plane.
The self-inductance of the leads in a typical IC
package can range from 5 to 10 nH per lead. To minimize noise levels within an acceptable range, a large number of leads must typically be dedicated to power and ground functions. Moreover, these leads must be allocated in a specific geometric pattern to avoid reductions in perform-ance, thus limiting flexibility in pin assignment.
In many plastic IC packages, the die attach paddle or "DAP" (the portion of the leadframe to which the IC chip is attached) is connected with thick tie bars to a number of corner leads to improve the thermal performance of the package. The tie bars are normally connected to an external ground plane. The symmetry of the configuration and the width of the tie bars ensures a very low inductance between the DAP and the external ground plane (typically less than 2 nH). Bond wires are then used to connect the IC bond pads to the DAP. These "down bonds" provide a more direct, lower inductance path from the IC to external ground, without requiring a large number of dedicated leads on the package, and without seriously restricting the pin assignment.
Modern, plastic encapsulated IC packages suffer from moisture absorption and retention, which can cause the molding compound to delaminate from the leadframe during board assembly. Such delamination does not affect relia-bility of standard packages if the delamination does not occur at a down bond site. However, delamination most often occurs at relatively large, unbroken areas of plated leadframe, due to the relatively low shear strength of the molding compound at the plated leadframe surfaces. The DAP
outside of the IC die periphery (the area in which down bonds are made) is such an area. Down bonds are thus at high risk from a reliability perspective, since delamina-tion of the molding compound from the DAP in the vicinityof a down bond may cause delamination of the down bond as well, thus breaking the down bond connection.
The present invention improves down bond relia-bility by enhancing the resistance of down bond sites to delamination of the molding compound from the leadframe.
Summary of the Invention In accordance with a first embodiment, the invention provides a leadframe in which the DAP is perfor-ated at each down bond site. The plastic molding compoundused to encapsulate the IC flows through the perfora-tion(s). The solidified molding compound extends through the DAP in the region of reliability concern to resist potential delamination and consequential breakage of the down bond.
Instead of perforating the DAP, one may alterna-tively dimple, serrate, or otherwise roughen the DAP's surface to improve adhesion of the molding compound at each down bond site and thereby resist delamination of the molding compound at such sites.
In accordance with a further embodiment of the invention, each leadframe lead selected for use as a power 21897~3 or ground connection is directly connected to the DAP via leadframe metal. A wire is bonded from each such lead to the IC in order to form a low inductance electrical connec-tion between the IC and the power/ground leads.
Brief Description of the Drawinqs Figure 1 is an enlarged, plan view of a portion of a prior art integrated circuit leadframe.
Figure 2 is a greatly enlarged side elevation~0 view of a typical prior art two wire down bond connection.
Figure 3 iS an enlarged, plan view of a portion of an integrated circuit leadframe constructed in accord-ance with a first embodiment of the invention.
Figures 4(a) and 4 (b) are respectively top plan 15 and side elevation views (both on a greatly enlarged scale) of a two wire down bond connection according to the first embodiment of the invention.
Figure 5 is a greatly enlarged side elevation view of a single wire down bond connection according to a 20 second embodiment of the invention.
Detailed Description of the Preferred Embodiment Figures 1 and 2 depict a typical bonding diagram for a thermally enhanced prior art leadframe. IC 10 is 25 coupled to package leads (i.e. leadframe) 12 by wires 14 which are connected between respective pairs of leads 12 and IC bond pads 16. Corner tie bar 18 connects DAP 20 to an external ground plane (not shown). Figure 1 shows two prior art down bonds 22, one of which appears in Figure 2 30 in side elevation and on a greatly magnified scale.
As best seen in Figure 2, each down bond 22 incorporates first and second bonding wires 26, 24. First wire 26 is bonded at one end to IC bond pad 16 and at its opposite end to DAP 20. Second wire 24 is bonded at one 35 end to leadframe 12 and at its opposite end to DAP 20.
From a reliability standpoint, the region of concern is the portion of DAP to which wires 24, 26 are bonded. If the 21897~
plastic molding compound which encapsulates IC 10, lead-frame 12 and DAP 20 delaminates in this region then the bonding of either or both of wires 24, 26 to DAP 20 may be broken, thus breaking the electrical connection between IC
bond pad 16 and leadframe 12.
Figures 3, 4 (a) and 4 (b) depict a leadframe modified in accordance with one embodiment of the present invention. A plurality of perforations 28 are provided in DAP 20 at each down bond site, before attachment of the bonding wires. When IC 10, leadframe 12 and DAP 20 are encapsulated with plastic molding compound, the compound flows through perforations 28 and solidifies. The molding compound thus extends through DAP 20 in the region of reliability concern, significantly improving that region's resistance to potential delamination of the molding com-pound and consequential breakage of the down bond. Perfor-ations 28 may be made on either stamped or etched lead-frames through simple tooling changes.
Figure 5 depicts a second embodiment of the invention in which the leadframe is modified by bridging additional leadframe material 30 between package lead 12 and DAP 20. In other words, package lead 12 is connected directly to DAP 20 with low inductance. A single bonding wire 32 iS bonded at one end to IC bond pad 16 and at its opposite end to package lead 12.
Note that either lower inductance or fewer required ground connections or a trade off between both goals may be achieved with any of these techniques.
As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. For example, instead of providing perforations 28 in the first embodiment of the invention, one could alter-natively provide dimples, serrations, protrusions, orsimilar surface roughening characteristics on DAP 20 in the down bond region in order to improve adhesion of the 21897~3 molding compound and resist delamination of the compound from the leadframe. Such surface modifications may be made either chemically (i.e. etching or roughening) or mechan-ically (i.e. stamping, cutting, scratching, etc.). As a further alternative, one may provide additional wire bonds made directly to the thermal leads at the tie bar, if the chip has power and ground pads located in immediate proxim-ity. Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims.
Claims (6)
1. An integrated circuit leadframe having a die attach paddle, a plurality of selected package leads and an equal plurality of down bond sites on said die attach paddle for bonding, at each one of said sites, of wires forming low inductance electrical connections to one of said selected leads, said leadframe comprising at least one perforation in said die attach paddle at each of said down bond sites.
2. An integrated circuit leadframe having a die attach paddle, a plurality of selected package leads and an equal plurality of down bond sites on said die attach paddle for bonding, at each of said sites, of wires forming a low inductance electrical connection to one of said selected leads, said die attach paddle comprising a roughened surface for adhering encapsulation molding compound at each of said sites and for resisting delamination of said compound at said sites.
3. An integrated circuit leadframe having a die attach paddle and a plurality of selected package leads for bonding to each of said selected leads of a wire forming a low inductance electrical connection to an integrated circuit, each of said selected leads being further electrically connected to said die attach paddle.
4. A method of resisting delamination of integrated circuit encapsulation molding compound at a down bond site on an integrated circuit leadframe die attach paddle, said method comprising perforating said die attach paddle at said down bond site prior to formation of said down bond.
5. A method of resisting delamination of integrated circuit encapsulation molding compound at a down bond site on an integrated circuit leadframe die attach paddle, said method comprising roughening said die attach paddle at said down bond site prior to formation of said down bond.
6. A method of resisting disruption of low inductance electrical connections between an integrated circuit and selected leads of a multi-lead integrated circuit leadframe having a die attach paddle, said method comprising the steps of:
(a) forming said leadframe with an electrical connection between said die attach paddle and each of said selected leads; and, (b) for each of said selected leads, bonding opposed ends of a wire to said one selected lead and to said integrated circuit respectively.
(a) forming said leadframe with an electrical connection between said die attach paddle and each of said selected leads; and, (b) for each of said selected leads, bonding opposed ends of a wire to said one selected lead and to said integrated circuit respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002189733A CA2189733A1 (en) | 1996-11-06 | 1996-11-06 | Integrated circuit leadframe with reduced inductance pin connections |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002189733A CA2189733A1 (en) | 1996-11-06 | 1996-11-06 | Integrated circuit leadframe with reduced inductance pin connections |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2189733A1 true CA2189733A1 (en) | 1998-05-06 |
Family
ID=4159214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002189733A Abandoned CA2189733A1 (en) | 1996-11-06 | 1996-11-06 | Integrated circuit leadframe with reduced inductance pin connections |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2189733A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258611B2 (en) | 2007-07-23 | 2012-09-04 | Nxp B.V. | Leadframe structure for electronic packages |
-
1996
- 1996-11-06 CA CA002189733A patent/CA2189733A1/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258611B2 (en) | 2007-07-23 | 2012-09-04 | Nxp B.V. | Leadframe structure for electronic packages |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |