CA2234493C - Architecture d'automate fini avec memoire a libre acces multiplex - Google Patents

Architecture d'automate fini avec memoire a libre acces multiplex Download PDF

Info

Publication number
CA2234493C
CA2234493C CA002234493A CA2234493A CA2234493C CA 2234493 C CA2234493 C CA 2234493C CA 002234493 A CA002234493 A CA 002234493A CA 2234493 A CA2234493 A CA 2234493A CA 2234493 C CA2234493 C CA 2234493C
Authority
CA
Canada
Prior art keywords
read
pipeline
output
null
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002234493A
Other languages
English (en)
Other versions
CA2234493A1 (fr
Inventor
Larrie Simon Carr
Winston Ki-Cheong Mok
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Storage Solutions Ltd
Original Assignee
PMC Sierra Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PMC Sierra Ltd filed Critical PMC Sierra Ltd
Priority to CA002234493A priority Critical patent/CA2234493C/fr
Publication of CA2234493A1 publication Critical patent/CA2234493A1/fr
Application granted granted Critical
Publication of CA2234493C publication Critical patent/CA2234493C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
CA002234493A 1998-04-09 1998-04-09 Architecture d'automate fini avec memoire a libre acces multiplex Expired - Fee Related CA2234493C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA002234493A CA2234493C (fr) 1998-04-09 1998-04-09 Architecture d'automate fini avec memoire a libre acces multiplex

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002234493A CA2234493C (fr) 1998-04-09 1998-04-09 Architecture d'automate fini avec memoire a libre acces multiplex

Publications (2)

Publication Number Publication Date
CA2234493A1 CA2234493A1 (fr) 1999-10-09
CA2234493C true CA2234493C (fr) 2002-12-31

Family

ID=4162317

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002234493A Expired - Fee Related CA2234493C (fr) 1998-04-09 1998-04-09 Architecture d'automate fini avec memoire a libre acces multiplex

Country Status (1)

Country Link
CA (1) CA2234493C (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7334099B2 (en) 2002-06-28 2008-02-19 Microsoft Corporation Method and system for managing image files
US7293150B2 (en) 2002-06-28 2007-11-06 Microsoft Corporation Method and system for creating and restoring an image file
GB2558955B (en) * 2017-01-24 2020-12-23 Advanced Risc Mach Ltd An apparatus and method for generating and processing a trace stream indicative of execution of predicated vector memory access instructions
CN115563920B (zh) * 2022-09-23 2026-01-27 山东云海国创云计算装备产业创新中心有限公司 Fpga综合过程中的ram映射前处理方法和系统

Also Published As

Publication number Publication date
CA2234493A1 (fr) 1999-10-09

Similar Documents

Publication Publication Date Title
US6333935B1 (en) State machine architecture with multiplexed random access memory
US5640398A (en) State machine architecture for concurrent processing of multiplexed data streams
US6362990B1 (en) Three port content addressable memory device and methods for implementing the same
JPH10340224A (ja) Ｓｄｒａｍを使用した高性能高帯域幅メモリおよびシステム
JPH0476280B2 (fr)
US20030229734A1 (en) FIFO scheduling time sharing
CA2445001A1 (fr) Architectures pour commande electrique de groupage de trafic en une phase
KR100303970B1 (ko) 동기식 멀티포트 인터페이스 및 그것의 인터페이스 방법
EP0589662B1 (fr) Système de traitement de signal numérique
KR960009771A (ko) Atm 셀 스위치 장치 및 atm 교환기
US5526487A (en) System for multiprocessor communication
US4392224A (en) Speech path switching system in time-divisional electronic telephone switching system
US5475383A (en) Cross-point type switch using common memories
US5276900A (en) Master connected to common bus providing synchronous, contiguous time periods having an instruction followed by data from different time period not immediately contiguous thereto
US5325354A (en) Synchronous terminal station receiving system
US5630063A (en) Data distribution system for multi-processor memories using simultaneous data transfer without processor intervention
JPH0278100A (ja) 再循環型シフトレジスタを用いたコントロールメモリ
EP1104579B1 (fr) Surveillance de memoire
KR0133078B1 (ko) 동기식 다이나믹 랜덤 억세스 메모리 장치 및 이를 사용하여 기록을 행하는 방법
JPS6386630A (ja) 並列伝送路におけるフレ−ム同期方式
CA2234493A1 (fr) Architecture d'automate fini avec memoire a libre acces multiplex
EP0184111B1 (fr) Distributeur de données capable de sélectionner un signal de données optionnelles et partielles et dispositif de distribution contenant une pluralité de ces distributeurs de données
EP1550953A1 (fr) Méthode et dispositif implémentant le multiplexage temporel d'accès à une mémoire RAM à deux ports de plusieurs sources de données disposant d'horloges indépendantes.
KR970004792B1 (ko) 다중접속에 의한 신호 다중화 장치
JPH1127771A (ja) ハイウェイスイッチ制御方式および方法

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed

Effective date: 20140409