CA2255232A1 - Method and device for the digital control of a phase-locked loop and relative phase-locked loop thus obtained - Google Patents
Method and device for the digital control of a phase-locked loop and relative phase-locked loop thus obtained Download PDFInfo
- Publication number
- CA2255232A1 CA2255232A1 CA002255232A CA2255232A CA2255232A1 CA 2255232 A1 CA2255232 A1 CA 2255232A1 CA 002255232 A CA002255232 A CA 002255232A CA 2255232 A CA2255232 A CA 2255232A CA 2255232 A1 CA2255232 A1 CA 2255232A1
- Authority
- CA
- Canada
- Prior art keywords
- phase
- digital
- frequency
- error
- fpe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000001914 filtration Methods 0.000 claims abstract description 31
- 230000003044 adaptive effect Effects 0.000 claims abstract description 22
- 238000004088 simulation Methods 0.000 claims description 19
- 238000011084 recovery Methods 0.000 claims description 11
- 238000012937 correction Methods 0.000 claims description 7
- 238000013459 approach Methods 0.000 claims description 6
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 101150052726 DSP2 gene Proteins 0.000 claims description 2
- 230000007423 decrease Effects 0.000 claims description 2
- 238000012545 processing Methods 0.000 claims description 2
- 238000004364 calculation method Methods 0.000 claims 2
- 238000013213 extrapolation Methods 0.000 claims 1
- 238000012886 linear function Methods 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- 238000004422 calculation algorithm Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 101150115013 DSP1 gene Proteins 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Numerical Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ITMI97/A02772 | 1997-12-16 | ||
| IT97MI002772A IT1296866B1 (it) | 1997-12-16 | 1997-12-16 | Metodo e dispositivo per il controllo numerico di un anello ad aggancio di fase e relativo anello ad aggancio di fase ottenuto |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2255232A1 true CA2255232A1 (en) | 1999-06-16 |
Family
ID=11378371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002255232A Abandoned CA2255232A1 (en) | 1997-12-16 | 1998-12-15 | Method and device for the digital control of a phase-locked loop and relative phase-locked loop thus obtained |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6046645A (de) |
| EP (1) | EP0926835A3 (de) |
| CA (1) | CA2255232A1 (de) |
| IT (1) | IT1296866B1 (de) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3356059B2 (ja) * | 1998-06-02 | 2002-12-09 | 日本ビクター株式会社 | クロック信号生成装置 |
| GB0205350D0 (en) * | 2002-03-07 | 2002-04-24 | Zarlink Semiconductor Inc | Clock synchronisation over a packet network using SRTS without a common network clock |
| WO2006127994A2 (en) * | 2005-05-25 | 2006-11-30 | Radioframe Networks, Inc. | Pll with phase clipping and resynchronization |
| US7643602B2 (en) * | 2005-09-30 | 2010-01-05 | Freescale Semiconductor, Inc. | Method and system for estimating frequency offsets |
| US7869554B2 (en) * | 2007-06-06 | 2011-01-11 | Honeywell International Inc. | Phase/frequency estimator-based phase locked loop |
| GB0800251D0 (en) * | 2008-01-08 | 2008-02-13 | Zarlink Semiconductor Inc | Phase locked loop with adaptive filter for dco synchronization |
| US11349310B2 (en) * | 2019-11-15 | 2022-05-31 | Smart Wires Inc. | Adaptive control technique for stability of impedance injection unit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4959656A (en) * | 1989-10-31 | 1990-09-25 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Efficient detection and signal parameter estimation with application to high dynamic GPS receiver |
| US5019824A (en) * | 1990-05-01 | 1991-05-28 | The United States Of America As Represented By The Administrator, National Aeronautics And Space Administration | Multistage estimation of received carrier signal parameters under very high dynamic conditions of the receiver |
| FR2706714B1 (fr) * | 1993-06-17 | 1995-07-21 | Alcatel Telspace | Système de réception d'un signal numérique à modulation de phase et d'amplitude. |
| AUPM972594A0 (en) * | 1994-11-28 | 1994-12-22 | Curtin University Of Technology | Steered frequency phase locked loop |
-
1997
- 1997-12-16 IT IT97MI002772A patent/IT1296866B1/it active IP Right Grant
-
1998
- 1998-12-04 EP EP98440279A patent/EP0926835A3/de not_active Withdrawn
- 1998-12-11 US US09/209,446 patent/US6046645A/en not_active Expired - Fee Related
- 1998-12-15 CA CA002255232A patent/CA2255232A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP0926835A2 (de) | 1999-06-30 |
| EP0926835A3 (de) | 2002-11-06 |
| ITMI972772A1 (it) | 1999-06-16 |
| IT1296866B1 (it) | 1999-08-02 |
| US6046645A (en) | 2000-04-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114175567B (zh) | 用于时钟发射的嵌入式时刻接收器 | |
| US6650719B1 (en) | MPEG PCR jitter, frequency offset and drift rate measurements | |
| US8599986B2 (en) | Phase locked loop with optimal state feedback controller | |
| EP0526573B1 (de) | Taktrückgewinnungsschaltung ohne anhebung des jitters | |
| CA2045338C (en) | Clock recovery circuit with open-loop phase estimator and wideband phase tracking loop | |
| KR100547831B1 (ko) | 가변 데이터 전송률에 대응이 가능한 클럭 및 데이터 복원장치 | |
| CN101854497B (zh) | 数字电视接收机及其定时恢复方法 | |
| US5638409A (en) | Data receiving device for reproducing a received symbol from a received data signal | |
| JPH03236652A (ja) | 適応位相検出同期方法 | |
| JPH021621A (ja) | デジタルフェーズロックループ用の商フェーズシフトプロセサ | |
| EP0805560A2 (de) | Digitaler Phasenregelkreis und Methode zum Einrasten | |
| CN108989260B (zh) | 基于Gardner的改进型全数字定时同步方法及装置 | |
| US4475220A (en) | Symbol synchronizer for MPSK signals | |
| US6046645A (en) | Method and device for the digital control of a phase-locked loop and relative phase-locked loop thus obtained | |
| US9020088B2 (en) | Digital system and method of estimating quasi-harmonic signal non-energy parameters using a digital Phase Locked Loop | |
| JP3644928B2 (ja) | デジタル受信器のサンプリングタイミングを制御する方法およびデバイス | |
| EP1225720A2 (de) | Taktsynchronisationsschaltung | |
| CN1968020B (zh) | 用于稳定数字锁相环的传递函数的方法和设备 | |
| JP2674295B2 (ja) | 速度変換回路 | |
| JP3028063B2 (ja) | 搬送波位相同期回路 | |
| JPH01273464A (ja) | オフセット四分割位相シフトキーイング用同期回路 | |
| US7154979B2 (en) | Timing recovery with variable bandwidth phase locked loop and non-linear control paths | |
| JP3092660B2 (ja) | ランダムな時刻情報から基準クロックを再生するｐｌｌとその方法 | |
| JP2823563B2 (ja) | Ｐｌｌ回路 | |
| KR100219880B1 (ko) | 완전 디지털 위상 검출 장치를 이용한 디지털수신기 및디지털 위상 검출 방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |