CA2283560C - Dispositif de protection de memoire d'instructions traduites pour microprocesseur evolue - Google Patents

Dispositif de protection de memoire d'instructions traduites pour microprocesseur evolue Download PDF

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Publication number
CA2283560C
CA2283560C CA002283560A CA2283560A CA2283560C CA 2283560 C CA2283560 C CA 2283560C CA 002283560 A CA002283560 A CA 002283560A CA 2283560 A CA2283560 A CA 2283560A CA 2283560 C CA2283560 C CA 2283560C
Authority
CA
Canada
Prior art keywords
target
host
instructions
instruction
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002283560A
Other languages
English (en)
Other versions
CA2283560A1 (fr
Inventor
Edmund J. Kelly
Robert F. Cmelik
Malcolm J. Wing
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intellectual Ventures Holding 81 LLC
Original Assignee
Transmeta Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transmeta Inc filed Critical Transmeta Inc
Publication of CA2283560A1 publication Critical patent/CA2283560A1/fr
Application granted granted Critical
Publication of CA2283560C publication Critical patent/CA2283560C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Executing Machine-Instructions (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention traite d'un procédé permettant de répondre à une tentative d'écriture au niveau d'une adresse en mémoire comportant une instruction cible qui a été traduite en instruction hôte en vue de son exécution par un processeur hôte. Ce procédé consiste à marquer une adresse en mémoire comportant une instruction cible qui a été traduite en instruction hôte; à déceler une adresse en mémoire qui a été marquée lors d'une tentative d'écriture au niveau de cette adresse en mémoire; et à répondre à la détection d'une adresse en mémoire marquée en protégeant une instruction cible située au niveau de l'adresse en mémoire jusqu'à ce qu'il soit certain que les traductions associées à ladite adresse en mémoire ne seront pas utilisées avant d'avoir été mises à jour.
CA002283560A 1997-08-11 1997-08-11 Dispositif de protection de memoire d'instructions traduites pour microprocesseur evolue Expired - Fee Related CA2283560C (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1997/014117 WO1999008191A1 (fr) 1997-08-11 1997-08-11 Dispositif de protection de memoire d'instructions traduites pour microprocesseur evolue

Publications (2)

Publication Number Publication Date
CA2283560A1 CA2283560A1 (fr) 1999-02-18
CA2283560C true CA2283560C (fr) 2003-12-09

Family

ID=22261430

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002283560A Expired - Fee Related CA2283560C (fr) 1997-08-11 1997-08-11 Dispositif de protection de memoire d'instructions traduites pour microprocesseur evolue

Country Status (5)

Country Link
EP (1) EP1004075A4 (fr)
JP (1) JP3621116B2 (fr)
KR (1) KR100421687B1 (fr)
CA (1) CA2283560C (fr)
WO (1) WO1999008191A1 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US6978462B1 (en) 1999-01-28 2005-12-20 Ati International Srl Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled
US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US7013456B1 (en) 1999-01-28 2006-03-14 Ati International Srl Profiling execution of computer programs
US7254806B1 (en) 1999-08-30 2007-08-07 Ati International Srl Detecting reordered side-effects
US6751583B1 (en) 1999-10-29 2004-06-15 Vast Systems Technology Corporation Hardware and software co-simulation including simulating a target processor using binary translation
US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US7353499B2 (en) 2003-09-25 2008-04-01 Sun Microsystems, Inc. Multiple instruction dispatch tables for application program obfuscation
US7363620B2 (en) 2003-09-25 2008-04-22 Sun Microsystems, Inc. Non-linear execution of application program instructions for application program obfuscation
US7415618B2 (en) 2003-09-25 2008-08-19 Sun Microsystems, Inc. Permutation of opcode values for application program obfuscation
US8220058B2 (en) 2003-09-25 2012-07-10 Oracle America, Inc. Rendering and encryption engine for application program obfuscation
US7424620B2 (en) 2003-09-25 2008-09-09 Sun Microsystems, Inc. Interleaved data and instruction streams for application program obfuscation
JP6103541B2 (ja) * 2014-03-18 2017-03-29 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ バイナリコードの実行を制御する装置及び方法
US10754790B2 (en) 2018-04-26 2020-08-25 Qualcomm Incorporated Translation of virtual addresses to physical addresses using translation lookaside buffer information

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4914577A (en) * 1987-07-16 1990-04-03 Icon International, Inc. Dynamic memory management system and method
US4825412A (en) * 1988-04-01 1989-04-25 Digital Equipment Corporation Lockout registers
GB2239724B (en) * 1990-01-05 1993-11-24 Sun Microsystems Inc Apparatus for maintaining consistency in a multi-processor computer system using virtual caching
US5282274A (en) * 1990-05-24 1994-01-25 International Business Machines Corporation Translation of multiple virtual pages upon a TLB miss
US5437017A (en) * 1992-10-09 1995-07-25 International Business Machines Corporation Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system
US5577231A (en) * 1994-12-06 1996-11-19 International Business Machines Corporation Storage access authorization controls in a computer system using dynamic translation of large addresses

Also Published As

Publication number Publication date
JP3621116B2 (ja) 2005-02-16
KR20010014096A (ko) 2001-02-26
EP1004075A1 (fr) 2000-05-31
EP1004075A4 (fr) 2001-01-17
KR100421687B1 (ko) 2004-03-10
WO1999008191A1 (fr) 1999-02-18
CA2283560A1 (fr) 1999-02-18
JP2001519955A (ja) 2001-10-23

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