CA2305779A1 - Structure bus et procede associe dans un systeme informatique - Google Patents

Structure bus et procede associe dans un systeme informatique Download PDF

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Publication number
CA2305779A1
CA2305779A1 CA002305779A CA2305779A CA2305779A1 CA 2305779 A1 CA2305779 A1 CA 2305779A1 CA 002305779 A CA002305779 A CA 002305779A CA 2305779 A CA2305779 A CA 2305779A CA 2305779 A1 CA2305779 A1 CA 2305779A1
Authority
CA
Canada
Prior art keywords
output
data
input
modules
latches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002305779A
Other languages
English (en)
Inventor
Stephen James Sheafor
James Yuan Wei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sitera Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2305779A1 publication Critical patent/CA2305779A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)

Abstract

L'invention concerne une structure bus numérique et le procédé associé. La structure bus comprend une couche de synchronisation d'entrée et une couche de synchronisation de sortie. Le transfert de données entre les différents modules est synchronisé par un signal d'horloge maître, de façon que les données provenant de l'un des modules soient verrouillées et placées sur le bus dans un seul cycle d'horloge. Puis, dans un second cycle d'horloge ou un cycle ultérieur, les données sont verrouillées de manière synchrone au niveau des autres modules du système, de façon à être disponibles pour le module prévu. Il n'y a aucun circuit logique entre les couches de synchronisation d'entrée et de sortie.
CA002305779A 1997-10-01 1998-09-16 Structure bus et procede associe dans un systeme informatique Abandoned CA2305779A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/942,011 1997-10-01
US08/942,011 US6493407B1 (en) 1997-05-27 1997-10-01 Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method
PCT/US1998/019319 WO1999017215A1 (fr) 1997-10-01 1998-09-16 Structure bus et procede associe dans un systeme informatique

Publications (1)

Publication Number Publication Date
CA2305779A1 true CA2305779A1 (fr) 1999-04-08

Family

ID=25477457

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002305779A Abandoned CA2305779A1 (fr) 1997-10-01 1998-09-16 Structure bus et procede associe dans un systeme informatique

Country Status (4)

Country Link
US (1) US6493407B1 (fr)
EP (1) EP1019839A1 (fr)
CA (1) CA2305779A1 (fr)
WO (1) WO1999017215A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6279058B1 (en) * 1998-07-02 2001-08-21 Advanced Micro Devices, Inc. Master isochronous clock structure having a clock controller coupling to a CPU and two data buses
WO2000016223A1 (fr) * 1998-09-15 2000-03-23 Acqiris Systeme modulaire d'acquisition de donnees
WO2002056546A1 (fr) * 2001-01-09 2002-07-18 Mitsubishi Denki Kabushiki Kaisha Systeme de transmission de donnees
US20040010652A1 (en) * 2001-06-26 2004-01-15 Palmchip Corporation System-on-chip (SOC) architecture with arbitrary pipeline depth
JP5478625B2 (ja) * 2009-08-18 2014-04-23 パナソニック株式会社 半導体集積回路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU597980B2 (en) * 1986-05-30 1990-06-14 Honeywell Bull Inc. Apparatus and method for interprocessor communication
US4829515A (en) * 1987-05-01 1989-05-09 Digital Equipment Corporation High performance low pin count bus interface
US4845663A (en) * 1987-09-03 1989-07-04 Minnesota Mining And Manufacturing Company Image processor with free flow pipeline bus
DE4022365C2 (de) * 1989-07-20 2000-02-24 Nippon Telegraph & Telephone Datenübertragungssystem
JP3118266B2 (ja) * 1990-03-06 2000-12-18 ゼロックス コーポレイション 同期セグメントバスとバス通信方法
US5289585A (en) * 1990-03-26 1994-02-22 Siemens Nixdorf Informationssysteme Ag Multiprocessor system having a system bus for the coupling of several processing units with appertaining private cache memories and a common main memory
JPH03276337A (ja) * 1990-03-27 1991-12-06 Toshiba Corp マイクロコントローラ
ES2109256T3 (es) * 1990-05-25 1998-01-16 At & T Corp Disposicion de bus de acceso a memoria.
JP2910303B2 (ja) * 1990-06-04 1999-06-23 株式会社日立製作所 情報処理装置
US5457683A (en) * 1993-05-07 1995-10-10 Apple Computer, Inc. Link and discovery protocols for a ring interconnect architecture
US5751999A (en) * 1994-06-23 1998-05-12 Matsushita Electric Industrial Co., Ltd. Processor and data memory for outputting and receiving data on different buses for storage in the same location
US5666551A (en) * 1994-06-30 1997-09-09 Digital Equipment Corporation Distributed data bus sequencing for a system bus with separate address and data bus protocols
US5781765A (en) * 1995-11-03 1998-07-14 Motorola, Inc. System for data synchronization between two devices using four time domains
US5768550A (en) * 1995-11-21 1998-06-16 International Business Machines Corporation Bus interface logic system

Also Published As

Publication number Publication date
EP1019839A1 (fr) 2000-07-19
US6493407B1 (en) 2002-12-10
WO1999017215A1 (fr) 1999-04-08

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Legal Events

Date Code Title Description
FZDE Discontinued