CA2345845C - Precharge de lignes de bits - Google Patents

Precharge de lignes de bits Download PDF

Info

Publication number
CA2345845C
CA2345845C CA2345845A CA2345845A CA2345845C CA 2345845 C CA2345845 C CA 2345845C CA 2345845 A CA2345845 A CA 2345845A CA 2345845 A CA2345845 A CA 2345845A CA 2345845 C CA2345845 C CA 2345845C
Authority
CA
Canada
Prior art keywords
bitline
bitlines
equalization
bln
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA2345845A
Other languages
English (en)
Other versions
CA2345845A1 (fr
Inventor
Peter P. Ma
Abdullah Ahmed
Valerie L. Lines
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Priority to CA2345845A priority Critical patent/CA2345845C/fr
Priority to US09/956,917 priority patent/US6504775B1/en
Priority to PCT/CA2002/000600 priority patent/WO2002089143A1/fr
Priority to CNB028091183A priority patent/CN100380525C/zh
Priority to TW091108844A priority patent/TW594783B/zh
Publication of CA2345845A1 publication Critical patent/CA2345845A1/fr
Priority to US10/290,287 priority patent/US6608788B2/en
Application granted granted Critical
Publication of CA2345845C publication Critical patent/CA2345845C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/043—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Dram (AREA)
CA2345845A 2001-04-30 2001-04-30 Precharge de lignes de bits Expired - Fee Related CA2345845C (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CA2345845A CA2345845C (fr) 2001-04-30 2001-04-30 Precharge de lignes de bits
US09/956,917 US6504775B1 (en) 2001-04-30 2001-09-21 Bitline precharge
PCT/CA2002/000600 WO2002089143A1 (fr) 2001-04-30 2002-04-25 Prechargement de lignes binaires
CNB028091183A CN100380525C (zh) 2001-04-30 2002-04-25 用于位线预先充电的电路和方法
TW091108844A TW594783B (en) 2001-04-30 2002-04-29 Bitline precharge
US10/290,287 US6608788B2 (en) 2001-04-30 2002-11-08 Bitline precharge

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA2345845A CA2345845C (fr) 2001-04-30 2001-04-30 Precharge de lignes de bits

Publications (2)

Publication Number Publication Date
CA2345845A1 CA2345845A1 (fr) 2002-10-30
CA2345845C true CA2345845C (fr) 2012-03-27

Family

ID=4168939

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2345845A Expired - Fee Related CA2345845C (fr) 2001-04-30 2001-04-30 Precharge de lignes de bits

Country Status (5)

Country Link
US (2) US6504775B1 (fr)
CN (1) CN100380525C (fr)
CA (1) CA2345845C (fr)
TW (1) TW594783B (fr)
WO (1) WO2002089143A1 (fr)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6590818B1 (en) * 2002-06-17 2003-07-08 Motorola, Inc. Method and apparatus for soft defect detection in a memory
US6785179B1 (en) * 2003-06-19 2004-08-31 Arm Limited Charge sharing between bit lines within a memory circuit to increase recharge speed
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
WO2005106892A1 (fr) * 2004-04-21 2005-11-10 Micron Technology, Inc. Amplificateur de detection destine a un dispositif memoire non volatil
ITRM20040199A1 (it) * 2004-04-21 2004-07-21 Micron Technology Inc Amplificatore di rilevazione per un dispositivo di memoria non volatile.
US7342832B2 (en) * 2005-11-16 2008-03-11 Actel Corporation Bit line pre-settlement circuit and method for flash memory sensing scheme
JP2007310936A (ja) * 2006-05-17 2007-11-29 Toshiba Corp 半導体記憶装置
RU2444073C1 (ru) * 2007-12-15 2012-02-27 Квэлкомм Инкорпорейтед Улучшение устойчивости считывания памяти с использованием избирательной предварительной зарядки
US7800965B2 (en) 2008-03-10 2010-09-21 Micron Technology, Inc. Digit line equilibration using access devices at the edge of sub-arrays
CN101645305B (zh) * 2008-08-05 2013-03-27 辉达公司 静态随机存取存储器的自动跟踪数据
US7881137B2 (en) 2008-10-23 2011-02-01 Qualcomm Incorporated Read assist for memory circuits with different precharge voltage levels for bit line pair
JP2015225682A (ja) * 2014-05-27 2015-12-14 ルネサスエレクトロニクス株式会社 半導体集積回路
CN105336369B (zh) * 2014-07-22 2019-09-10 硅存储技术公司 用于高速闪存存储器系统的位线调节器
US9418716B1 (en) * 2015-04-15 2016-08-16 Qualcomm Incorporated Word line and bit line tracking across diverse power domains
TWI648737B (zh) * 2015-11-19 2019-01-21 鈺創科技股份有限公司 能夠快速寫入資料的記憶體電路
US11011238B2 (en) * 2018-06-28 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Floating data line circuits and methods
US11100964B1 (en) 2020-02-10 2021-08-24 Taiwan Semiconductor Manufacturing Company Limited Multi-stage bit line pre-charge
CN113395465B (zh) * 2020-03-12 2024-03-05 格科微电子（上海）有限公司 存储单元的数据读取方法
CN115346578A (zh) * 2021-04-27 2022-11-15 华为技术有限公司 一种内容寻址存储器
US12340838B2 (en) 2022-07-13 2025-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Drive circuit with improved timing margin for memory device
CN116343895B (zh) * 2023-03-07 2025-10-03 浙江大学 6t sram单元晶体管阈值电压片上测量电路、测量方法、芯片

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289414A (en) * 1991-09-27 1994-02-22 Matsushita Electric Industrial Co., Ltd. Comparator
US5327372A (en) * 1992-01-17 1994-07-05 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device
US5446685A (en) * 1993-02-23 1995-08-29 Intergraph Corporation Pulsed ground circuit for CAM and PAL memories
US5392241A (en) * 1993-12-10 1995-02-21 International Business Machines Corporation Semiconductor memory circuit with block overwrite
JPH08212791A (ja) 1995-02-03 1996-08-20 Kawasaki Steel Corp 連想メモリ装置
US5646878A (en) * 1995-06-02 1997-07-08 Motorola, Inc. Content addressable memory system
US5673219A (en) 1996-03-21 1997-09-30 Texas Instruments Incorporated Apparatus and method for reducing leakage current in a dynamic random access memory
US6054918A (en) 1996-09-30 2000-04-25 Advanced Micro Devices, Inc. Self-timed differential comparator
US5745423A (en) 1996-12-17 1998-04-28 Powerchip Semiconductor Corp. Low power precharge circuit for a dynamic random access memory
US5930178A (en) 1997-11-17 1999-07-27 International Business Machines Corporation Bitline voltage stabilization device and method

Also Published As

Publication number Publication date
CA2345845A1 (fr) 2002-10-30
US6504775B1 (en) 2003-01-07
US20030016580A1 (en) 2003-01-23
US6608788B2 (en) 2003-08-19
WO2002089143A1 (fr) 2002-11-07
TW594783B (en) 2004-06-21
US20030072205A1 (en) 2003-04-17
CN1513185A (zh) 2004-07-14
CN100380525C (zh) 2008-04-09

Similar Documents

Publication Publication Date Title
CA2345845C (fr) Precharge de lignes de bits
US6480424B1 (en) Compact analog-multiplexed global sense amplifier for RAMS
US6958507B2 (en) Semiconductor memory pipeline buffer
US5555212A (en) Method and apparatus for redundancy word line replacement in a semiconductor memory device
US6552944B2 (en) Single bitline direct sensing architecture for high speed memory device
CA2384039C (fr) Architecture de memoire adressable par le contenu a basse puissance
US8441878B2 (en) Embedded memory databus architecture
US20020196669A1 (en) Decoding scheme for a stacked bank architecture
JP2836596B2 (ja) 連想メモリ
US7813155B1 (en) Content addressable memory (CAM) cell having column-wise conditional data pre-write
US5949732A (en) Method of structuring a multi-bank DRAM into a hierarchical column select line architecture
US6678198B2 (en) Pseudo differential sensing method and apparatus for DRAM cell
Lines et al. 66 MHz 2.3 M ternary dynamic content addressable memory
US6297985B1 (en) Cell block structure of nonvolatile ferroelectric memory
US6519174B2 (en) Early write DRAM architecture with vertically folded bitlines
US5625601A (en) DRAM page copy method
EP0902434B1 (fr) Architecture hierarchique de ligne de sélection de colonne pour des mémoires DRAM multibancs et méthode pour telle
US6671218B2 (en) System and method for hiding refresh cycles in a dynamic type content addressable memory
US7474557B2 (en) MRAM array and access method thereof
US20250118353A1 (en) Apparatuses and methods for single and multi memory cell architectures

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed

Effective date: 20170501