CA2978535C - Emetteur et procede de permutation de parite associe - Google Patents

Emetteur et procede de permutation de parite associe Download PDF

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Publication number
CA2978535C
CA2978535C CA2978535A CA2978535A CA2978535C CA 2978535 C CA2978535 C CA 2978535C CA 2978535 A CA2978535 A CA 2978535A CA 2978535 A CA2978535 A CA 2978535A CA 2978535 C CA2978535 C CA 2978535C
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CA
Canada
Prior art keywords
bits
ldpc
parity
group
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CA2978535A
Other languages
English (en)
Other versions
CA2978535A1 (fr
Inventor
Se-Ho Myung
Kyung-Joong Kim
Hong-Sil Jeong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to CA3209954A priority Critical patent/CA3209954A1/fr
Priority claimed from PCT/KR2016/002091 external-priority patent/WO2016140513A1/fr
Publication of CA2978535A1 publication Critical patent/CA2978535A1/fr
Application granted granted Critical
Publication of CA2978535C publication Critical patent/CA2978535C/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
    • H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

La présente invention se rapporte à un émetteur. L'émetteur comprend : un codeur à contrôle de parité de faible densité (LDPC) configuré pour coder des bits d'entrée afin de générer des bits de parité; un permutateur de parité configuré pour entrelacer groupe par groupe une pluralité de groupes de bits comprenant les bits de parité; et un dispositif de poinçonnage configuré pour sélectionner certains des bits de parité dans les groupes de bits entrelacés groupe par groupe et poinçonner les bits de parité sélectionnés, le permutateur de parité entrelaçant groupe par groupe les groupes de bits de telle sorte que certains des groupes de bits, en des emplacements prédéterminés dans les groupes de bits avant l'entrelacement groupe par groupe sont positionnés de manière sérielle après l'entrelacement groupe par groupe et un reste de groupes de bits, avant l'entrelacement groupe par groupe, est positionné sans ordre après l'entrelacement groupe par groupe de sorte que le dispositif de poinçonnage sélectionne des bits de parité compris dans certains des groupes de bits séquentiellement et sélectionne des bits de parité compris dans le reste des groupes de bits sans ordre.
CA2978535A 2015-03-02 2016-03-02 Emetteur et procede de permutation de parite associe Active CA2978535C (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA3209954A CA3209954A1 (fr) 2015-03-02 2016-03-02 Emetteur et procede de permutation de parite associe

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562127014P 2015-03-02 2015-03-02
US62/127,014 2015-03-02
KR1020150137188A KR102426780B1 (ko) 2015-03-02 2015-09-27 송신 장치 및 그의 패리티 퍼뮤테이션 방법
KR10-2015-0137188 2015-09-27
PCT/KR2016/002091 WO2016140513A1 (fr) 2015-03-02 2016-03-02 Émetteur et procédé de permutation de parité associé

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CA3209954A Division CA3209954A1 (fr) 2015-03-02 2016-03-02 Emetteur et procede de permutation de parite associe

Publications (2)

Publication Number Publication Date
CA2978535A1 CA2978535A1 (fr) 2016-09-09
CA2978535C true CA2978535C (fr) 2023-10-17

Family

ID=56950313

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2978535A Active CA2978535C (fr) 2015-03-02 2016-03-02 Emetteur et procede de permutation de parite associe

Country Status (4)

Country Link
KR (1) KR102426780B1 (fr)
CN (1) CN107567692B (fr)
CA (1) CA2978535C (fr)
MX (1) MX376908B (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4714081A1 (fr) * 2023-05-16 2026-03-25 Qualcomm Incorporated Structures d'émetteur pour introduction de dispositifs à faible puissance

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7706455B2 (en) * 2005-09-26 2010-04-27 Intel Corporation Multicarrier transmitter for multiple-input multiple-output communication systems and methods for puncturing bits for pilot tones
KR101503058B1 (ko) * 2008-02-26 2015-03-18 삼성전자주식회사 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서의 채널 부호화/복호화 방법 및 장치
CN101807966B (zh) * 2009-02-13 2012-12-12 瑞昱半导体股份有限公司 奇偶校验码解码器及接收系统
ES2930153T3 (es) * 2010-05-11 2022-12-07 Electronics & Telecommunications Res Inst Método de transmisión de información de rango de canal de enlace descendente a través de un canal compartido de enlace ascendente físico
KR20150005853A (ko) * 2013-07-05 2015-01-15 삼성전자주식회사 송신 장치 및 그의 신호 처리 방법
KR20150005426A (ko) * 2013-07-05 2015-01-14 삼성전자주식회사 송신 장치 및 그의 신호 처리 방법

Also Published As

Publication number Publication date
KR102426780B1 (ko) 2022-07-29
KR20160106476A (ko) 2016-09-12
MX376908B (es) 2025-03-07
CA2978535A1 (fr) 2016-09-09
CN107567692B (zh) 2020-09-04
MX2017011153A (es) 2017-11-09
CN107567692A (zh) 2018-01-09

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