CA3085277C - Emetteur, et procede de generation de bits de parite supplementaires correspondant - Google Patents

Emetteur, et procede de generation de bits de parite supplementaires correspondant Download PDF

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Publication number
CA3085277C
CA3085277C CA3085277A CA3085277A CA3085277C CA 3085277 C CA3085277 C CA 3085277C CA 3085277 A CA3085277 A CA 3085277A CA 3085277 A CA3085277 A CA 3085277A CA 3085277 C CA3085277 C CA 3085277C
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CA
Canada
Prior art keywords
bits
ldpc
parity bits
parity
values
Prior art date
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Active
Application number
CA3085277A
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English (en)
Other versions
CA3085277A1 (fr
Inventor
Hong-Sil Jeong
Kyung-Joong Kim
Se-Ho Myung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CA3085277A1 publication Critical patent/CA3085277A1/fr
Application granted granted Critical
Publication of CA3085277C publication Critical patent/CA3085277C/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Error Detection And Correction (AREA)

Abstract

Un appareil de réception et un procédé associé sont décrits. Lappareil comprend un récepteur configuré pour recevoir un signal de radiodiffusion à partir dun appareil de transmission, un démodulateur configuré pour démoduler des données dun premier mot de code et dun deuxième mot de code, un intubateur configuré pour insérer des valeurs prédéterminées, un combineur configuré pour ajouter des valeurs si un mode prédéterminé est présent, un décodeur configuré pour décoder les valeurs ajoutées et valeurs restantes daprès un code de contrôle de parité à faible densité afin de générer des bits de sortie. Si un mode prédéterminé est détecté, le premier mot de code est basé sur des bits de parité restants après la perforation dau moins un bit de parité à partir des bits de parité générés daprès des bits dinformations et des bits de parité de répétition sélectionnés à partir des bits de parité générés, et le deuxième mot de code est basé sur au moins un bit de parité sélectionné parmi les bits de parité de répétition et les bits de parité générés.
CA3085277A 2015-02-13 2016-02-15 Emetteur, et procede de generation de bits de parite supplementaires correspondant Active CA3085277C (fr)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US201562115810P 2015-02-13 2015-02-13
US62/115,810 2015-02-13
US201562120543P 2015-02-25 2015-02-25
US62/120,543 2015-02-25
US201562202304P 2015-08-07 2015-08-07
US62/202,304 2015-08-07
KR10-2015-0137191 2015-09-27
KR1020150137191A KR101800423B1 (ko) 2015-02-13 2015-09-27 송신 장치 및 그의 부가 패리티 생성 방법
CA2975077A CA2975077C (fr) 2015-02-13 2016-02-15 Emetteur, et procede de generation de bits de parite supplementaires correspondant

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CA2975077A Division CA2975077C (fr) 2015-02-13 2016-02-15 Emetteur, et procede de generation de bits de parite supplementaires correspondant

Publications (2)

Publication Number Publication Date
CA3085277A1 CA3085277A1 (fr) 2016-08-18
CA3085277C true CA3085277C (fr) 2023-06-20

Family

ID=56875537

Family Applications (2)

Application Number Title Priority Date Filing Date
CA3085277A Active CA3085277C (fr) 2015-02-13 2016-02-15 Emetteur, et procede de generation de bits de parite supplementaires correspondant
CA2975077A Active CA2975077C (fr) 2015-02-13 2016-02-15 Emetteur, et procede de generation de bits de parite supplementaires correspondant

Family Applications After (1)

Application Number Title Priority Date Filing Date
CA2975077A Active CA2975077C (fr) 2015-02-13 2016-02-15 Emetteur, et procede de generation de bits de parite supplementaires correspondant

Country Status (5)

Country Link
KR (5) KR101800423B1 (fr)
CN (1) CN107251464B (fr)
BR (1) BR112017016116B1 (fr)
CA (2) CA3085277C (fr)
MX (1) MX373036B (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20260031836A1 (en) * 2024-07-26 2026-01-29 Avago Technologies International Sales Pte. Limited Low-density parity check (ldpc) decoders using partial syndrome early termination

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050020526A (ko) * 2003-08-23 2005-03-04 삼성전자주식회사 이동통신시스템에서 비트 인터리빙장치 및 방법
RU2323520C2 (ru) * 2006-03-21 2008-04-27 Самсунг Электроникс Ко., Лтд. Способ передачи голосовых данных в системе цифровой радиосвязи и способ перемежения последовательности кодовых символов (варианты)
KR101503058B1 (ko) * 2008-02-26 2015-03-18 삼성전자주식회사 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서의 채널 부호화/복호화 방법 및 장치
KR20110055410A (ko) * 2009-11-18 2011-05-25 삼성전자주식회사 통신 시스템에서 데이터 송수신 방법 및 장치
KR101806212B1 (ko) * 2011-02-22 2017-12-08 삼성전자주식회사 디지털 방송 시스템에서 시그널링 정보 전송 방법 및 장치
WO2013032156A1 (fr) * 2011-08-30 2013-03-07 Samsung Electronics Co., Ltd. Procédé et appareil pour transmettre et recevoir des informations dans un système de diffusion/communication
KR101922555B1 (ko) * 2011-08-30 2018-11-28 삼성전자주식회사 방송/통신시스템에서 정보 송수신 방법 및 장치
CN105453553B (zh) * 2013-08-01 2018-08-28 Lg 电子株式会社 发送广播信号的设备、接收广播信号的设备、发送广播信号的方法以及接收广播信号的方法

Also Published As

Publication number Publication date
KR102114481B1 (ko) 2020-05-22
BR112017016116A2 (pt) 2018-03-27
BR112017016116B1 (pt) 2023-10-31
KR20170130321A (ko) 2017-11-28
KR102227537B1 (ko) 2021-03-12
CA3085277A1 (fr) 2016-08-18
MX373036B (es) 2020-05-27
CN107251464B (zh) 2020-08-07
KR20180103794A (ko) 2018-09-19
KR20160100198A (ko) 2016-08-23
CA2975077A1 (fr) 2016-08-18
MX2017010344A (es) 2018-01-23
KR20190042521A (ko) 2019-04-24
CN107251464A (zh) 2017-10-13
KR101970825B1 (ko) 2019-04-19
KR101898697B1 (ko) 2018-09-13
KR20200058345A (ko) 2020-05-27
KR101800423B1 (ko) 2017-11-23
CA2975077C (fr) 2020-09-01

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