CH448198A - Verfahren zum Herstellen von elektrisch leitenden Verbindungen zwischen Festkörperbauelementen und dem Leitungsmuster einer Schaltungsplatte - Google Patents

Verfahren zum Herstellen von elektrisch leitenden Verbindungen zwischen Festkörperbauelementen und dem Leitungsmuster einer Schaltungsplatte

Info

Publication number
CH448198A
CH448198A CH348767A CH348767A CH448198A CH 448198 A CH448198 A CH 448198A CH 348767 A CH348767 A CH 348767A CH 348767 A CH348767 A CH 348767A CH 448198 A CH448198 A CH 448198A
Authority
CH
Switzerland
Prior art keywords
solid
circuit board
electrically conductive
conductor pattern
conductive connections
Prior art date
Application number
CH348767A
Other languages
English (en)
Inventor
Augustus Chance Dudley
Anthony Perri John
Riseman Jacob
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH448198A publication Critical patent/CH448198A/de

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00Soldering, e.g. brazing, or unsoldering
    • B23K1/005Soldering by means of radiant energy
    • B23K1/0056Soldering by means of radiant energy soldering by means of beams, e.g. lasers, electron beams [EB]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00Articles made by soldering, welding or cutting
    • B23K2101/36Electric or electronic devices
    • B23K2101/38Conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/682Shapes or dispositions thereof comprising holes having chips therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128Assembling formed circuit to base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base

Landscapes

  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
CH348767A 1966-03-09 1967-03-09 Verfahren zum Herstellen von elektrisch leitenden Verbindungen zwischen Festkörperbauelementen und dem Leitungsmuster einer Schaltungsplatte CH448198A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US53307366A 1966-03-09 1966-03-09

Publications (1)

Publication Number Publication Date
CH448198A true CH448198A (de) 1967-12-15

Family

ID=24124356

Family Applications (1)

Application Number Title Priority Date Filing Date
CH348767A CH448198A (de) 1966-03-09 1967-03-09 Verfahren zum Herstellen von elektrisch leitenden Verbindungen zwischen Festkörperbauelementen und dem Leitungsmuster einer Schaltungsplatte

Country Status (7)

Country Link
US (1) US3614832A (de)
CH (1) CH448198A (de)
DE (1) DE1591186B1 (de)
FR (1) FR1521440A (de)
GB (1) GB1162184A (de)
NL (1) NL149674B (de)
SE (1) SE345343B (de)

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Also Published As

Publication number Publication date
GB1162184A (en) 1969-08-20
DE1591186B1 (de) 1971-01-14
SE345343B (de) 1972-05-23
FR1521440A (fr) 1968-04-19
NL6703605A (de) 1967-09-11
US3614832A (en) 1971-10-26
NL149674B (nl) 1976-05-17

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