CH449777A - Verfahren zur Herstellung einer Festkörperschaltung - Google Patents

Verfahren zur Herstellung einer Festkörperschaltung

Info

Publication number
CH449777A
CH449777A CH709265A CH709265A CH449777A CH 449777 A CH449777 A CH 449777A CH 709265 A CH709265 A CH 709265A CH 709265 A CH709265 A CH 709265A CH 449777 A CH449777 A CH 449777A
Authority
CH
Switzerland
Prior art keywords
solid
manufacturing
state circuit
circuit
state
Prior art date
Application number
CH709265A
Other languages
English (en)
Inventor
Hans-Juergen Dr Schuetze
Klaus Dr Hennings
Original Assignee
Telefunken Patent
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefunken Patent filed Critical Telefunken Patent
Publication of CH449777A publication Critical patent/CH449777A/de

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/019Manufacture or treatment of isolation regions comprising dielectric materials using epitaxial passivated integrated circuit [EPIC] processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/061Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00Highly-doped buried regions of integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00Highly-doped buried regions of integrated devices
    • H10W15/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/021Manufacture or treatment of air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20Air gaps
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/051Etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/145Shaped junctions
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/928Front and rear surface processing
CH709265A 1964-08-08 1965-05-20 Verfahren zur Herstellung einer Festkörperschaltung CH449777A (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DET0026759 1964-08-08
DET0027136 1964-10-03
DET0027418 1964-11-14

Publications (1)

Publication Number Publication Date
CH449777A true CH449777A (de) 1968-01-15

Family

ID=27213131

Family Applications (1)

Application Number Title Priority Date Filing Date
CH709265A CH449777A (de) 1964-08-08 1965-05-20 Verfahren zur Herstellung einer Festkörperschaltung

Country Status (6)

Country Link
US (1) US3689992A (de)
CH (1) CH449777A (de)
DE (3) DE1439712A1 (de)
FR (1) FR1453410A (de)
GB (2) GB1124627A (de)
SE (1) SE337871B (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3815223A (en) * 1971-02-08 1974-06-11 Signetics Corp Method for making semiconductor structure with dielectric and air isolation
US3786560A (en) * 1972-03-20 1974-01-22 J Cunningham Electrical isolation of circuit components of integrated circuits
US3883948A (en) * 1974-01-02 1975-05-20 Signetics Corp Semiconductor structure and method
JPS589584B2 (ja) * 1974-01-11 1983-02-22 株式会社日立製作所 ハンドウタイソウチ
US4106050A (en) * 1976-09-02 1978-08-08 International Business Machines Corporation Integrated circuit structure with fully enclosed air isolation
US4169000A (en) * 1976-09-02 1979-09-25 International Business Machines Corporation Method of forming an integrated circuit structure with fully-enclosed air isolation
US4860081A (en) * 1984-06-28 1989-08-22 Gte Laboratories Incorporated Semiconductor integrated circuit structure with insulative partitions
US4987101A (en) * 1988-12-16 1991-01-22 International Business Machines Corporation Method for providing improved insulation in VLSI and ULSI circuits
US5070026A (en) * 1989-06-26 1991-12-03 Spire Corporation Process of making a ferroelectric electronic component and product
US5098856A (en) * 1991-06-18 1992-03-24 International Business Machines Corporation Air-filled isolation trench with chemically vapor deposited silicon dioxide cap
US5227658A (en) * 1991-10-23 1993-07-13 International Business Machines Corporation Buried air dielectric isolation of silicon islands
GB9305448D0 (en) * 1993-03-17 1993-05-05 British Tech Group Semiconductor structure and method of manufacturing same
US5324683A (en) * 1993-06-02 1994-06-28 Motorola, Inc. Method of forming a semiconductor structure having an air region
US5508231A (en) * 1994-03-07 1996-04-16 National Semiconductor Corporation Apparatus and method for achieving mechanical and thermal isolation of portions of integrated monolithic circuits
US5750415A (en) * 1994-05-27 1998-05-12 Texas Instruments Incorporated Low dielectric constant layers via immiscible sol-gel processing
WO1999059203A1 (en) * 1998-05-08 1999-11-18 Infineon Technologies Ag Substrate and method for manufacturing the same
US6211057B1 (en) 1999-09-03 2001-04-03 Taiwan Semiconductor Manufacturing Company Method for manufacturing arch air gap in multilevel interconnection
GB2371922B (en) 2000-09-21 2004-12-15 Cambridge Semiconductor Ltd Semiconductor device and method of forming a semiconductor device
JP5392959B2 (ja) * 2000-09-21 2014-01-22 ケンブリッジ セミコンダクター リミテッド 半導体デバイスおよび半導体デバイスを形成する方法
ATE511213T1 (de) * 2004-09-03 2011-06-15 Cambridge Semiconductor Ltd Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements
FR2947949B1 (fr) 2009-07-08 2012-03-02 Centre Nat Rech Scient Module electronique de puissance
US8853816B2 (en) 2012-12-05 2014-10-07 Nxp B.V. Integrated circuits separated by through-wafer trench isolation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3079254A (en) * 1959-01-26 1963-02-26 George W Crowley Photographic fabrication of semiconductor devices
US3158788A (en) * 1960-08-15 1964-11-24 Fairchild Camera Instr Co Solid-state circuitry having discrete regions of semi-conductor material isolated by an insulating material
US3290753A (en) * 1963-08-19 1966-12-13 Bell Telephone Labor Inc Method of making semiconductor integrated circuit elements
US3307239A (en) * 1964-02-18 1967-03-07 Bell Telephone Labor Inc Method of making integrated semiconductor devices

Also Published As

Publication number Publication date
DE1439712A1 (de) 1968-11-28
DE1439741B2 (de) 1975-01-09
DE1439741A1 (de) 1969-09-04
GB1124627A (en) 1968-08-21
GB1124628A (en) 1968-08-21
DE1439728A1 (de) 1969-11-06
SE337871B (de) 1971-08-23
DE1439741C3 (de) 1975-08-21
FR1453410A (fr) 1966-06-03
US3689992A (en) 1972-09-12

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