CH468721A - Verfahren zum gleichzeitigen Herstellen einer Vielzahl von Halbleiterbauelementen - Google Patents

Verfahren zum gleichzeitigen Herstellen einer Vielzahl von Halbleiterbauelementen

Info

Publication number
CH468721A
CH468721A CH1146467A CH1146467A CH468721A CH 468721 A CH468721 A CH 468721A CH 1146467 A CH1146467 A CH 1146467A CH 1146467 A CH1146467 A CH 1146467A CH 468721 A CH468721 A CH 468721A
Authority
CH
Switzerland
Prior art keywords
multiplicity
semiconductor components
simultaneous manufacture
simultaneous
manufacture
Prior art date
Application number
CH1146467A
Other languages
English (en)
Inventor
Puetter Lothar
Lutz Gerhard
Riermeier Manfred
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of CH468721A publication Critical patent/CH468721A/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/13—Containers comprising a conductive base serving as an interconnection
    • H10W76/138—Containers comprising a conductive base serving as an interconnection having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07336—Soldering or alloying
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/4981—Utilizing transitory attached element or associated separate material
CH1146467A 1966-08-26 1967-08-15 Verfahren zum gleichzeitigen Herstellen einer Vielzahl von Halbleiterbauelementen CH468721A (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DES105551A DE1277446B (de) 1966-08-26 1966-08-26 Verfahren zum Herstellen von Halbleiterbauelementen mit vollstaendig gekapseltem Halbleiterelement
DE1564720A DE1564720C3 (de) 1966-08-26 1966-09-22 Verfahren zum gleichzeitigen Herstellen einer Vielzahl von Halbleiteranordnungen
DE1564770A DE1564770C3 (de) 1966-08-26 1966-12-03 Verfahren zum gleichzeitigen Herstellen einer Vielzahl von Halbleiteranordnungen

Publications (1)

Publication Number Publication Date
CH468721A true CH468721A (de) 1969-02-15

Family

ID=27212985

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1146467A CH468721A (de) 1966-08-26 1967-08-15 Verfahren zum gleichzeitigen Herstellen einer Vielzahl von Halbleiterbauelementen

Country Status (7)

Country Link
US (2) US3531858A (de)
BE (1) BE702724A (de)
CH (1) CH468721A (de)
DE (3) DE1277446B (de)
GB (2) GB1168357A (de)
NL (1) NL6711275A (de)
SE (1) SE317138B (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849880A (en) * 1969-12-12 1974-11-26 Communications Satellite Corp Solar cell array
FR2102512A5 (de) * 1970-08-06 1972-04-07 Liaison Electr Silec
US3698073A (en) * 1970-10-13 1972-10-17 Motorola Inc Contact bonding and packaging of integrated circuits
DE3036260A1 (de) * 1980-09-26 1982-04-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur herstellung von elektrischen kontakten an einer silizium-solarzelle
US6190947B1 (en) * 1997-09-15 2001-02-20 Zowie Technology Corporation Silicon semiconductor rectifier chips and manufacturing method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE529799C (de) * 1931-07-17 Kloeckner Werke A G Abtlg Mann Verfahren zur Herstellung von Messerklingen
DE379716C (de) * 1923-08-27 Olof Oskar Kring Zusammenloeten von Metallgegenstaenden
DE708363C (de) * 1936-11-13 1941-07-18 Fried Krupp Akt Ges Einrichtung zum Loeten in einer reduzierenden Gasatmosphaere
NL96632C (de) * 1955-07-06
NL222168A (de) * 1957-11-05
US3155936A (en) * 1958-04-24 1964-11-03 Motorola Inc Transistor device with self-jigging construction
US2994121A (en) * 1958-11-21 1961-08-01 Shockley William Method of making a semiconductive switching array
DE1831308U (de) * 1960-09-27 1961-05-18 Standard Elektrik Lorenz Ag Hochspannungsgleichrichter.
NL256344A (de) * 1960-09-28
DE1188731B (de) * 1961-03-17 1965-03-11 Intermetall Verfahren zum gleichzeitigen Herstellen von mehreren Halbleiteranordnungen
DE1180067C2 (de) * 1961-03-17 1970-03-12 Elektronik M B H Verfahren zum gleichzeitigen Kontaktieren mehrerer Halbleiteranordnungen
DE1199408B (de) * 1961-06-28 1965-08-26 Siemens Ag Verfahren zum Herstellen von Halbleiterbau-elementen und nach diesem Verfahren hergestelltes Halbleiterbauelement
US3270399A (en) * 1962-04-24 1966-09-06 Burroughs Corp Method of fabricating semiconductor devices

Also Published As

Publication number Publication date
DE1564720A1 (de) 1970-09-17
DE1564720B2 (de) 1977-08-04
GB1168357A (en) 1969-10-22
DE1564770C3 (de) 1980-07-10
US3550262A (en) 1970-12-29
NL6711275A (de) 1968-02-27
DE1564770A1 (de) 1971-01-28
BE702724A (de) 1968-01-15
SE317138B (de) 1969-11-10
DE1564720C3 (de) 1978-04-06
DE1277446B (de) 1968-09-12
GB1168358A (en) 1969-10-22
DE1564770B2 (de) 1979-10-18
US3531858A (en) 1970-10-06

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