CH493097A - Integrated solid-state circuit with only two electrode leads - Google Patents

Integrated solid-state circuit with only two electrode leads

Info

Publication number
CH493097A
CH493097A CH248269A CH248269A CH493097A CH 493097 A CH493097 A CH 493097A CH 248269 A CH248269 A CH 248269A CH 248269 A CH248269 A CH 248269A CH 493097 A CH493097 A CH 493097A
Authority
CH
Switzerland
Prior art keywords
electrode leads
state circuit
integrated solid
integrated
solid
Prior art date
Application number
CH248269A
Other languages
German (de)
Inventor
Hans Dr Weinerth
Hartmut Dr Bleher
Original Assignee
Itt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19681639176 external-priority patent/DE1639176C3/en
Application filed by Itt filed Critical Itt
Publication of CH493097A publication Critical patent/CH493097A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
CH248269A 1968-02-23 1969-02-19 Integrated solid-state circuit with only two electrode leads CH493097A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19681639176 DE1639176C3 (en) 1968-02-23 1968-02-23 Temperature-compensated Zener diode arrangement in the form of a semiconductor circuit

Publications (1)

Publication Number Publication Date
CH493097A true CH493097A (en) 1970-06-30

Family

ID=5683973

Family Applications (1)

Application Number Title Priority Date Filing Date
CH248269A CH493097A (en) 1968-02-23 1969-02-19 Integrated solid-state circuit with only two electrode leads

Country Status (7)

Country Link
CH (1) CH493097A (en)
DE (1) DE1639176B2 (en)
ES (1) ES363985A1 (en)
FR (1) FR2002487A1 (en)
GB (1) GB1230880A (en)
NL (1) NL6902799A (en)
SE (1) SE358050B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0307844A3 (en) * 1987-09-14 1989-07-19 Fujitsu Limited Semiconductor integrated circuit having interconnection with improved design flexibility
EP0379878A1 (en) * 1989-01-23 1990-08-01 Motorola, Inc. Substrate power supply contact for power integrated circuits
EP0382504A3 (en) * 1989-02-09 1992-08-26 Fujitsu Limited Semiconductor integrated circuit having interconnection with improved design flexibility
EP0619920B1 (en) * 1991-12-30 1999-10-06 Bernd HÖFFLINGER Integrated circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5965930A (en) * 1997-11-04 1999-10-12 Motorola, Inc. High frequency bipolar transistor and method of forming the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0307844A3 (en) * 1987-09-14 1989-07-19 Fujitsu Limited Semiconductor integrated circuit having interconnection with improved design flexibility
US5072274A (en) * 1987-09-14 1991-12-10 Fujitsu Limited Semiconductor integrated circuit having interconnection with improved design flexibility
EP0379878A1 (en) * 1989-01-23 1990-08-01 Motorola, Inc. Substrate power supply contact for power integrated circuits
EP0382504A3 (en) * 1989-02-09 1992-08-26 Fujitsu Limited Semiconductor integrated circuit having interconnection with improved design flexibility
EP0619920B1 (en) * 1991-12-30 1999-10-06 Bernd HÖFFLINGER Integrated circuit

Also Published As

Publication number Publication date
ES363985A1 (en) 1971-01-01
NL6902799A (en) 1969-08-26
DE1639176A1 (en) 1970-08-20
DE1639176B2 (en) 1971-02-25
FR2002487A1 (en) 1969-10-17
GB1230880A (en) 1971-05-05
SE358050B (en) 1973-07-16

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Legal Events

Date Code Title Description
PL Patent ceased