CH529446A - Selbstausrichtendes Maskierverfahren, insbesondere für Halbleiteroberflächen - Google Patents

Selbstausrichtendes Maskierverfahren, insbesondere für Halbleiteroberflächen

Info

Publication number
CH529446A
CH529446A CH1217971A CH1217971A CH529446A CH 529446 A CH529446 A CH 529446A CH 1217971 A CH1217971 A CH 1217971A CH 1217971 A CH1217971 A CH 1217971A CH 529446 A CH529446 A CH 529446A
Authority
CH
Switzerland
Prior art keywords
self
masking process
semiconductor surfaces
aligning
aligning masking
Prior art date
Application number
CH1217971A
Other languages
English (en)
Inventor
F Dr Broom Ronald
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Priority to CH1217971A priority Critical patent/CH529446A/de
Priority to DE2234189A priority patent/DE2234189A1/de
Priority to JP47071364A priority patent/JPS4831878A/ja
Priority to FR7228653A priority patent/FR2149384A1/fr
Publication of CH529446A publication Critical patent/CH529446A/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
CH1217971A 1971-08-19 1971-08-19 Selbstausrichtendes Maskierverfahren, insbesondere für Halbleiteroberflächen CH529446A (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CH1217971A CH529446A (de) 1971-08-19 1971-08-19 Selbstausrichtendes Maskierverfahren, insbesondere für Halbleiteroberflächen
DE2234189A DE2234189A1 (de) 1971-08-19 1972-07-12 Verfahren zur maskierung von halbleiteroberflaechen
JP47071364A JPS4831878A (de) 1971-08-19 1972-07-18
FR7228653A FR2149384A1 (en) 1971-08-19 1972-08-03 Semiconductor component prodn - with automatic precision mask location esp for fets

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1217971A CH529446A (de) 1971-08-19 1971-08-19 Selbstausrichtendes Maskierverfahren, insbesondere für Halbleiteroberflächen

Publications (1)

Publication Number Publication Date
CH529446A true CH529446A (de) 1972-10-15

Family

ID=4380613

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1217971A CH529446A (de) 1971-08-19 1971-08-19 Selbstausrichtendes Maskierverfahren, insbesondere für Halbleiteroberflächen

Country Status (4)

Country Link
JP (1) JPS4831878A (de)
CH (1) CH529446A (de)
DE (1) DE2234189A1 (de)
FR (1) FR2149384A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2424629A1 (fr) * 1978-04-28 1979-11-23 Ates Componenti Elettron Processus de fabrication d'elements resistants pour circuits integres

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3426421A1 (de) * 1984-07-18 1986-01-23 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen einer halbleiteranordnung

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2424629A1 (fr) * 1978-04-28 1979-11-23 Ates Componenti Elettron Processus de fabrication d'elements resistants pour circuits integres

Also Published As

Publication number Publication date
FR2149384A1 (en) 1973-03-30
FR2149384B1 (de) 1974-07-12
JPS4831878A (de) 1973-04-26
DE2234189A1 (de) 1973-03-01

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Legal Events

Date Code Title Description
PL Patent ceased