JPS4831878A - - Google Patents

Info

Publication number
JPS4831878A
JPS4831878A JP47071364A JP7136472A JPS4831878A JP S4831878 A JPS4831878 A JP S4831878A JP 47071364 A JP47071364 A JP 47071364A JP 7136472 A JP7136472 A JP 7136472A JP S4831878 A JPS4831878 A JP S4831878A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP47071364A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4831878A publication Critical patent/JPS4831878A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
JP47071364A 1971-08-19 1972-07-18 Pending JPS4831878A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1217971A CH529446A (de) 1971-08-19 1971-08-19 Selbstausrichtendes Maskierverfahren, insbesondere für Halbleiteroberflächen

Publications (1)

Publication Number Publication Date
JPS4831878A true JPS4831878A (de) 1973-04-26

Family

ID=4380613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP47071364A Pending JPS4831878A (de) 1971-08-19 1972-07-18

Country Status (4)

Country Link
JP (1) JPS4831878A (de)
CH (1) CH529446A (de)
DE (1) DE2234189A1 (de)
FR (1) FR2149384A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1094517B (it) * 1978-04-28 1985-08-02 Componenti Elettronici Sgs Ate Procedimento per la fabbricazione di un elemento resistivo filiforme per circuito integrato
DE3426421A1 (de) * 1984-07-18 1986-01-23 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen einer halbleiteranordnung

Also Published As

Publication number Publication date
FR2149384B1 (de) 1974-07-12
DE2234189A1 (de) 1973-03-01
FR2149384A1 (en) 1973-03-30
CH529446A (de) 1972-10-15

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