CN101556830B - Shift register and grid electrode driving device thereof - Google Patents

Abstract

The invention relates to a shift register and a gate driving device thereof. The shift register includes six thin film transistors directly deposited on the array substrate, wherein a capacitor is set between the gate and the source of the first thin film transistor, and its drain is connected to the first clock signal output terminal; the gate of the second thin film transistor The pole is connected to the gate of the third thin film transistor; the gate of the fourth thin film transistor is connected to the drain, the drain is connected to the shift start signal output terminal or the output terminal of the previous stage, and the source is connected to the first thin film transistor The gate of the fifth thin film transistor is connected to the first clock signal output end; the gate of the sixth thin film transistor is connected to the second clock signal output end. The invention maintains the invalid state of the output end of the current stage, the gate line will not float, and will not be affected by other noise voltages connected to the gate line, and the shift register will reliably maintain the invalid state without causing erroneous operations.

Description

Shift register and its gate driving device

technical field

The invention relates to a shift register and a gate drive device thereof, in particular to a shift register of a liquid crystal display and a gate drive device thereof. the

Background technique

Thin film transistor liquid crystal display (TFT-LCD) has the characteristics of light weight, thin thickness and low power consumption, and is widely used in mobile phones, monitors, televisions and other devices. the

In order to display images, TFT-LCD displays with a progressive scan matrix of m×n dots. The TFT-LCD driver mainly includes a gate driver and a data driver. The data driver latches the input display data and clock signals in a timing sequence, converts them into analog signals and inputs them to the data lines of the LCD panel, and the gate driver passes the input clock signals through The shift register is converted and switched to turn on/off voltage, which is applied to the grid lines of the liquid crystal panel in sequence. In an active matrix thin film transistor liquid crystal display (AMTFT-LCD), the shift register in the gate driver is used to generate a scan signal for scanning the gate lines, and the shift register in the data driver is used to select the data line module. the

In the shift register in the prior art, the shift register is composed of stages. The start signal of the first stage is connected to the input terminal, and several gate lines are selected in order according to the output signals of each stage. In the operation of the shift register, it is required that all stages of the shift register remain in the disabled state at all times other than the effective (inable) state, but the shift register in the prior art makes the gate line floating (floating), and is affected by the noise voltage at the same time. The stages of the shift register cannot remain inactive, resulting in erroneous operation. 4 is a schematic structural diagram of a shift register in the prior art, which includes four thin film transistors, wherein the drain of the first thin film transistor M1 is connected to the clock signal output terminal CKV, a capacitor Cb is set between the gate and the source, and the source is connected to the second TFT. The drain of the second thin film transistor M2 is connected to the output terminal OUTn of the current stage; the source of the second thin film transistor M2 is connected to the negative terminal VSS of the power supply, the gate is connected to the gate of the third thin film transistor M3, and connected to the next The stage output terminal OUTn+1 is connected; the source of the third thin film transistor M3 is connected to the negative power supply terminal VSS, and the drain is respectively connected to the gate of the first thin film transistor M1 and the source of the fourth thin film transistor M4; the fourth thin film transistor The drain of M4 is connected to its gate, and is connected to the output terminal OUTn-1 of the previous stage. As shown in Figure 4, when the first thin film transistor M1 and the second thin film transistor M2 are in the inactive state of being turned off, the gate line will float, therefore, the shift register cannot maintain Invalid state and results in erroneous operation. the

In the prior art, in order to maintain the invalid state of each stage of the shift register and prevent erroneous operations, a method of adding an extra power supply circuit is generally adopted, but this method directly leads to an increase in cost. the

Contents of the invention

The purpose of the present invention is to provide a shift register and a gate driving device thereof, which can effectively overcome technical defects such as gate floating of the existing shift register and other technical defects. the

In order to achieve the above object, the present invention provides a shift register, including six thin film transistors deposited directly on the array substrate, wherein the six thin film transistors are:

The first thin film transistor has a capacitance between its gate and source, its drain is connected to the first clock signal output terminal, and its source is connected to the output terminal of the current stage;

The gate of the second thin film transistor is connected to the output terminal of the next stage, its drain is connected to the output terminal of the current stage, and its source is connected to the negative terminal of the power supply;

The gate of the third thin film transistor is respectively connected to the gate of the second thin film transistor and the output terminal of the next stage, its drain is connected to the gate of the first thin film transistor, and its source is connected to the negative terminal of the power supply;

The gate of the fourth thin film transistor is connected to its drain, its drain is connected to the output terminal of the shift start signal or the output terminal of the previous stage, and its source is connected to the gate of the first thin film transistor and the gate of the third thin film transistor respectively. drain connection;

The gate of the fifth thin film transistor is connected to the first clock signal output terminal, the drain is respectively connected to the gate and drain of the fourth thin film transistor, and the source is connected to the output terminal of the current stage;

The gate of the sixth thin film transistor is connected to the second clock signal output terminal, the drain is connected to the source of the fifth thin film transistor and the output terminal of the current stage, and the source is connected to the negative terminal of the power supply. the

In order to achieve the above object, the present invention also provides a gate drive device, including a shift start signal output terminal and five shift registers, wherein the five shift registers are respectively connected to the negative terminal of the power supply and the output terminal of the first clock signal. It is connected with the second clock signal output end, and among the five shift registers, the first shift register is connected with the shift start signal output end and has a first output end; the second shift register is connected with the first shift register The first output end of the register is connected, and its second output end is connected with the first shift register; the third shift register is connected with the second output end of the second shift register, and its third output end is connected with the first shift register. Two shift registers are connected; the fourth shift register is connected with the third output end of the third shift register, and its fourth output end is connected with the third shift register; the fifth shift register is connected with the fourth shift register The fourth output terminal of is connected, and has a fifth output terminal. the

The present invention proposes a shift register and a gate drive device directly deposited on the array substrate, and the high level sequentially output by the first clock signal output terminal and the second clock signal output terminal effectively maintains the invalidity of the output terminal of the current stage. state, the gate line will not float, and will not be affected by other noise voltages connected to the gate line, and the shift register will reliably maintain an invalid state without causing erroneous operations. Compared with the technical solution of adding an extra power supply circuit in order to prevent wrong operation in the prior art, the present invention does not need to add an extra power supply circuit, and has the characteristics of low cost and the like. the

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. the

Description of drawings

Fig. 1 a is the equivalent circuit diagram of a kind of structure of shift register of the present invention;

Fig. 1 b is the equivalent circuit diagram of another kind of structure of shift register of the present invention;

Fig. 2 is the working sequence diagram of shift register of the present invention;

FIG. 3 is a schematic structural diagram of a gate drive device of the present invention;

FIG. 4 is a schematic structural diagram of a shift register in the prior art. the

Detailed ways

Fig. 1a is an equivalent circuit diagram of one structure of the shift register of the present invention, and Fig. 1b is an equivalent circuit diagram of another structure of the shift register of the present invention. As shown in Figure 1a and Figure 1b, the main structure of the shift register of the present invention includes six thin film transistors and corresponding input and output terminals, and the six thin film transistors are respectively the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor The input and output terminals of the transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 are respectively the output terminal OUTn of the current stage, the output terminal OUTn-1 of the previous stage, the output terminal OUTn+1 of the next stage, The first clock signal output terminal CKV1 , the second clock signal output terminal CKV2 , the shift start signal output terminal STV and the negative power supply terminal VSS. the

Specifically, a capacitor Cb is provided between the gate and source of the first thin film transistor T1, its drain is connected to the first clock signal output terminal CKV1, and its source is connected to the output terminal OUTn of the current stage; the second thin film transistor T2 The gate is connected to the gate of the third thin film transistor T3, and connected to the output terminal OUTn+1 of the next stage, and its drain is connected to the source of the first thin film transistor T1, and connected to the output terminal OUTn of the current stage, and its source is connected to The negative terminal VSS of the power supply is connected; the gate of the third thin film transistor T3 is connected to the gate of the second thin film transistor T2, and connected to the output terminal OUTn+1 of the next stage, and its drain is respectively connected to the gate of the first thin film transistor T1 and The source of the fourth thin film transistor T4 is connected, and its source is connected to the negative power supply terminal VSS; the gate of the fourth thin film transistor T4 is connected to its drain, and its drains are respectively connected to the drain of the fifth thin film transistor T5, and connected to The shift start signal output terminal STV or the output terminal OUTn-1 of the previous stage, its source is respectively connected to the gate of the first thin film transistor T1 and the drain of the third thin film transistor T3; the gate of the fifth thin film transistor T5 connected to the first clock signal output terminal CKV1, its drain connected to the gate and drain of the fourth thin film transistor T4, its source connected to the drain of the sixth thin film transistor T6, and connected to the output terminal OUTn of the current stage; The gate of the sixth thin film transistor T6 is connected to the second clock signal output terminal CKV2, the drain is connected to the source of the fifth thin film transistor T5, and connected to the output terminal OUTn of the current stage, and the source is connected to the negative power supply terminal VSS. Since the thin film transistor of the present invention is directly deposited on the array substrate, the source and the drain are opposite, and in actual use, the corresponding source can be set as the drain, and the corresponding drain can be set as the source. the

Fig. 2 is a working sequence diagram of the shift register of the present invention. As shown in Figure 1a and Figure 2, for the shift register at the first position, first the first clock signal output terminal CKV1 outputs a high level (the second clock signal output terminal CKV2 is low level), because the fifth film The gate of the transistor T5 is connected to the first clock signal output terminal CKV1, so the fifth thin film transistor T5 is started, and the source and drain of the fifth thin film transistor T5 are turned on; The start signal output terminal STV is connected, the source of the fifth thin film transistor T5 is connected to the output terminal OUTn of the current stage, and at this time, the output of the shift start signal output terminal STV is low, so the output terminal OUTn of the current stage is also low level, remain inactive. During this process, since the output terminal OUTn+1 of the next stage is at low level, the second thin film transistor T2 and the third thin film transistor T3 are in an off state; since the second clock signal output terminal CKV2 is at low level, the sixth thin film transistor T6 is in cut-off state. the

Then the second clock signal output terminal CKV2 outputs a high level (the first clock signal output terminal CKV1 is low level), and since the gate of the sixth thin film transistor T6 is connected to the second clock signal output terminal CKV2, the sixth thin film transistor T6 T6 starts, and the source and drain of the sixth thin film transistor T6 are turned on; since the drain of the sixth thin film transistor T6 is connected to the output terminal OUTn of the current stage, and the source of the sixth thin film transistor T6 is connected to the negative terminal VSS of the power supply, so The output terminal OUTn of this stage is also low level and remains in an invalid state. During this process, the output of the shift start signal output terminal STV is at a high level, and since the gate of the fourth thin film transistor T4 is connected to its drain, the fourth thin film transistor T4 is activated, and the source of the fourth thin film transistor T4 It is connected with the drain, and the source of the fourth thin film transistor T4 is also at a high level. Since the output terminal OUTn of this stage is at a low level at this time, the source of the fourth thin film transistor T4 at a high level is connected to the low level. The capacitor Cb between the flat output terminals OUTn of the current stage is charged. Since the output terminal OUTn+1 of the next stage is at low level, the second thin film transistor T2 and the third thin film transistor T3 are in a cut-off state. the

Then the first clock signal output terminal CKV1 outputs a high level (the second clock signal output terminal CKV2 and the shift start signal output terminal STV are low level), then the fifth thin film transistor T5 is in a conducting state, and the fourth thin film transistor T4 is in the off state, the charge accumulated in the capacitor Cb makes the gate of the first thin film transistor T1 at a high level, the first thin film transistor T1 is started, the source and drain of the first thin film transistor T1 are turned on, and the first clock signal The high level output by the output terminal CKV1 is output by the output terminal OUTn of the current stage. During this process, since the output terminal OUTn+1 of the next stage is at low level, the second thin film transistor T2 and the third thin film transistor T3 are in an off state; since the second clock signal output terminal CKV2 is at low level, the sixth thin film transistor T6 is in cut-off state. the

After that, the shift start signal output terminal STV is always low level, the second clock signal output terminal CKV2 outputs high level (the first clock signal output terminal CKV1 is low level), the sixth thin film transistor T6 is activated, The source and drain of the sixth thin film transistor T6 are turned on; since the drain of the sixth thin film transistor T6 is connected to the output terminal OUTn of the current stage, and the source of the sixth thin film transistor T6 is connected to the negative terminal VSS of the power supply, the output of the current stage Terminal OUTn is also low level and remains inactive. During this process, since the output terminal OUTn+1 of the next stage is at a high level, the second thin film transistor T2 and the third thin film transistor T3 are in the conduction state, and the source and drain of the second thin film transistor T2 are turned on so that the current stage The output terminal OUTn is connected to the negative terminal VSS of the power supply, which further ensures the low level of the output terminal OUTn of this stage, and the source and drain of the third thin film transistor T3 are turned on so that the source of the fourth thin film transistor T4 is connected to the low level. The capacitor Cb between the output terminals OUTn of the current stage is discharged. Therefore, no matter whether the first thin film transistor T1 and the second thin film transistor T2 are pulled up (pull-up) or pulled down (pull-down), the output terminal OUTn of the current stage remains inactive. the

For the shift register located in the second position and subsequent positions, its working principle is basically the same as the aforementioned process, the difference is that since the gate of the fourth thin film transistor T4 is connected to the output terminal OUTn-1 of the previous stage, in When the output terminal OUTn-1 of the upper stage outputs a high level, the fourth thin film transistor T4 is activated, so that the capacitor Cb between the source of the fourth thin film transistor T4 at a high level and the output terminal OUTn of the current stage at a low level is charged. , and realize the high-level output of this stage at the next moment. the

As shown in Figure 1b and Figure 2, first the first clock signal output terminal CKV1 outputs a high level (the second clock signal output terminal CKV2 is low level), the fifth thin film transistor T5 is started, and its source and drain are turned on , because the drain of the fifth thin film transistor T5 is connected to the low-level output terminal of the previous stage, so the output terminal of the current stage is also low-level and remains inactive. During this process, the second thin film transistor T2, the third thin film transistor T3 and the sixth thin film transistor T6 are in an off state. the

Then the second clock signal output terminal CKV2 outputs a high level (the first clock signal output terminal CKV1 is low level), the sixth thin film transistor T6 starts, and its source and drain are turned on, because the sixth thin film transistor T6 The source of the power supply is connected to the negative terminal VSS of the power supply, so the output terminal of this stage is also at a low level and remains in an invalid state. During this process, the second thin film transistor T2 and the third thin film transistor T3 are in an off state. the

Afterwards, the first clock signal output terminal CKV1 outputs a high level (the second clock signal output terminal CKV2 is low level), the fifth thin film transistor T5 is started, and its source and drain are turned on. terminal outputs a high level, and the drain of the fifth thin film transistor T5 is connected to the output terminal of the previous stage, so the high level output from the output terminal of the previous stage is output by the output terminal of the current stage. During this process, the second thin film transistor T2, the third thin film transistor T3 and the sixth thin film transistor T6 are in an off state. the

After that, the output terminal of the upper stage is always at low level, the second clock signal output terminal CKV2 outputs high level (the first clock signal output terminal CKV1 is low level), the sixth thin film transistor T6 is activated, and its source Conducted with the drain, the output of this stage is low and remains inactive. During this process, the second thin film transistor T2 and the third thin film transistor T3 are in the conduction state, which further ensures the low level of the output terminal of the current stage, and at the same time makes the source of the fourth thin film transistor T4 and the low level output terminal of the current stage The capacitor Cb between discharges. Therefore, no matter whether the first thin film transistor T1 and the second thin film transistor T2 are pulled up (pull-up) or pulled down (pull-down), the output terminal of the current stage remains inactive. the

The working process of other position shift registers can be obtained through the structure shown in FIG. 1 b and the working sequence diagram shown in FIG. 2 , and will not be repeated here. the

It can be seen from the above technical solution of the present invention that the shift register of the present invention effectively maintains the invalid state of the output terminal through the high level sequentially output by the first clock signal output terminal CKV1 and the second clock signal output terminal CKV2, and the gate line will not appear Floating and unaffected by other noise voltages connected to the gate lines, the shift register remains reliably inactive without causing erroneous operation. the

The shift register of the present invention can be realized by 5 masking processes or 4 masking processes in the liquid crystal display array process, by arranging thin film transistors in the vacant part outside the active area of the substrate or at the edge of the substrate, and then directly depositing them on the array substrate. the

FIG. 3 is a schematic structural diagram of a gate driving device of the present invention. As shown in FIG. 3, the main structure of the gate driving device includes five shift registers, a shift start signal output terminal STV, a first clock signal output terminal CKV1, a second clock signal output terminal CKV2, and a negative power supply terminal VSS. Each shift register is respectively connected to the negative power supply terminal VSS, the first clock signal output terminal CKV1 and the second clock signal output terminal CKV2, wherein each shift register is connected to the negative power supply terminal VSS for receiving the gate cut-off voltage , each shift register is connected to the first clock signal output terminal CKV1 and the second clock signal output terminal CKV2 for receiving the first clock signal and the second clock signal, further, the first shift register SFT1 and the second shift register SFT1 The second output terminal OUT2 of the register SFT2 is connected to receive the second output signal of the second shift register SFT2, while the first output terminal OUT1 of the first shift register SFT1 is connected to the second shift register SFT2 for providing The second shift register SFT2 outputs the first output signal. The second shift register SFT2 is connected to the third output terminal OUT3 of the third shift register SFT3 for receiving the third output signal of the third shift register SFT3, while the second output terminal OUT2 of the second shift register SFT2 is connected to the second output terminal OUT2 of the second shift register SFT3. The three shift registers SFT3 are connected to output the second output signal to the third shift register SFT3. The third shift register SFT3 is connected to the fourth output terminal OUT4 of the fourth shift register SFT4 for receiving the fourth output signal of the fourth shift register SFT4, while the third output terminal OUT3 of the third shift register SFT3 is connected to the fourth output terminal OUT4 of the fourth shift register SFT4. The fourth shift register SFT4 is connected to output the third output signal to the fourth shift register SFT4. The fourth shift register SFT4 is connected to the fifth output terminal OUT5 of the fifth shift register SFT5 for receiving the fifth output signal of the fifth shift register SFT5, while the fourth output terminal OUT4 of the fourth shift register SFT4 is connected to The fifth shift register SFT5 is connected to output the fourth output signal to the fifth shift register SFT5. The fifth output terminal OUT5 of the fifth shift register SFT5 is connected to the fourth shift register SFT4 for outputting a fifth output signal to the fourth shift register SFT4. the

The shift start signal output terminal STV first outputs a start pulse, and then the first shift register SFT1 receives the first clock signal and the second clock signal from the first clock signal output terminal CKV1 and the second clock signal output terminal CKV2 respectively. A clock signal is a high-level pulse, and the second clock signal is a high-level pulse following the first clock signal. The first shift register SFT1 of the present invention with the structure shown in Figure 1a works, and the working process is no longer repeated. ; After the first output terminal OUT1 of the first shift register SFT1 outputs the first output signal to the second shift register SFT2, the second shift register SFT2 outputs the clock signal from the first clock signal output terminal CKV1 and the second clock signal output terminal CKV2 respectively. Receive the first clock signal and the second clock signal, the second clock signal is a high level pulse, the first clock signal is a high level pulse next to the second clock signal, the first clock signal of the present invention having the structure shown in Figure 1b The two shift registers SFT2 work, repeat the above process, and realize the progressive scanning of the liquid crystal display. the

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention without limitation, although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be Modifications or equivalent replacements can be made without departing from the spirit and scope of the technical solutions of the present invention. the

Claims (2)

1. A shift register, characterized in that it comprises six thin film transistors directly deposited on the array substrate, wherein the six thin film transistors are respectively: The first thin film transistor has a capacitance between its gate and source, its drain is connected to the first clock signal output terminal, and its source is connected to the output terminal of the current stage; The gate of the second thin film transistor is connected to the output terminal of the next stage, the drain is connected to the output terminal of the current stage, and the source is connected to the negative terminal of the power supply; The gate of the third thin film transistor is respectively connected to the gate of the second thin film transistor and the output terminal of the next stage, the drain is connected to the gate of the first thin film transistor, and the source is connected to the negative terminal of the power supply; The gate of the fourth thin film transistor is connected to its drain, its drain is connected to the output terminal of the shift start signal or the output terminal of the previous stage, and its source is connected to the gate of the first thin film transistor and the gate of the third thin film transistor respectively. drain connection; The gate of the fifth thin film transistor is connected to the first clock signal output terminal, the drain is respectively connected to the gate and drain of the fourth thin film transistor, and the source is connected to the output terminal of the current stage; The gate of the sixth thin film transistor is connected to the second clock signal output terminal, the drain is connected to the source of the fifth thin film transistor and the output terminal of the current stage, and the source is connected to the negative terminal of the power supply. 2. A gate drive device comprising the shift register according to claim 1, characterized in that it comprises a shift start signal output terminal and five shift registers, wherein the five shift registers are respectively connected to the negative terminal of the power supply, The first clock signal output end is connected with the second clock signal output end, and among the five shift registers, the first shift register is connected with the shift start signal output end and has a first output end; the second shift register The register is connected with the first output end of the first shift register, and its second output end is connected with the first shift register; the third shift register is connected with the second output end of the second shift register, and its third The output end is connected with the second shift register; the fourth shift register is connected with the third output end of the third shift register, and its fourth output end is connected with the third shift register; the fifth shift register It is connected with the fourth output end of the fourth shift register and has a fifth output end.

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