CN1062995A - Improving one's methods of a kind of electro static discharge characteristic of semiconductor device - Google Patents

Abstract

The present invention relates to methods of improving electrostatic discharge (ESD) characteristics. Especially for the method for improving the ESD characteristic of semiconductor device, the present invention does not adopt ESD protective pattern, by making the actual space between n ⁺ region and isolation layer be greater than the actual space between n ⁺ region and semiconductor substrate, introduce vertical breakdown, thereby It can improve the ESD characteristics to about 2000 volts.

Description

The present invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method of a semiconductor device with improved electrostatic discharge characteristics without the need for electrostatic discharge (hereinafter referred to as "E, S, D") protection patterns (Saftguarded pattern).

Generally speaking, the substrate PnP transistor consists of an n-type epitaxial layer 2 grown on a P-type silicon substrate 1, an isolation layer 3 formed by diffusing P-type impurities in a designated area on the n-type epitaxial layer 2, And the P ⁺ region 4 and the n ⁺ region 5 formed in the specified area on the surface of the n-type epitaxial layer as the emitter region and the base region of the PnP transistor respectively, as shown in Fig. 1A and Fig. 1B .

A problem with substrate PnP transistors is that the electrostatic discharge characteristic voltage between the base and collector is low (about 400V to 600V).

Conventional methods to improve E.S.D characteristics, such as using SCR (silicon controlled silicon) and voltage BVceo (the breakdown voltage of the emitter cammen transistor when the base is open), have been widely used.

Although the E, S, and D characteristics can be improved by using the SCR method, there is still a problem that the capacitance value increases due to the E.S.D protection pattern.

The structure of improving E.S.D by using common emitter transistor base open circuit breakdown voltage BVceo includes:

A base 5a is added on the common substrate PnP transistor, as shown in Fig. 1C.

The substrate PnP transistor consists of an n-type epitaxial layer 2 grown on a P-type silicon substrate 1, an isolation layer 3 formed by diffusing P-type impurities on a designated area of the n-type epitaxial layer 2, and an n-type epitaxial layer as a base region. The P ⁺ region 4, 4a and the n ⁺ region 5, 5a formed in the specified area on the surface of the epitaxial layer are shown in Fig. 1c.

In order to improve the E, S, D characteristics, the n ⁺ region 5 as the base of the PnP transistor constitutes the collector of the parasitic nPn transistor, correspondingly, this constitutes a parasitic nPn transistor with the base region 4a open.

Figure 1D shows the equivalent circuit of a common-emitter transistor with an open base, as shown in Figure 1C.

The E, S, and D characteristics between the base and the collector are improved to a certain extent, but when a high-frequency signal is input, the substrate PnP transistor has such a problem that due to the bias of the capacitance Cex to the base of the parasitic transistor cause malfunction.

There are many difficulties when the above two methods for improving E, S, and D characteristics are actually applied to semiconductor devices.

Moreover, in a common transistor, the lateral space between the n ⁺ region 5 and the isolation layer 3 in the design task (Pdesign roLe) is larger than the vertical space between the n ⁺ region 5 and the P-type silicon substrate 1, but in the actual process However, the lateral space between the n ⁺ region 5 and the isolation layer 3 becomes smaller than the vertical space between the n ⁺ region 5 and the P-type silicon substrate 1 (diminishing).

Correspondingly, when the ESD phenomenon occurs, the E, S, and D characteristics will become lower due to the lateral breakdown caused by the current flowing through the narrow space between the n ⁺ region 5 and the isolation layer 3 .

In order to solve the aforementioned problems, the present invention does not use E.S.D protection patterns to maintain the substrate PnP transistor structure; at the same time, the lateral breakdown is induced into a vertical breakdown, which is beneficial to E.S.D characteristics because there is no parasitic phenomenon.

To achieve the above object, the present invention (a method of improving the electrostatic characteristics of a semiconductor device) comprises the following steps.

The first step is to form a buried layer 6 before growing the n-type epitaxial layer 2 on the semiconductor substrate 1; the second step is to form an isolation layer 3 to divide the n-type epitaxial layer 2; the third step is to form a predetermined area of the n-type epitaxial layer 2 Form the P ⁺ region 4; the fourth step is to form the n ⁺ region 5 on the designated area of the n-type epitaxial layer 2

FIG. 1A is a plan view of a conventional substrate PnP transistor structure.

Figure 1B is a cross-sectional view of a conventional substrate PnP transistor structure

Figure 1C is a plan view of a conventional substrate PnP transistor structure using the nPn transistor voltage BVceo method

FIG. 1D is an equivalent circuit diagram of a conventional substrate PnP transistor structure using the PnP transistor voltage BVceo method.

Fig. 2A is a plan view of the substrate PnP transistor structure of the present invention

Figure 2B is a cross-sectional view of the substrate PnP transistor structure of the present invention

So far, the present invention will be described with reference to the accompanying drawings

2A and 2B are structural diagrams of semiconductor devices according to the present invention

Firstly, a diffusion layer is formed in a designated area on the P-type semiconductor substrate 1 by means of diffusion; a buried layer 6 is formed before the n-type epitaxial layer 2 is grown by a common method.

Diffusion method is used to form the isolation layer 3 in the designated area of the n-type epitaxial layer 2 .

Then form a P ⁺ region 4 in the designated area on the surface of the n-type epitaxial layer 2

At this time, the actual lateral space between the n ⁺ region 5 and the isolation layer 3 is greater than the vertical space between the n ⁺ region 5 and the P-type silicon substrate 1 .

For the semiconductor device prepared according to the method, when ESD occurs, the current flows through the n ⁺ region 5, the n-type epitaxial layer 2, the buried layer 6 and the p-type silicon substrate 1 in sequence.

As mentioned above, the semiconductor device according to the present invention does not need E.S.D protection pattern, and can be used in a large number of ampere-level (Stage of AmP) inputs, because the utilization of E.S.D characteristics of the longitudinal breakdown phenomenon can reach about 2000 volts.

Claims (5)

1, a kind of method of improving semiconductor device E.S.D (static discharge) characteristic comprises the following steps:

The first step forms buried layer before n type epitaxial loayer is grown on Semiconductor substrate;

In second step, form separator to cut apart n type epitaxial loayer;

In the 3rd step, on n type epitaxial loayer, form P in the appointed area ⁺The district;

In the 4th step, on n type epitaxial loayer appointed area, form n ⁺The district.

2, a kind of the method for claim 1, wherein n ⁺The district is positioned on the same vertical line with buried layer;

3, a kind of the method for claim 1, wherein n ⁺Actual horizontal space is wider than n between district and the separator ⁺Longitudinal space between district and the P type silicon substrate.

4, a kind of the method for claim 1 wherein only has the n of narrow and small longitudinal space ⁺Introduce vertically between district and P type silicon substrate and puncture.

5, a kind of method as claimed in claim 4, wherein breakdown current is successively along n ⁺The district, n type epitaxial loayer, buried layer and P type silicon substrate path flow.