JPH0485937A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakage of a transistor by making the breakdown voltage of a separated island, where an element is made, smaller than the breakdown voltage of the element itself, and making use of the separated island itself for surge absorption. CONSTITUTION:After formation of a separated island, seeing that it does not include the part where an NPN transistor is made, phosphorus is diffused only into the epitaxial layer 9 near the separated region 4, whereby the concentration of the impurities at that part is elevated. And this impurity concentration is made so that the breakdown strengh voltage at the junction made by the separated region 4 and the epitaxial layer 3 may be smaller than the breakdown strengh voltage between the emitter and the collector of the NPN transistor. Subsequently, a base region 5, an emitter region 61, a collector contact layer 62, and aluminum wiring 8 are formed. Hereby, a semiconductor device, which has great surge breakdown resistance, can be gotten without increasing chip area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor integrated circuit of a junction-separated type, and relates to a device capable of improving surge breakdown resistance.

[Conventional technology]

The conventional technology will be explained using FIGS. 5 to 7.

FIG. 5 shows the manufacturing process of an isolation island in a conventional junction-separated semiconductor integrated circuit. Create a buried layer 2 of the mold, and add N on top of it.
Next, by diffusing boron from the surface of the epitaxial layer 3 to the semiconductor substrate 1, an isolation region 4 is formed, and the P-type silicon substrate 1 and the isolation region 4 are bonded to each other. Separated N-type isolated islands are obtained. Then, an oxide film 7 is provided on the surface, and then a semiconductor element is formed in this isolation island.

FIG. 6 shows the structure of a conventional NPN) transistor. In this case, following FIG. 5, a P-type base region 5 is created by diffusing boron from the surface of the epitaxial layer 3, and then By further diffusing phosphorus, emitter region 61 and collector contact region 62 are formed. Then, a hole for a wiring contact is opened in the oxide film 7, and a wiring 8 is formed from aluminum to complete the process.

Also, Fig. 7 shows a vertical PNP) transistor, which in this case is made in the same manner as an NPN) transistor, but
A PNP transistor is made by using the base region of the PN transistor as an emitter, an epitaxial layer as a base, and a silicon substrate as a collector.

[Problem to be solved by the invention]

All semiconductor devices manufactured in this manner have a specific breakdown voltage, and if a voltage higher than this breakdown voltage is applied to the device, a breakdown current that cannot be controlled by the device itself will flow.

If this breakdown current is small, the junction is reversible to the breakdown phenomenon, and if the voltage is removed, the junction returns to its original state and no abnormality occurs.However, if the applied voltage is excessive and the If a breakdown current flows through the device, the device will be permanently destroyed.

Usually, in order to prevent such destruction, a maximum voltage that can be applied to a semiconductor element is defined, and as long as the element is used within that range, the element can be prevented from being destroyed.

However, when considering the case where the device is actually used, there is a very high possibility that a voltage exceeding the maximum voltage will be applied due to electrostatic surges generated during handling, line surges induced in the circuit used, etc.

In order to prevent frequent destruction of elements due to such surges, regulations are set for surge voltages in addition to the maximum voltage mentioned above. In law, 200-30
A surge resistance of 0■ is required.

However, as the size of semiconductor devices has been reduced, it has become physically impossible to provide this kind of surge resistance with the devices themselves alone, so surge absorption devices such as Zener diodes have become necessary. Measures have been taken to satisfy the above surge resistance by incorporating elements. However, since there is always a possibility that an external surge will be applied to a portion where an electrode is taken out to the outside of the semiconductor chip, it is necessary to incorporate all such surge absorbing elements for each extraction electrode. Furthermore, if the surge absorbing element is made smaller, its own surge resistance will be reduced, and the surge resistance of the entire element will be reduced, so the thickness cannot be reduced unnecessarily.

In this way, in the conventional structure, it is necessary to incorporate a surge absorption element with a large area into all the extraction electrodes, and especially for elements with a large number of pins, the area occupied by this element greatly compresses the overall area of the chip. There was a problem.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor device having a large surge breakdown resistance without increasing the chip area.

[Means to solve the problem]

In the semiconductor device according to the present invention, the breakdown voltage of the isolation island on which the element is formed is made lower than the breakdown voltage of the element itself, and the isolation island itself is used for surge absorption.

[Effect]

In this invention, the breakdown voltage of the isolation island is made smaller than the breakdown voltage of the element inside the isolation island, so when a surge is applied to the element, the isolation island breaks down first and absorbs the surge. Therefore, it is possible to prevent the element from being destroyed. Further, since the size of the isolation island is sufficiently large, the overall surge resistance does not decrease due to the surge resistance of the isolation island.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

1 to 4 show cross-sectional structures of semiconductor devices according to first to fourth embodiments of the present invention, respectively. In these figures, 1 is a silicon substrate, 2 is a buried layer, and 3 is a silicon substrate. Epitaxial growth layer, 4 is aS region, 5
is NPN) base region of transistor and PNP) emitter region of transistor, 61 is NPN) emitter region of transistor, 62 is NPN) collector contact region of transistor and PNP) base contact region of transistor, 7 is oxide film, 8 is aluminum wiring, 9
is a phosphorus diffusion slope.

First, a first embodiment of the present invention will be described using FIG. 1.

FIG. 1 shows an example of an NPN transistor, and the steps up to the formation of isolation islands are similar to the conventional example explained in FIG. In the example in Figure 1, after forming the isolated island,
By diffusing phosphorus only into the epitaxial layer 9 near the isolation region 4, excluding the part where the NPN) transistor is formed, the impurity concentration in that part is increased. And this impurity concentration is minjll *!
The breakdown voltage of the junction formed by the I region 4 and the epitaxial layer 3 is
It is selected so that it is smaller than the emitter-collector breakdown voltage of the NPN transistor.

Subsequently, base region 5, emitter region 61, collector contact region 62, and aluminum wiring 8 are formed in the same manner as in FIG.

In the NPN) transistor manufactured in this way, when a surge is applied to the collector contact region 62, the junction between the isolation region 4 and the epitaxial layer 3 breaks down before the transistor breaks down, and the surge is applied to the silicon. It is possible to prevent the transistor from being destroyed due to leakage into the substrate 1.

Further, FIG. 2 shows the structure of a semiconductor device according to a second embodiment of the present invention, and this embodiment is another embodiment regarding an NPN transistor.

In this example, the method of forming the transistor is exactly the same as the conventional example shown in FIG. However, the distance between the region 4 and the buried layer 2 is set differently so that the breakdown voltage of the junction between the buried layer 2 and the substrate 1 is smaller than the emitter-collector breakdown voltage of the transistor. Since both the It fil region 4 and the buried layer 2 have high concentrations, the breakdown voltage of the buried layer 2 decreases as the distance @L between the two decreases.

Further, in FIG. 2, if the impurity concentration of the silicon substrate 1 is increased without reducing the distance, the breakdown voltage between the buried layer 2 and the silicon substrate 1 is lowered, and the same effect as in the above embodiment can be obtained.

Further, FIG. 3 shows the structure of a semiconductor device according to a third embodiment of the present invention, and this embodiment is an embodiment of a vertical PNP transistor.

The buried layer 2 is not built into the PNP (conventional structure) transistor. This is because the existence of the buried layer 2 reduces the transport efficiency of minority carriers injected from the emitter 5 in the base 3. This is because the current amplification factor decreases. However, in this example, we dare to use PNP
) By providing the buried layer 2 in the transistor, breakdown occurs between the buried layer 2 and the silicon substrate 1 when a surge is applied to the emitter. The emitter-collector breakdown voltage is determined by the breakdown voltage of the junction formed by the buried layer 2, the semiconductor substrate 1, and the isolation region.

When a surge is applied to the emitter, the surge is absorbed by the junction between the buried layer and the substrate, as in the embodiment shown in FIG. 3, so that the transistor can be prevented from being destroyed.

In addition, in conventional structures, breakdown occurs in a narrow area on the surface of the isolation region, which tends to lead to breakdown, and even if breakdown does not occur, hot carriers generated by breakdown are injected into the oxide film, causing the device to break down. However, by allowing breakdown to occur between the buried layer 2 and the silicon substrate 1, the breakdown occurs over a wide area of the buried layer 2, improving surge resistance. There are also no problems caused by hot carriers since they occur in the bulk rather than on the surface.

Next, a fourth embodiment of the present invention will be described using FIG. 4.

FIG. 4 shows an embodiment of a vertical PNP transistor, similar to the embodiment 113 above. In this example, the buried layer 2 is removed below the emitter region in order to avoid a decrease in current amplification factor due to the provision of the buried layer 2. In this case, the minority carriers injected from the emitter are not blocked by the buried layer and can crawl along this removed portion to reach the collector region, which suppresses the drop in transport efficiency and reduces the current amplification factor. can be avoided. When a surge is applied to the emitter, the surge is absorbed by the junction between the buried layer and the substrate, as in the embodiment shown in FIG. 3, so that destruction of the transistor can be prevented.

In the above embodiments, NPN and PNP transistors have been particularly described, but it goes without saying that similar effects can be obtained with other semiconductor devices.

〔Effect of the invention〕

As explained above, according to the present invention, the breakdown voltage of the isolation island on which the element is formed is made lower than the breakdown voltage of the element itself, and the isolation island itself is used for surge absorption. The isolation island enables surge absorption without incorporating a separate surge absorption element, which is extremely effective in reducing the chip area. Moreover, there is almost no need for process steps, and the process steps are minimal, so there is no increase in costs.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention with respect to an NPN transistor, and FIG.
N) A sectional view showing the structure of a transistor according to the third embodiment of the present invention; FIG. 3 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention;
5 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of a PNP transistor, FIG. 5 is a cross-sectional view showing the manufacturing process of an isolation island of a conventional semiconductor device, and FIG.
) A sectional view showing the structure of a transistor, and FIG. 7 is a sectional view showing the structure of a conventional vertical PNP transistor. In the figure, 1 is a silicon substrate, 2 is a buried layer, 3 is an epitaxial layer, 4 is an Mn region, 5 is a base region of an NPN) transistor and an emitter region of a PNP) transistor, 61 is an emitter region of an NPN transistor,
62 is a collector contact region of an NPN transistor and a base contact region of a PNP transistor, 7 is an oxide film, 8 is an aluminum wiring, and 9 is a phosphorus diffusion region into the epitaxial layer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type provided thereon, and a buried layer of a second conductivity type provided at the interface between the semiconductor substrate and the second conductivity type layer. and a first conductivity type isolation region penetrating from the surface of the second conductivity type layer to the semiconductor substrate, wherein the junction isolation type semiconductor integrated circuit comprises: a first conductivity type isolation region penetrating from the surface of the second conductivity type layer to the semiconductor substrate; The breakdown voltage that the island region of the second conductivity type layer has with respect to the semiconductor substrate and the isolation region is greater than at least one of the breakdown voltages that the semiconductor element formed in the island region has with respect to the semiconductor substrate potential. A semiconductor device characterized by being small. (2) The breakdown voltage that the junction-separated island region has with respect to the semiconductor substrate and the isolation region is the breakdown voltage of the junction formed between the buried layer and the semiconductor substrate, or
2. The semiconductor device according to claim 1, wherein the voltage is determined by a breakdown voltage of a junction formed by the isolation region and the semiconductor layer.