CN107424980B - 半导体封装件及半导体封装件的制造方法 - Google Patents

半导体封装件及半导体封装件的制造方法 Download PDF

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CN107424980B
CN107424980B CN201710227962.4A CN201710227962A CN107424980B CN 107424980 B CN107424980 B CN 107424980B CN 201710227962 A CN201710227962 A CN 201710227962A CN 107424980 B CN107424980 B CN 107424980B
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semiconductor device
semiconductor package
recess
opening
adhesive layer
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CN107424980A (zh
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竹原靖之
北野一彦
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Rely On Technology Japan Co
Amkor Technology Japan Inc
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Rely On Technology Japan Co
J Devices Corp
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    • HELECTRICITY
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
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    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
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    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/044Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
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    • H10W70/08Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
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CN201710227962.4A 2016-04-28 2017-04-10 半导体封装件及半导体封装件的制造方法 Active CN107424980B (zh)

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JP2016090189A JP6678506B2 (ja) 2016-04-28 2016-04-28 半導体パッケージ及び半導体パッケージの製造方法

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JP6691835B2 (ja) * 2016-06-17 2020-05-13 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージの製造方法
KR102138012B1 (ko) * 2018-08-28 2020-07-27 삼성전자주식회사 팬-아웃 반도체 패키지
CN111415908B (zh) 2019-01-07 2022-02-22 台达电子企业管理(上海)有限公司 电源模块、芯片嵌入式封装模块及制备方法
WO2021111517A1 (ja) * 2019-12-03 2021-06-10 太陽誘電株式会社 部品モジュールおよびその製造方法
US12266581B2 (en) * 2020-10-30 2025-04-01 Intel Corporation Electronic substrates having heterogeneous dielectric layers
US20220238473A1 (en) * 2021-01-25 2022-07-28 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device

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