CN107463473A - Chip software and hardware simulated environment based on UVM and FPGA - Google Patents

Abstract

The invention discloses a chip software and hardware simulation environment based on UVM and FPGA. The simulation environment includes FPGA verification platform, UVM verification platform and IP standard model. The IP standard model is connected to the FPGA verification platform, drives the FPGA for simulation verification, and sends the FPGA verification results to the UVM verification platform as the on-site environment configuration. The UVM verification platform is connected to the IP standard model, and the algorithm in the IP standard model is called to perform UVM simulation verification on the FPGA verification results. The invention connects the FPGA verification platform and the UVM verification platform through the IP standard model, and makes a software and hardware simulation verification environment capable of performing FPGA verification and UVM verification at the same time. FPGA verification focuses on the chip application layer, and completes the verification of chip codes for a large number of random excitation scenarios; UVM verification focuses on the bottom layer of the chip, and further verifies the results of FPGA verification by directly calling the algorithm in the IP standard model; the two verifications cooperate with each other, The cycle of chip verification is accelerated, and the quality of chip verification is improved.

Description

Chip software and hardware simulation environment based on UVM and FPGA

technical field

The invention relates to the field of chip simulation verification, in particular to a chip software and hardware simulation environment based on UVM and FPGA.

Background technique

In recent years, with the emergence of large-scale SOC and multi-core designs, the design of application-specific integrated chips (ASICs) has become more and more complex, and the functional complexity of chips has increased greatly, making the verification requirements of chips more and more high. How to complete the chip function verification in a short time and ensure the correct logic function puts forward higher requirements for the completeness, automation and reusability of the verification environment.

FPGA verification uses hardware description language to write test cases for the design under test. After simple simulation, the netlist is synthesized and downloaded to the target board for debugging. By observing the output waveform, it is judged whether the designed function is correct. Traditional FPGA verification uses directional testing to construct test cases for all functional points one by one. The workload is heavy, there will always be human omissions, and it is difficult to achieve full coverage. It is more suitable for large-scale, low-complexity chip verification. Although in response to the above problems, the emergence of FPGA random verification can allow chip codes to traverse more scenarios. However, FPGA random verification is mainly for the application layer verification, which cannot capture the underlying content of the chip, and cannot obtain some information inside the chip, such as code coverage, scene combination, performance statistics, etc.), and cannot analyze the problems existing in the chip. position.

Compared with FPGA verification, UVM verification has attributes such as object-oriented programming, constrained random excitation, power coverage check, and assertion, which makes it easier to locate problems. The UVM-based verification environment and verification methodology can create solid, reusable, automated, easy-to-maintain, and interoperable test process components, which have been widely recognized and adopted by the industry. However, due to the limited simulation speed, UVM verification cannot traverse too many scenarios, and is suitable for small and complex chip verification.

Contents of the invention

The purpose of the present invention is to provide a chip software and hardware simulation environment based on UVM and FPGA, to speed up the cycle of chip verification and improve the efficiency and quality of chip verification.

In order to realize the purpose of the present invention, the present invention has taken following technical scheme:

A kind of chip hardware and software simulation environment based on UVM and FPGA, comprising FPGA verification platform, UVM verification platform; It is characterized in that: described simulation environment also comprises IP standard model; Described IP standard model is connected with FPGA verification platform, drives FPGA to carry out Simulation verification, and the result of FPGA verification is sent to the UVM verification platform as the field environment configuration; the UVM verification platform is connected to the IP standard model, and the algorithm in the IP standard model is called to perform UVM simulation verification on the FPGA verification result.

Further, the IP standard model includes a control module, a printing module, an algorithm model, an excitation generator, and a first bus driver; Device, UVM verification platform unidirectional connection; Described printing module is connected with algorithm model; Described excitation generator is connected with algorithm model, first bus driver respectively; Described first bus driver is bidirectionally connected with FPGA verification platform;

The control module controls the excitation generator to generate the excitation signal, and the control algorithm model controls the first bus driver to send the excitation signal to the FPGA verification platform according to the generation algorithm of the chip to be tested, and controls the printing module to set the wrong printing point in the algorithm model, that is, print breakpoint; the printing module realizes fast positioning of the problem by setting a printing breakpoint in the algorithm model; the excitation generator directly sends the excitation signal to the algorithm model for simulation, and sends the simulation result to the control module; The excitation generator sends the excitation signal to the FPGA verification platform for simulation through the first bus driver, and sends the simulation result to the control module through the first bus driver;

The control module compares the simulation result output by the FPGA verification platform with the simulation result output by the algorithm model, and sends the comparison result, namely the FPGA verification result, to the UVM verification platform as a field environment configuration.

Further, the FPGA verification platform includes an FPGA chip and a second bus driver; the second bus driver is bidirectionally connected with the first bus driver and the FPGA chip respectively; the second bus driver receives the stimulus generator through the first bus driver output excitation signal, and send the excitation signal to the FPGA chip; the FPGA chip performs simulation according to the input excitation signal, and sends the simulation result to the first bus driver through the second drive bus, and then sends it to the control module.

Further, the FPGA verification platform also includes hardware peripherals; the hardware peripherals are bidirectionally connected to the FPGA chip, receive the driver of the FPGA, and feed back the results to the FPGA chip.

Further, the UVM verification platform includes a test case module, a test case configuration module, a data configuration module, a reference model, a scoreboard, a DUT (design under testbench, design under test) module (hereinafter the same) and a first monitor; Described test case module is connected with control module, test case configuration module; Described test case configuration module is connected with reference model, DUT module respectively; Described data configuration module is connected with reference model, DUT module respectively; Described reference model and algorithm model , scoreboard connection; the DUT module is sequentially connected with the first monitor and the scoreboard;

Described test case module receives the result of the FPGA verification of control module output and produces random test case and sends to test case configuration module; Described test case configuration module stores the random test case of test case module output and configures random test case to reference respectively A model and a DUT module; the data configuration module generates random data and configures these random data to the reference model and the DUT module respectively;

The reference model directly calls the algorithm in the algorithm model to simulate the random data under the random test case, and sends the simulation result to the scoreboard; the DUT module simulates the random data under the random test case, and simulates the random data under the random test case. The result is sent to the first monitor; the simulation result of the DUT module output is sent to the scoreboard by the first monitor; the simulation result of the DUT module output collected by the first monitor and the output of the reference model The simulation results are compared, and the comparison results are printed as the results of the UVM verification.

Further, the data configuration module includes a random data generator, a second driver and a third monitor; the random data generator is sequentially connected to the second driver and the DUT module; the random data generator generates random data, through The second driver sends random data to the DUT module and drives the DUT module to simulate; the random data generator is connected with the second driver, the third monitor, and the reference model in sequence; the third monitor receives random data through the second driver The random data output by the data generator, and driven by the second driver, send the random data to the reference model for simulation.

Further, the test case module includes a random stimulus and a random sequence generator; the random stimulus is connected with the control module and the random sequence generator, receives the result of the FPGA verification of the control module output and generates a random stimulus scenario and sends it to the random sequence generator device; the random sequence generator generates a random test case according to a random stimulus scenario and sends it to the test case configuration module.

Further, the test case configuration module includes a random sequence scheduler, a first driver, and a second monitor; the random sequence scheduler is connected with the random sequence generator, receives and stores the random test case output by the random sequence generator; The random sequence scheduler is connected with the first driver and the DUT module in sequence, and the random test case is sent to the DUT module by the first driver and drives the DUT module to simulate; the random sequence scheduler is connected with the first driver and the second monitor and the reference model are sequentially connected; the second monitor receives the random test cases output by the random sequence scheduler through the first driver, and sends the random test cases to the reference model for simulation under the drive of the first driver.

Further, the test case configuration module also includes a coverage statistics module; the coverage statistics module is connected with the first driver, receives the random test case output by the random sequence scheduler through the first driver, and the coverage rate of the random test case Make statistics.

Further, the DUT module includes a DUT and a virtual interface; the virtual interface is connected to the first driver and the DUT, receives the random test case output by the first driver and sends it to the DUT; the virtual interface is connected to the second driver and the DUT , receive the random data output by the second driver and send it to the DUT; the DUT is sequentially connected to the virtual interface and the first monitor, simulates the random data under the random test case and sends the simulation result to the first monitor through the virtual interface , and then sent to the scoreboard.

Further, the UVM verification platform also includes a top-level module; the top-level module includes a simulation script, a console, an assertion, and a memory; the console is connected to the simulation script and the DUT in sequence, and the simulation script code is loaded, and the packaged various The configuration parameters are output to the entire UVM verification platform; the console is connected to the memory, and receives the command of the simulation script to complete the initialization of the memory; the memory is bidirectionally connected to the DUT, and performs data interaction with the DUT; the assertion is connected to the console and the virtual interface Connect, receive commands from the simulation script through the console, and monitor the virtual interface in real time.

Further, the top-level module also includes a performance testing module and a Debug testing module; the console is connected with the performance testing module and the Debug testing module, and performs performance testing and Debug testing to the entire UVM verification platform; the performance testing module is used to judge whether the performance of the system meets expectations; the Debug test module, that is, the fault elimination test module, is used to detect whether the elimination of the system fault is completed.

Further, the UVM verification platform also includes a custom library file; the custom library file is respectively connected with the reference model, the scoreboard and the test case configuration module, and sends all global variables, events, and print controls of the package to the reference Model, scoreboard and test case configuration modules.

Beneficial effects of the present invention:

It can be seen from the above technical solutions that the present invention connects the FPGA verification platform and the UVM verification platform through the IP standard model, and makes a software and hardware simulation verification environment that can perform FPGA verification and UVM verification at the same time. Among them, FPGA verification focuses on the chip application layer, and completes the verification of chip codes for a large number of random excitation scenarios; the IP standard model drives the FPGA verification platform for simulation verification, and sends the FPGA verification results to the UVM verification platform as the on-site environment configuration; UVM verification Focus on the bottom layer of the chip, and further verify the results of FPGA verification by directly calling the algorithm in the IP standard model; the two verifications cooperate with each other to speed up the cycle of chip verification and improve the quality of chip verification. At the same time, the present invention can realize rapid positioning of problems by using the printing module in the IP standard model to set wrong printing points; the present invention can realize the collection of coverage by using the coverage statistics module in the UVM verification platform.

Description of drawings

In order to illustrate the embodiments of the present invention more clearly, the following briefly introduces the drawings used in the embodiments. The drawings in the following description are only embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative work.

Fig. 1 is an overall structural block diagram of the present invention;

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings.

In order to make the object, technical solution, and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

As shown in Figure 1, a chip software and hardware simulation environment based on UVM and FPGA, including FPGA verification platform, UVM verification platform, and IP standard model. The IP standard model is connected to the FPGA verification platform, drives the FPGA for simulation verification, and sends the FPGA verification results to the UVM verification platform as the on-site environment configuration. The UVM verification platform is connected to the IP standard model, and calls the algorithm in the IP standard model for simulation verification. Since the algorithm model has been separated from FPGA verification and UVM verification, it is only necessary to modify the algorithm in the algorithm model to complete the simulation verification of different DUTs (design undertestbench, design under test) (the same below). If an error occurs in the FPGA verification, the UVM verification platform can use the error scene list in the on-site environment configuration to simulate and locate the problem, and then perform batch regression to ensure that the problem is solved.

As shown in Figure 1, the IP standard model includes a control module, a printing module, an algorithm model, an excitation generator, and a first bus driver. The control module is bidirectionally connected with the algorithm model and the first bus driver, and is unidirectionally connected with the printing module, the excitation generator and the UVM verification platform. The printing module is connected with the algorithm model, and the excitation generator is respectively connected with the algorithm model and the first bus driver. The first bus driver is bidirectionally connected to the FPGA verification platform.

The control module controls the stimulus generator to generate the stimulus signal, the control algorithm model controls the first bus driver to send the stimulus signal to the FPGA verification platform according to the generation algorithm of the chip to be tested, and controls the printing module to set the wrong printing point in the algorithm model, that is, the printing breakpoint . The IP standard model sets printing breakpoints in the algorithm model through the printing module to quickly locate problems. The excitation generator sends the excitation signal directly to the algorithm model for simulation, and sends the simulation result to the control module. At the same time, the excitation generator sends the excitation signal to the FPGA verification platform for simulation through the first bus driver, and sends the simulation result to the control module through the first bus driver. The control module compares the simulation results output by the FPGA verification platform with the simulation results output by the algorithm model, and sends the comparison result, that is, the FPGA verification result, to the UVM verification platform as the on-site environment configuration.

In this embodiment, the algorithm model first constructs a standard model through a C model or a MATLAB model, and then under the action of the control module, rewrites the standard model according to the actual chip implementation to obtain an accurate algorithm.

In this embodiment, the control module configures the FPGA verification result to the UVM verification platform by printing.

As shown in Figure 1, the FPGA verification platform includes an FPGA chip, a second bus driver and hardware peripherals. The second bus driver is bidirectionally connected with the first bus driver and the FPGA chip respectively, receives the excitation signal output by the excitation generator through the first bus driver, and sends the excitation signal to the FPGA chip; the FPGA chip performs simulation according to the input excitation signal, and The simulation result is sent to the first bus driver through the second driver bus, and then sent to the control module. The hardware external device is bidirectionally connected with the FPGA chip, receives the driver of the FPGA, and feeds back the result to the FPGA chip.

As shown in Figure 1, the UVM verification platform includes a test case module, a test case configuration module, a data configuration module, a reference model, a scoreboard, a DUT module, a first monitor, a top-level module, and a custom library file. The test case module is connected with the control module and the test case configuration module. The test case configuration module is connected with the reference model and the DUT module respectively. The data configuration module is respectively connected with the reference model and the DUT module. The reference model is connected with the algorithm model and scoreboard. The DUT module is sequentially connected with the first monitor and the scoreboard. The top module is connected with the DUT module. The custom library files are connected with the reference model, scoreboard and test case configuration modules respectively.

The test case module receives the FPGA verification results output by the control module and generates random test cases and sends them to the test case configuration module. The test case configuration module stores the random test cases output by the test case module and configures the random test cases to the reference model and the DUT module respectively. The data configuration module generates random data and configures these random data to the reference model and the DUT module respectively.

The reference model directly calls the algorithm in the algorithm model to simulate the random data under the random test case, and sends the simulation result to the scoreboard. The DUT module simulates random data under random test cases, and sends the simulation results to the first monitor. The first monitor sends the simulation results output by the DUT module to the scoreboard. The scoreboard compares the simulation results output by the DUT module collected by the first monitor with the simulation results output by the reference model, and prints out the comparison results as UVM verification results. According to the printed results, the scoreboard can first confirm whether the simulation is correct, and then locate the problem according to the wrong printing points in the reference model.

The custom library file encapsulates all global variables, events, and print controls sent to the reference model, scoreboard, and test case configuration modules. At this time, the UVM verification platform can directly call the code in the custom library file, reducing unnecessary code volume, and directly modifying and expanding the custom library file can complete the underlying modification of the entire UVM verification platform.

As shown in Figure 1, the test case module includes a random stimulus and a random sequence generator. The random excitation is connected with the control module and the random sequence generator, receives the FPGA verification result output by the control module and generates a random excitation scene and sends it to the random sequence generator. The random sequence generator generates random test cases according to random stimulus scenarios and sends them to the test case configuration module.

As shown in Figure 1, the test case configuration module includes a random sequence scheduler, a first driver, a second monitor, and a coverage statistics module. The random sequence scheduler is connected with the random sequence generator, receives and stores the random test cases output by the random sequence generator. The random sequence scheduler is sequentially connected with the first driver and the DUT module, sends random test cases to the DUT module through the first driver, and drives the DUT module for simulation. The random sequence scheduler is sequentially connected with the first driver, the second monitor and the reference model. The second monitor receives the random test cases output by the random sequence scheduler through the first driver, and sends the random test cases to the reference model for simulation driven by the first driver. The coverage statistics module is connected with the first driver, receives the random test cases output by the random sequence scheduler through the first driver, and makes statistics on the coverage ratio of the test cases.

As shown in FIG. 1 , the data configuration module includes a random data generator, a second driver and a third monitor. The random data generator is sequentially connected with the second driver and the DUT module. The random data generator generates random data, sends the random data to the DUT module through the second driver and drives the DUT module for simulation. The random data generator is sequentially connected with the second driver, the third monitor and the reference model. The third monitor receives the random data output by the random data generator through the second driver, and sends the random data to the reference model for simulation under the drive of the second driver.

As shown in Figure 1, the DUT module includes DUT and virtual interface. The virtual interface is connected with the first driver and the DUT, receives random test cases output by the first driver and sends them to the DUT. The virtual interface is connected with the second driver and the DUT, receives random data output by the second driver and sends it to the DUT. The DUT is sequentially connected to the virtual interface and the first monitor, performs simulation on random data under random test cases, and sends the simulation results to the first monitor through the virtual interface, and then to the scoreboard.

As shown in Figure 1, the top-level modules include simulation scripts, consoles, assertions, memory, performance test modules, and Debug test modules. The console is connected to the simulation script and DUT in turn, loads the simulation script code, and outputs the packaged various configuration parameters to the entire UVM verification platform. The console is connected with the storage, and receives the command of the simulation script to complete the initialization of the storage. The memory is bidirectionally connected to the DUT and performs data interaction with the DUT. The assertion is connected with the console and the virtual interface, receives the command of the simulation script through the console, monitors the virtual interface in real time and can quickly locate the interface problem. The console is connected with the performance test module and the Debug test module to perform performance test and Debug test on the entire UVM verification platform. The performance test module is used to judge whether the performance of the system meets expectations. The Debug test module, that is, the fault elimination test module, is used to detect whether the elimination of system faults is completed.

The above descriptions are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention should also be regarded as the protection scope of the present invention.

Claims (13)

1. a kind of chip software and hardware simulated environment based on UVM and FPGA, including FPGA verification platforms, UVM verification platforms；It is special Sign is：The simulated environment also includes IP master patterns；The IP master patterns are connected with FPGA verification platforms, drive FPGA Simulating, verifying is carried out, and UVM verification platforms are sent to using the result of FPGA checkings as site environment configuration；The UVM checkings Platform is connected with IP master patterns, and the result for calling the algorithm in IP master patterns to verify FPGA carries out UVM simulating, verifyings.

A kind of 2. chip software and hardware simulated environment based on UVM and FPGA according to claim 1, it is characterised in that：

The IP master patterns include control module, print module, algorithm model, excitation generator, the first bus driver；It is described Control module is bi-directionally connected with algorithm model, the first bus driver respectively, and flat with print module, excitation generator, UVM checkings Platform unidirectionally connects；The print module is connected with algorithm model；The excitation generator drives with algorithm model, the first bus respectively Dynamic connection；First bus driver is bi-directionally connected with FPGA verification platforms；

Control module control excitation generator produces pumping signal, control algolithm model according to chip generating algorithm to be measured, Control the first bus driver that pumping signal is sent into FPGA verification platforms, control print module sets mistake in algorithm model Print point, that is, print breakpoint；The print module by setting printing breakpoint in algorithm model, determine by the quick of problem of implementation Position；Pumping signal is transmitted directly to algorithm model and emulated by the excitation generator, and simulation result is sent into control Module；Pumping signal is sent to FPGA verification platforms by the first bus driver and emulated by the excitation generator, and will Simulation result is sent to control module by the first bus driver；

The control module by the simulation result that FPGA verification platforms export compared with the simulation result that algorithm model exports, And the result that comparative result is FPGA checkings is sent to UVM verification platforms as site environment configuration.

A kind of 3. chip software and hardware simulated environment based on UVM and FPGA according to claim 2, it is characterised in that：Institute Stating FPGA verification platforms includes fpga chip and the second bus driver；Second bus driver is driven with the first bus respectively Dynamic, fpga chip is bi-directionally connected；Second bus driver receives the excitation of excitation generator output by the first bus driver Signal, and pumping signal is sent to fpga chip；The fpga chip is emulated according to the pumping signal of input, and will be imitative True result is sent to the first bus driver by the second driving bus, and then is sent to control module.

A kind of 4. chip software and hardware simulated environment based on UVM and FPGA according to claim 3, it is characterised in that：Institute Stating FPGA verification platforms also includes hardware external equipment；The hardware external equipment is bi-directionally connected with fpga chip, receives FPGA Driving, and result is fed back into fpga chip.

A kind of 5. chip software and hardware simulated environment based on UVM and FPGA according to claim 2, it is characterised in that：

The UVM verification platforms include test case module, test case configuration module, data configuration module, reference model, meter Scoreboard, DUT module and the first monitor；The test case module is connected with control module, test case configuration module；Institute Test case configuration module is stated to be connected with reference model, DUT module respectively；The data configuration module respectively with reference model, DUT module connects；The reference model is connected with algorithm model, scoring board；The DUT module and the first monitor, scoring board It is sequentially connected；

The result of the FPGA checkings of test case module receive and control module output simultaneously produces random test use-case and is sent to Test case configuration module；The random test use-case of test case configuration module storage test case module output simultaneously will be with Machine test case is respectively configured to reference model and DUT module；The data configuration module produce random data and by these with Machine data are respectively configured to reference model and DUT module；

The algorithm that the reference model is directly invoked in algorithm model emulates to the random data under random test use-case, and Simulation result is sent to scoring board；The random data that the DUT module is directed under random test use-case is emulated, and will be imitative True result is sent to the first monitor；The simulation result that DUT module exports is sent to scoring board by first monitor；It is described Scoring board is compared the simulation result that the simulation result that the DUT module that the first monitor gathers exports exports with reference model Compared with, and printed comparative result as the UVM results verified.

A kind of 6. chip software and hardware simulated environment based on UVM and FPGA according to claim 5, it is characterised in that：Institute Stating data configuration module includes random data generator, the second driver and the 3rd monitor；The random data generator It is sequentially connected with the second driver, DUT module；The random data generator produces random data, will by the second driver Random data is sent to DUT module and drives DUT module to be emulated；The random data generator and the second driver, Three monitors, reference model are sequentially connected；3rd monitor receives random data generator by the second driver and exported Random data, and random data is sent to reference model under the driving of the second driver and emulated.

A kind of 7. chip software and hardware simulated environment based on UVM and FPGA according to claim 6, it is characterised in that：Institute Stating test case module includes arbitrary excitation and random sequence generator；The arbitrary excitation produces with control module, random sequence Raw device connection, the result of the FPGA checkings of receive and control module output simultaneously produce arbitrary excitation scene and are sent to random sequence generation Device；The random sequence generator produces random test use-case according to arbitrary excitation scene and is sent to test case configuration mould Block.

A kind of 8. chip software and hardware simulated environment based on UVM and FPGA according to claim 7, it is characterised in that：Institute Stating test case configuration module includes random sequence scheduler, the first driver, the second monitor；The random sequence scheduler It is connected with random sequence generator, receives and store the random test use-case of random sequence generator output；The random sequence Scheduler is sequentially connected with the first driver, DUT module, and random test use-case is sent into DUT module by the first driver And DUT module is driven to be emulated；The random sequence scheduler and the first driver, the second monitor and reference model according to Secondary connection；The random test use-case that second monitor is exported by the first driver reception random sequence scheduler, and Random test use-case is sent into reference model under the driving of first driver to be emulated.

A kind of 9. chip software and hardware simulated environment based on UVM and FPGA according to claim 8, it is characterised in that：Institute Stating test case configuration module also includes coverage rate statistical module；The coverage rate statistical module is connected with the first driver, is led to The random test use-case that the first driver receives the output of random sequence scheduler is crossed, the coverage rate of random test use-case is united Meter.

10. a kind of chip software and hardware simulated environment based on UVM and FPGA according to claim 7 or 8, its feature exist In：The DUT module includes DUT and virtual interface；The virtual interface is connected with the first driver, DUT, receives the first driving The random test use-case of device output is simultaneously sent to DUT；The virtual interface is connected with the second driver, DUT, receives the second driving The random data of device output is simultaneously sent to DUT；The DUT is sequentially connected with virtual interface, the first monitor, for random test Random data under use-case is emulated and simulation result is sent into the first monitor by virtual interface, and then is sent to meter Scoreboard.

A kind of 11. chip software and hardware simulated environment based on UVM and FPGA according to claim 10, it is characterised in that： The UVM verification platforms also include top-level module；The top-level module includes emulation script, console, asserted, memory；Institute State console to be sequentially connected with emulation script, DUT, loading emulation scripted code, the various configuration parameters of encapsulation are output to whole Individual UVM verification platforms；The console is connected with memory, and the initialization of memory is completed in the order for receiving emulation script；Institute State memory to be bi-directionally connected with DUT, data interaction is carried out with DUT；Described assert is connected with console and virtual interface, passes through control Platform processed receives the order of emulation script, monitors virtual interface in real time.

A kind of 12. chip software and hardware simulated environment based on UVM and FPGA according to claim 11, it is characterised in that： The top-level module also includes performance test module, Debug test modules；The console is surveyed with performance test module, Debug Die trial block is connected, and performance test is carried out to whole UVM verification platforms and Debug is tested；The performance test module is for sentencing Whether the performance of disconnected system meets expection；The Debug test modules, that is, fault test module is eliminated, is for detecting system Whether the elimination of failure is completed.

A kind of 13. chip software and hardware simulated environment based on UVM and FPGA according to claim 10, it is characterised in that： The UVM verification platforms also include self-defined library file；The self-defined library file respectively with reference model, scoring board and survey Example configuration module connection on probation, by all global variables, event, the print control of encapsulation be sent to reference model, scoring board and Test case configuration module.