CN110415744A - Nonvolatile storage based on ferroelectric transistor - Google Patents

Abstract

Nonvolatile storage the invention discloses one kind based on ferroelectric transistor, element circuit and array circuit including the nonvolatile storage designed based on ferroelectric transistor, its element circuit structure includes two transistors or three transistors, being combined into the array layout modes of several row several columns by way of electrical connection between multiple units.The present invention utilizes ferroelectric transistor drain-source current-grid voltage hysteretic characteristic, completes the high efficiency read-write operation to memory.

Description

Non-volatile memory based on ferroelectric transistor

technical field

The invention relates to the technical field of low power consumption nonvolatile memory structure design, in particular to a nonvolatile memory based on ferroelectric transistors.

Background technique

In today's era, with the increasing amount of information, people put forward higher requirements on the non-volatile performance of memory in order to prevent the loss of stored information. For many memories, such as DRAM (dynamic random access memory, dynamic random access memory), when there is no external power supply for a long time, the information stored in the memory will be lost due to the reduction of the energy of the circuit device. Random access NVM (nonvolatile memory, nonvolatile memory) can effectively solve the above problems. The current non-volatile memories include PCRAM, ReRAM, FeRAM, STT-MRAM, etc., but these memories still have relatively low data access energy consumption and delay, process compatibility, device durability, and circuit design complexity. Many deficiencies.

At present, the FeFET (ferroelectric field effect transistor, ferroelectric transistor) based on new materials and manufacturing processes makes the designed memory have good process compatibility and low power consumption characteristics, and has good durability and moderate working voltage, such as , The recent test results published in the industry show that the bias voltage of FeFET read and write operations can be reduced to within 1.5V. These characteristics indicate that ferroelectric transistors have great application potential in the fields of array design, distributed data storage, and neuromorphic computing. Further, in the Nonvolatile memory design based on ferroelectric FETs, a nonvolatile memory array with two transistors per circuit unit is designed to achieve high energy efficiency; Potential for high energy efficiency of electrical transistors.

Contents of the invention

The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

For this reason, an object of the present invention is to propose a class of circuit units designed based on ferroelectric transistors, which fully utilizes the drain-source current-gate voltage hysteresis characteristics of ferroelectric transistors, and designs novel circuit structures and operations In this way, the purpose of lower power consumption non-volatile memory is achieved.

Another object of the present invention is to propose a corresponding array circuit based on the above-mentioned circuit unit designed with ferroelectric transistors.

In order to achieve the above purpose, the embodiment of the first aspect of the present invention proposes a circuit unit based on a ferroelectric transistor design, including: a first transistor, a second transistor, a bit line, a first word line and a second word line, wherein, The gate of the first transistor is connected to the first word line, the drain of the first transistor is connected to the bit line, and the source of the first transistor is connected to the drain of the second transistor , the gate of the second transistor is connected to the second word line, the source of the second transistor is grounded or biased at a preset potential, and at least one of the first transistor and the second transistor is an iron electric transistor.

In order to achieve the above purpose, the embodiment of the second aspect of the present invention proposes an array circuit based on ferroelectric transistor design, including: at least one circuit unit as described in the above embodiment, and each unit of the array circuit is electrically connected A multi-row multi-column layout is combined in a multi-row multi-column manner, wherein the first word lines of the circuit units in the same row are connected, the second word lines of the circuit units in the same row are connected, and the bit lines of the circuit units in the same column are connected.

According to the circuit unit and array circuit designed based on ferroelectric transistors in the embodiment of the present invention, for each circuit unit has a nonvolatile memory with two transistors, the energy delay product of the write operation can be lower, thereby fully utilizing the ferroelectric The transistor's drain-source current-gate voltage hysteresis characteristic, a new circuit structure and operation mode are designed, and the purpose of lower power consumption non-volatile memory is achieved.

In addition, the array circuit designed based on ferroelectric transistors according to the above-mentioned embodiments of the present invention may also have the following additional technical features:

Further, in an embodiment of the present invention, wherein, when the data stored in the circuit unit is read, the voltage of the second word line of the circuit unit makes the second transistor of the circuit unit turn on, so as to distinguish the stored value of the circuit unit according to the resistance value between the drain and source of the first transistor of the circuit unit or the influence of the resistance value on the voltage or current change on the bit line of the circuit unit. data.

Further, in one embodiment of the present invention, wherein, when the data stored in the circuit unit is written, the voltages of the bit line and the first word line are controlled so that the circuit unit The polarization characteristic of the first transistor is consistent with the data to be stored.

Further, in an embodiment of the present invention, wherein, when the data stored in the circuit unit is written, the bit line voltage is biased at a high level or a low level, and the first word The voltage of the line stays at the low voltage and the high voltage for a period of time and then recovers to the original voltage, and the voltage of the second word line causes the second transistor of the circuit unit to be turned off.

In order to achieve the above purpose, the embodiment of the third aspect of the present invention proposes a circuit unit based on ferroelectric transistor design, including: a first transistor, a second transistor, a third transistor, a first bit line, a second bit line, a second A word line, a second word line and a third word line, wherein the gate of the first transistor is connected to the first word line, the drain of the first transistor is connected to the gate of the second transistor connected, the source of the first transistor is connected to the first bit line, the drain of the second transistor is connected to the source of the third transistor, and the source of the second transistor is connected to the second word line , the gate of the third transistor is connected to the third word line, and the drain of the third transistor is connected to the second bit line, wherein the first transistor, the second transistor and the third transistor At least one of the transistors in is a ferroelectric transistor.

In addition, the circuit unit designed based on ferroelectric transistors according to the above embodiments of the present invention may also have the following additional technical features:

Further, in an embodiment of the present invention, the first bit line and the second bit line are combined into one bit line in a form of short circuit.

In order to achieve the above purpose, the embodiment of the fourth aspect of the present invention proposes an array circuit based on ferroelectric transistor design, including: at least one circuit unit as described in the above embodiment, and each unit of the array circuit is electrically connected The layout of multiple rows and multiple columns is combined in a multi-row and multi-column manner, wherein the first word lines of the circuit cells in the same row are connected, the second word lines of the circuit cells in the same row are connected, and the third word lines of the circuit cells in the same row are also connected. , the first bit lines of the circuit units in the same column are connected, and the second bit lines of the circuit units in the same column are also connected.

The circuit unit and array circuit designed based on ferroelectric transistors in the embodiment of the present invention effectively reduce the energy delay product of the write operation for a nonvolatile memory with three transistors for each circuit unit. The write operation will not affect the normal state of other circuit units. At the same time, the circuit unit only needs a single voltage to maintain the operation, thus making full use of the drain-source current-gate voltage hysteresis characteristics of the ferroelectric transistor, and designing a new circuit structure and operation mode, the purpose of lower power consumption non-volatile memory is achieved.

In addition, the array circuit designed based on ferroelectric transistors according to the above-mentioned embodiments of the present invention may also have the following additional technical features:

Further, in one embodiment of the present invention, wherein, when the data stored in the circuit unit is read, the voltage of the third word line makes the third transistor turn on, so as to The value of the resistance between the drain and source of the second transistor or its influence is used to distinguish the data stored by the circuit unit.

Further, in one embodiment of the present invention, wherein, when the data stored in the circuit unit is written, the voltages of the second word line and the first bit line are controlled so that the The polarization characteristic of the second transistor of the circuit unit is consistent with the data to be stored.

Further, in an embodiment of the present invention, wherein, when the data stored in the circuit unit is written, the voltage of the first bit line is biased at a high level or a low level, so The voltage of the first word line turns on the first transistor, and the voltage of the third word line turns off the third transistor.

Further, in one embodiment of the present invention, wherein when the data stored in the circuit unit is written, the voltage of the second word line stays at a low voltage and a high voltage for a period of time respectively Then return to the original voltage.

Further, in an embodiment of the present invention, the first bit line and the second bit line are combined into one bit line in a form of short circuit.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

1 is a schematic diagram of circuit symbols of a ferroelectric transistor according to an embodiment of the present invention;

2 is a schematic diagram of a structure of a ferroelectric transistor according to an embodiment of the present invention;

3 is a schematic diagram of a typical situation of a ferroelectric transistor drain-source conductance-gate-source voltage hysteresis characteristic curve according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a structure of a circuit unit including two transistors and a read and write operation according to an embodiment of the present invention;

5 is a schematic structural diagram of an array circuit designed based on ferroelectric transistors according to an embodiment of the present invention;

6 is a schematic diagram of an array structure of a first memory according to an embodiment of the present invention;

7 is a schematic diagram of transient waveforms under different operations of the first memory according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a structure of a circuit unit including three transistors and a read and write operation according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of an array structure of a second memory according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of an array structure of a third memory according to an embodiment of the present invention;

Figure 11 shows three types of non-volatile memory write delay-average write energy, read delay-average read energy, and write delay-kinetic energy coefficient based on ferroelectric transistor design according to an embodiment of the present invention Schematic diagram of the comparison of performance;

FIG. 12 is a schematic diagram of comparison of performance indicators among different nonvolatile memories based on ferroelectric transistor designs according to an embodiment of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

The embodiments of the present invention are mainly a type of nonvolatile memory based on ferroelectric transistors, including unit circuits and array circuits of nonvolatile memories designed based on ferroelectric transistors, and the unit circuit structure includes two transistors or three transistors. Each unit can be combined into a layout of several rows and several columns through electrical connection. The embodiment of the present invention utilizes the hysteresis characteristic of the drain-source current-gate voltage of the ferroelectric transistor to complete high-efficiency read and write operations on the memory.

The ferroelectric transistor-based circuit unit and memory according to the embodiments of the present invention will be described below with reference to the drawings. First, the ferroelectric transistor-based circuit unit according to the embodiments of the present invention will be described with reference to the drawings.

The circuit unit designed based on ferroelectric transistors includes: a first transistor, a second transistor, a bit line, a first word line and a second word line.

Wherein, the gate of the first transistor is connected to the first word line, the drain of the first transistor is connected to the bit line, the source of the first transistor is connected to the drain of the second transistor, and the gate of the second transistor is connected to the second The word lines are connected, the source of the second transistor is grounded or biased at a preset potential, and at least one of the first transistor and the second transistor is a ferroelectric transistor. The circuit unit of the embodiment of the present invention can make full use of the drain-source current-gate voltage hysteresis characteristic of the ferroelectric transistor, design a new circuit structure and operation mode, and achieve the purpose of a non-volatile memory with lower power consumption.

The preset potential can be understood as that the source of the second transistor is biased at a fixed potential, which can be set by those skilled in the art according to actual conditions, and is not specifically limited here.

It should be noted that the circuit symbol of the ferroelectric transistor is shown in Figure 1, a structure of the ferroelectric transistor is shown in Figure 2, and a typical situation of the drain-source conductance-gate-source voltage hysteresis characteristic curve of the ferroelectric transistor is shown in Figure 3 shows.

The circuit unit designed based on the ferroelectric transistor will be further elaborated below through a specific embodiment.

For a nonvolatile memory with two transistor structures per circuit unit, as shown in Figure 4, the gate of the ferroelectric transistor T2 is connected to the word line WLW, the drain is connected to the bit line BL, and the source is connected to the drain of the transistor T1 The gate of the transistor T1 is connected to the word line WLR, and the source is biased at a fixed potential of 0.

In the absence of external energy injection, the bit line BL and the two write word lines WLW, WLR are biased at 0 potential, at this time the gate-source voltage V _GS of the ferroelectric transistor = 0, and the ferroelectric transistor operates at drain-source current - Inside the hysteresis interval of the gate voltage hysteresis curve. When there is energy injection, when the data of the storage unit is not read and written, the WLW potential is biased at VDD/2, and the WLR potential is biased at 0. In the above cases, the polarization of the ferroelectric transistor will not change, that is, the stored information will not change. will change.

When the memory cell is read, the potential of WLR is biased at VDD, T1 is in a conduction state, and the potential of WLW is biased at VDD/2. Use the method of measuring the voltage change of the bit line to judge the read information, as shown in (a) (b) of Figure 4: BL potential is biased at VDD, if the ferroelectric transistor is in a positive polarization state, the voltage on BL will drop from VDD to 0 ; If it is a negative polarization state, the voltage on BL is always kept at VDD. The above changes can be detected by measuring the voltage on BL with a voltage amplifier. In addition, it is also possible to measure the change of the current on the BL to judge the read information. For a large-scale array, the delay of judging by the change of the current is lower than that of judging by the change of the voltage. Discharge.

When writing to the memory cell, as shown in (c)(d) of Figure 4, the WLR is biased at 0 potential, and the transistor T1 is in an off state. If a '1' is written to the memory cell, the BL potential is biased The potential on VDD and WLW is biased twice: first biased to VDD, and then biased to 0. When biased to VDD for the first time, the original stored information of T2 does not change. When biased to 0 for the second time, T2 becomes negatively polarized, that is, writing '1'; if writing '0' to the memory cell, the BL potential is biased at 0, WLW performs the same operation as above, and T2 becomes positive when it is biased to VDD for the first time When it is written into '0' and biased to 0 for the second time, the previously written '0' does not change. In addition, the write operation can also be realized by biasing the upper potential of WLW to 0 first, and then biasing it to VDD.

Considering the influence of the initial potential of each pole of the circuit unit transistor on the correctness of read and write operations, the memory designed by this principle can ensure the correctness of read and write operations, because the potential on WLW will be biased at VDD/2 before the read and write operations , so that the polarization state of T2 does not change.

Next, an array circuit designed based on ferroelectric transistors proposed according to an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 5 is a schematic structural diagram of an array circuit designed based on ferroelectric transistors according to an embodiment of the present invention.

As shown in FIG. 5, the array circuit designed based on ferroelectric transistors includes: at least one circuit unit as in the above-mentioned embodiment, and each unit of the array circuit is combined into a multi-row and multi-column layout by electrical connection, wherein, The first word lines of the circuit units in the same row are connected, the second word lines of the circuit units in the same row are connected, and the bit lines of the circuit units in the same column are connected.

Furthermore, in an embodiment of the present invention, wherein, when the data stored in the circuit unit is read, the voltage of the second word line makes the second transistor turn on, so that according to the first The resistance value between the drain and source of a transistor or the change of the resistance value on the voltage or current on the bit line affects the resolution of the data stored by the circuit unit.

Further, when the data stored in the circuit unit is written, the voltage of the bit line and the first word line is controlled to make the polarization characteristics of the first transistor consistent with the data to be stored .

Further, when the data stored in the circuit unit is written, the voltage of the bit line is biased at a high level or a low level, and the voltage of the first word line is at a low voltage and a high voltage, respectively. After staying for a period of time and then recovering to the original voltage, the voltage of the second word line turns off the second transistor.

In addition, as shown in FIG. 6 , FIG. 6 is a schematic diagram of an array structure of the first memory of the present invention, and a schematic diagram of transient waveforms of the first memory under different operations is shown in FIG. 7 .

According to the circuit unit and array circuit designed based on ferroelectric transistors proposed by the embodiments of the present invention, for a nonvolatile memory with two transistors per circuit unit, the energy delay product of the write operation can be lower, thereby making full use of the The drain-source current-gate voltage hysteresis characteristic of ferroelectric transistors, a new circuit structure and operation mode are designed, and the purpose of lower power consumption non-volatile memory is achieved.

Based on the previous embodiment, the second embodiment of the present invention provides another circuit unit based on ferroelectric transistor design. This embodiment and the previous embodiment have their own emphasis on the description content. The above places can be referred to each other. The second embodiment of the present invention will be described in detail below.

The circuit unit designed based on ferroelectric transistors includes: a first transistor, a second transistor, a third transistor, a first bit line, a second bit line, a first word line, a second word line and a third word line.

Wherein, the gate of the first transistor is connected to the first word line, the drain of the first transistor is connected to the gate of the second transistor, the source of the first transistor is connected to the first bit line, and the drain of the second transistor is connected to the first bit line. The source of the third transistor is connected, the source of the second transistor is connected to the second word line, the gate of the third transistor is connected to the third word line, and the drain of the third transistor is connected to the second bit line, wherein the At least one of the first transistor, the second transistor and the third transistor is a ferroelectric transistor.

In the second specific implementation mode, each circuit unit uses three transistors and has two bit lines. As shown in FIG. 8(a), the gate of the transistor T1 is connected to the word line WLW, and its drain is connected to the iron The gate of the transistor T2 is connected, and the source is connected to the bit line BLW; the drain of the ferroelectric transistor T2 is connected to the source of the transistor T3, and its source is connected to the word line WLRW; the gate of the transistor T3 is connected to the word line WLR , the drain is connected to the bit line BLR;

In the absence of external energy injection, or when there is external energy injection but the memory cell data is not read and written, the three word lines and two bit lines are all biased at 0 potential, and the ferroelectric transistor works at the drain-source current -In the hysteresis interval of the gate voltage hysteresis curve, the stored information will not change.

When the memory cell is read, the potential of WLR is biased at VDD, the potentials of WLW, BLW, and WLRW are all biased at 0, T1 is in an off state, and T3 is in an on state. As shown in Figure 8(a), the information stored in the circuit unit is judged by the change of the voltage on the BLR: the voltage on the BLR is biased at VDD, if T2 is negatively polarized, the BLR potential is always kept at VDD; if it is positively polarized, the BLR The potential will decrease to 0. Judging the change of the current on the BLR can also judge the information stored in the circuit unit, which provides an effective way to realize the energy delay idealization of a large storage array.

When performing a write operation on the memory cell, the potential of WLW is biased at VDD, the potential of WLR is biased at GND, T1 is in an on state, and T3 is in an off state. As shown in Figure 8(c)(d), if '1' is written into the memory cell, the potential of BLW is biased at 0, and the potential of WLWR is biased twice: first biased to VDD, then biased to 0 , when it is biased to VDD for the first time, T2 becomes negatively polarized, that is, writing '1', when it is biased to 0 for the second time, the previously written '1' does not change; if it is written into the memory cell Enter '0', the BLW potential is biased at VDD, and WLWR performs the same operation as above. When it is biased to VDD for the first time, the polarization state of T2 does not change. When it is biased to 0 for the second time, T2 becomes positively polarized. That is, write '0'. In addition, the write operation can also be realized by biasing the upper potential of WLWR to 0 first, and then biasing it to VDD.

Next, the array circuit based on ferroelectric transistor design proposed according to the above-mentioned embodiments will be described.

The array circuit designed based on ferroelectric transistors includes: at least one circuit unit as in the second embodiment, and each unit of the array circuit is combined into a multi-row and multi-column layout by electrical connection, wherein the circuit units in the same row The first word lines of the circuit units in the same row are connected, the third word lines of the circuit units in the same row are also connected, the first bit lines of the circuit units in the same column are connected, and the circuit units in the same column are connected. The second bit line is also connected.

Further, in one embodiment of the present invention, wherein, when the data stored in the circuit unit is read, the voltage of the third word line makes the third transistor turn on, so as to The value of the resistance between the drain and the source of the second transistor or its influence is used to distinguish the data stored by the circuit unit.

Further, when the data stored in the circuit unit is written, the voltages of the second word line and the first bit line are controlled so that the polarization characteristics of the second transistor are consistent with the data stored in the circuit unit. The data is consistent.

Further, when the data stored in the circuit unit is written, the voltage of the first bit line is biased at high level or low level, and the voltage of the first word line makes the first transistor is turned on, the voltage of the third word line turns off the third transistor.

Further, when the data stored in the circuit unit is written, the voltage of the second word line stays at the low voltage and the high voltage for a period of time and then returns to the original voltage.

In addition, as shown in FIG. 9 , FIG. 9 is a schematic diagram of an array structure of the second type of memory.

According to the circuit unit and array circuit designed based on ferroelectric transistors proposed in the embodiment of the present invention, for each circuit unit has three transistors non-volatile memory, effectively reduces the energy delay product of the write operation, for a certain circuit The writing operation of the unit will not affect the normal state of other circuit units. At the same time, the circuit unit only needs a single voltage to maintain the operation, thus making full use of the drain-source current-gate voltage hysteresis characteristics of the ferroelectric transistor, and designing a new type of The circuit structure and operation mode achieve the purpose of the non-volatile memory with lower power consumption.

Further, the first bit line and the second bit line in the second embodiment of the present invention can be combined into one bit line in the form of a short circuit, therefore, the third embodiment of the present invention provides another ferroelectric transistor-based For the designed circuit unit, this embodiment and the above-mentioned embodiments have different emphases in the description content, and the various embodiments can refer to each other for the parts that are not fully described. The third embodiment of the present invention will be described in detail below.

The circuit unit designed based on ferroelectric transistors includes: a first transistor, a second transistor, a third transistor, a bit line, a first word line, a second word line and a third word line.

Wherein, the gate of the first transistor is connected to the first word line, the drain of the first transistor is connected to the gate of the second transistor, the source of the first transistor is connected to the bit line, and the drain of the second transistor is connected to the third The sources of the transistors are connected, the source of the second transistor is connected to the second word line, the gate of the third transistor is connected to the third word line, and the drain of the third transistor is connected to the bit line, wherein the first transistor At least one of the transistors, the second transistor and the third transistor is a ferroelectric transistor.

In the third specific implementation mode, each circuit unit uses three transistors and only one bit line, as shown in Figure 8(b), the gate of the transistor T1 is connected to the word line WLW, and the drain is connected to the ferroelectric transistor The gate of T2 is connected, and the source is connected to the bit line BL; the drain of transistor T2 is connected to the source of transistor T3, and the source is connected to the word line WLRW; the gate of transistor T3 is connected to the word line WLR, and the drain is connected to the bit line Line BL is connected;

In the absence of external energy injection, or when there is external energy injection but no read and write operations are performed on the memory cell data, the three word lines and bit lines are all biased at 0 potential, and the ferroelectric transistor works at drain-source current-gate Within the hysteresis interval of the pole voltage hysteresis curve, the stored information will not change.

When the memory cell is read, the potential of WLR is biased at VDD, the potentials of WLW and WLRW are both biased at 0, T1 is in an off state, and T3 is in an on state. The information stored in the circuit unit is judged by the change of the voltage on the BL: the voltage on the BL is biased at VDD, if T2 is negatively polarized, the BL potential is always kept at VDD; if it is positively polarized, the BL potential will be reduced to 0. Judging the change of the current on the BL can also judge the information stored in the circuit unit.

When performing a write operation on a storage unit, its working principle is the same as that of the second type of memory circuit unit. It only needs to change the operation on BLW to the operation on BL, and keep other operations unchanged. A write operation to the third type memory circuit unit. For the second and third types of memory, the initial potential of each pole of the circuit unit transistor will not affect the polarization of the ferroelectric transistor, that is, it will not affect the correctness of the circuit unit read and write operations.

Next, the array circuit based on ferroelectric transistor design proposed according to the above-mentioned embodiments will be described.

The array circuit designed based on ferroelectric transistors includes: at least one circuit unit as in the third embodiment, and each unit of the array circuit is combined into a multi-row and multi-column layout by electrical connection, wherein the circuit units in the same row The first word lines of the circuit units in the same row are connected, the second word lines of the circuit units in the same row are also connected, and the bit lines of the circuit units in the same column are connected.

Further, in an embodiment of the present invention, wherein, when the data stored in the circuit unit is read, the voltage of the third word line makes the third transistor turn on, so as to The data stored in the circuit unit is determined by the resistance value between the drain and source of the two transistors or its influence.

Further, when the data stored in the circuit unit is written, the voltages of the second word line and the bit line are controlled to make the polarization characteristic of the second transistor consistent with the data to be stored.

Further, when the data stored in the circuit unit is written, the voltage of the bit line is biased at a high level or a low level, and the voltage of the first word line makes the first transistor turn on, The voltage of the third word line turns off the third transistor.

Further, when the data stored in the circuit unit is written, the voltage of the second word line stays at the low voltage and the high voltage for a period of time and then returns to the original voltage.

In addition, as shown in FIG. 10 , FIG. 10 is a schematic diagram of an array structure of the third memory.

According to the circuit unit and array circuit designed based on ferroelectric transistors proposed in the embodiment of the present invention, for each circuit unit has three transistors non-volatile memory, effectively reduces the energy delay product of the write operation, for a certain circuit The writing operation of the unit will not affect the normal state of other circuit units. At the same time, the circuit unit only needs a single voltage to maintain the operation, thus making full use of the drain-source current-gate voltage hysteresis characteristics of the ferroelectric transistor, and designing a new type of The circuit structure and operation mode achieve the purpose of the non-volatile memory with lower power consumption.

Further, on the basis of the above three embodiments, as shown in Figure 11 and Figure 12, Figure 11 shows different non-volatile memory write delays based on ferroelectric transistor design - average write energy, read delay -Comparison of the three performances of average read energy, write delay-kinetic energy coefficient, Figure 12 is a comparison of performance indicators between different non-volatile memories designed based on ferroelectric transistors.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

In the description of this specification, descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and those skilled in the art can make the above-mentioned The embodiments are subject to changes, modifications, substitutions and variations.

Claims (13)

1. A circuit unit designed based on a ferroelectric transistor, characterized in that it comprises: a first transistor, a second transistor, a bit line, a first word line and a second word line, wherein, The gate of the first transistor is connected to the first word line, the drain of the first transistor is connected to the bit line, and the source of the first transistor is connected to the drain of the second transistor , the gate of the second transistor is connected to the second word line, the source of the second transistor is grounded or biased at a preset potential, and at least one of the first transistor and the second transistor is an iron electric transistor. 2. A kind of array circuit based on ferroelectric transistor design, it is characterized in that, comprising: At least one circuit unit according to claim 1, and each unit of the array circuit is combined into a multi-row and multi-column layout through electrical connection, wherein the first word lines of the circuit units in the same row are connected, and the same The second word lines of the circuit units of the row are connected, and the bit lines of the circuit units of the same column are connected. 3. The array circuit according to claim 2, wherein, When the data stored in the circuit unit is read, the voltage of the second word line of the circuit unit makes the second transistor of the circuit unit turn on, so that according to the first transistor of the circuit unit The magnitude of the resistance value between the drain and the source or the change of the magnitude of the resistance value on the voltage or current on the bit line of the circuit unit affects the resolution of the data stored by the circuit unit. 4. The array circuit according to claim 2, wherein, When the data stored in the circuit unit is written, the voltage of the bit line and the first word line is controlled so that the polarization characteristics of the first transistor of the circuit unit are consistent with the data stored in the circuit unit. The data is consistent. 5. The array circuit according to claim 4, wherein, When the data stored in the circuit unit is written, the voltage of the bit line is biased at a high level or a low level, and the voltage of the first word line stays at a low voltage and a high voltage for a period of time respectively Then restore to the original voltage, the voltage of the second word line makes the second transistor of the circuit unit cut off. 6. A circuit unit designed based on ferroelectric transistors, characterized in that it comprises: a first transistor, a second transistor, a third transistor, a first bit line, a second bit line, a first word line, a second word line with the third word line, where, The gate of the first transistor is connected to the first word line, the drain of the first transistor is connected to the gate of the second transistor, and the source of the first transistor is connected to the first bit line. line, the drain of the second transistor is connected to the source of the third transistor, the source of the second transistor is connected to the second word line, the gate of the third transistor is connected to the third word line The drain of the third transistor is connected to the second bit line, wherein at least one of the first transistor, the second transistor and the third transistor is a ferroelectric transistor. 7 . The circuit unit according to claim 6 , wherein the first bit line and the second bit line are combined into one bit line in the form of a short circuit. 8. An array circuit designed based on ferroelectric transistors, characterized in that it comprises: At least one circuit unit as claimed in claim 6, and each unit of the array circuit is combined into a multi-row and multi-column layout by electrical connection, wherein the first word lines of the circuit units in the same row are connected, and the same The second word lines of the circuit units in the same row are connected, the third word lines of the circuit units in the same row are also connected, the first bit lines of the circuit units in the same column are connected, and the second bit lines of the circuit units in the same column are also connected. 9. The array circuit according to claim 8, wherein, When performing a read operation on the data stored in the circuit unit, the voltage of the third word line makes the third transistor turn on, so that the resistance value between the drain and source of the second transistor is or its influence to distinguish the data stored by the circuit unit. 10. The array circuit according to claim 8, wherein, When the data stored in the circuit unit is written, the voltages of the second word line and the first bit line are controlled to make the polarization characteristics of the second transistor of the circuit unit consistent with the required The stored data is consistent. 11. The array circuit according to claim 10, wherein, When the data stored in the circuit unit is written, the voltage of the first bit line is biased at high level or low level, and the voltage of the first word line makes the first transistor conduct On, the voltage of the third word line turns off the third transistor. 12. The array circuit according to claim 11, wherein, When the data stored in the circuit unit is written, the voltage of the second word line stays at the low voltage and the high voltage for a period of time and then returns to the original voltage. 13. The array circuit according to any one of claims 8-12, wherein the first bit line and the second bit line are combined into one bit line in the form of a short circuit.