CN113473144B - YUV4:4:4 image transmission method - Google Patents
YUV4:4:4 image transmission method Download PDFInfo
- Publication number
- CN113473144B CN113473144B CN202110799433.8A CN202110799433A CN113473144B CN 113473144 B CN113473144 B CN 113473144B CN 202110799433 A CN202110799433 A CN 202110799433A CN 113473144 B CN113473144 B CN 113473144B
- Authority
- CN
- China
- Prior art keywords
- yuv4
- image
- fpga
- decoding
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 230000006835 compression Effects 0.000 description 14
- 238000007906 compression Methods 0.000 description 14
- 239000003086 colorant Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009313 farming Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/186—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/132—Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention relates to the technical field of multimedia, in particular to a YUV4:4:4 image transmission method, which comprises the steps of processing YUV4:4:4 image data by an FPGA coding system, obtaining YUV4:2:0 coded data and a first code by network transmission, decoding by an FPGA decoding system, and finally reversely restoring to a YUV4:4:4 image. The encoding and decoding system of the FPGA provided by the invention can be realized by using the middle-low-end FPGA without the support of DDR and other peripheral equipment, on one hand, under the condition of ensuring the minimum distortion, the encoding and decoding system of the FPGA can provide more excellent image quality and more excellent video playing experience; on the other hand, the FPGA is used for encoding and decoding, so that the image quality of YUV4:4:4 can be ensured, the color restoration requirement of desktop application is ensured, and the method is applicable to scenes such as desktop application with high requirement on image quality.
Description
Technical Field
The invention relates to the technical field of multimedia, in particular to a YUV4:4:4 image transmission method.
Background
The video demands are changed day by day, and the development of algorithms such as a large compression rate H.264/265 is promoted.
In the video transmission/display field, compression is performed using a large number of h.264/h.265 compression schemes, while a large number of ASIC chips provide compression modules for hardware. However, the prior art is limited to the compression algorithm of H.264/H.265, and the image can only use 4:2:2 color compression, so that most ASIC chips use 4:2:0 compression for cost and efficiency.
In most applications, particularly in meetings, large screen displays, etc. where detail reduction of single pixel images is required, a 4:4:4 color space acquisition processing system must be used. But 4:2:0 colors do not meet the requirements of desktop applications in terms of rendition.
Disclosure of Invention
In order to solve the technical problem that the color of 4:2:0 cannot meet the requirements of desktop application in the reduction degree, the technical scheme provided by the invention is as follows:
The invention provides a YUV4:4:4 image transmission method, which comprises the following steps:
step S1: acquiring first YUV4:4:4 image data;
Step S2: the FPGA programming system receives the first YUV4:4:4 image data and processes the first YUV4:2:0 image data to obtain a first code;
step S3: the first code obtained in the step S2 is sent through a network; encoding the first YUV4:2:0 image obtained in the step S2, and transmitting the encoded image through a network;
step S4: the FPGA decoding system receives the first code obtained in the step S3, and decodes and restores the first code; decoding the encoded first YUV4:2:0 image in the step S3 to obtain a second YUV4:2:0 image;
step S5: inputting the second YUV4:2:0 image into an FPGA decoding system, and combining the second YUV4:2:0 image with the decoded first code;
Step S6: a fourth YUV4:4:4 image is generated.
Further, the programming step of the FPGA programming system in step S2 includes:
step S11: downsampling the first YUV4:4:4 image data to generate a first YUV4:2:0 image;
step S12: upsampling the first YUV4:2:0 image to generate a second YUV4:4:4 image;
Step S13: calculating UV residual data of a first YUV4:4 image data and a second YUV4:4 image;
Step S14: and carrying out lossless coding on the UV residual data in the step S13 to obtain a first code.
Step S15: a first code stream is obtained through network first coding transmission;
Step S16: and encoding the first YUV4:2:0 image through an encoding ASIC supporting YUV4:2:0, and sending the encoded image through a network to obtain a second code stream.
Further, the decoding step of the FPGA decoding system in step S4 includes:
Step S21: receiving the first code, performing lossless decoding, and restoring the first code into UV residual data;
step S22: an ASIC supporting YUV4:2:0 decoding decodes the encoded first YUV4:2:0 image to generate a second YUV4:2:0 image;
Step S23: upsampling the second YUV4:2:0 image to generate a third YUV4:4:4 image;
Step S24: combining the third YUV4:4 image with the restored UV residual data;
step S25: a fourth YUV4:4:4 image is generated.
Further, the FPGA programming system and the FPGA decoding system are both realized through an FPGA chip.
Further, step S2 implements network transmission through the network switch.
Further, the decoding or encoding of the ASIC is implemented by an ASIC chip.
Further, the FPGA chip comprises any one of an A7 chip and a K7 chip of Xilinx, an Intel Cyclone10 chip, a Arria chip and a Lattice chip.
The invention has the advantages or beneficial effects that:
According to the YUV4:4 image transmission method, YUV4:4 image data are processed by an FPGA coding system, coded data of YUV4:2:0 and a first code are obtained through network transmission, then decoding is carried out through an FPGA decoding system, and finally the YUV4:4 image is reversely restored. The encoding and decoding system of the FPGA provided by the invention can be realized by using the middle-low-end FPGA without the support of DDR and other peripheral equipment, on one hand, the image quality can be improved under the condition that the minimum distortion of the image is ensured, and the video playing experience is improved; on the other hand, the FPGA is used for encoding and decoding, so that the image quality of YUV4:4:4 can be ensured, the color restoration requirement of desktop application is ensured, and the method is applicable to scenes such as desktop application with high requirement on image quality.
Drawings
The invention and its features, aspects and advantages will become more apparent from the detailed description of non-limiting embodiments with reference to the following drawings. Like numbers refer to like parts throughout. The drawings are not intended to be drawn to scale, emphasis instead being placed upon illustrating the principles of the invention.
Fig. 1 is a flowchart of a method for YUV4:4:4 image transmission according to embodiment 1 of the present invention.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components, and/or groups thereof.
The terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the invention.
The terms "first," "second," "third," and the like, as used herein, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" should be construed broadly, as if they were fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The following description of the technical solutions according to the embodiments of the present invention refers to the accompanying drawings, which are included to illustrate only some embodiments of the invention, and not all embodiments. Accordingly, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to fall within the scope of the present invention.
Example 1
In the video transmission/display field, compression is performed using a large number of h.264/h.265 compression schemes, while a large number of ASIC chips provide compression modules for hardware. However, the prior art is limited to the compression algorithm of H.264/H.265, and the image can only use 4:2:2 color compression, so that most ASIC chips use 4:2:0 compression for cost and efficiency.
In most applications, particularly in meetings, large screen displays, etc. where detail reduction of single pixel images is required, a 4:4:4 color space acquisition processing system must be used. But 4:2:0 colors do not meet the requirements of desktop applications in terms of rendition.
In order to solve the above technical problems, the present invention provides a method for transmitting YUV4:4:4 image, as shown in fig. 1, including:
Step S1: acquiring data of a first YUV4:4:4 image 1;
Step S2: the FPGA programming system 3 receives data of a first YUV4:4:4 image 1 and processes the data to obtain a first YUV4:2:0 image 2 and a first code;
step S3: the first code obtained in the step S2 is sent through a network; encoding the first YUV4:2:0 image 2 obtained in the step S2, and sending the encoded image through a network;
Step S4: the FPGA decoding system 4 receives the first code obtained in the step S3, decodes and restores the first code; decoding the encoded first YUV4:2:0 image 2 in the step S3 to obtain a second YUV4:2:0 image 21;
Step S5: inputting the second YUV4:2:0 image 21 to the FPGA decoding system 4, and combining with the decoded first code;
step S6: a fourth YUV4:4:4 image 13 is generated.
According to the YUV4:4 image transmission method, data of a first YUV4:4:4 image 1 are processed by an FPGA coding system, coded data of a first YUV4:2:0 image 2 and a first code are obtained through network transmission, then decoding is carried out through an FPGA decoding system 4, and finally the data are reversely restored to a fourth YUV4:4:4 image 13. The encoding and decoding system of the FPGA provided by the invention can be realized by using the middle-low-end FPGA without the support of DDR and other peripheral equipment, and can provide better image quality and better video playing experience under the condition of ensuring the minimum distortion of the image; in the second aspect, the FPGA is used for encoding and decoding, so that the image quality of YUV4:4:4 can be ensured, the color restoration requirement of desktop application is ensured, and the method is applicable to scenes such as desktop application with higher requirement on image quality; in the third aspect, on the basis of reducing the cost, the color reduction degree is effectively improved, and the method is not only suitable for 1080p images, but also suitable for 4k images or other resolution images, so that the displayed image color can meet the requirements of the public.
Preferably, in the method for transmitting YUV4:4:4 image provided by the present invention, as shown in fig. 1, the programming steps of the FPGA programming system 3 in step S2 include:
step S11: downsampling the data of the first YUV4:4:4 image 1 to generate a first YUV4:2:0 image 2;
Step S12: upsampling the first YUV4:2:0 image 2 to generate a second YUV4:4:4 image 11;
Step S13: calculating UV residual data of the first YUV4:4 image 1 data and the second YUV4:4 image 11;
step S14: the UV residual data in step S13 is subjected to lossless encoding or slightly lossy encoding to obtain a first encoding.
Step S15: transmitting the first code to obtain a first code stream through a network;
Step S16: and encoding the first YUV4:2:0 image 2 through an encoding ASIC supporting YUV4:2:0, and sending the encoded image 2 through a network to obtain a second code stream.
According to the invention, an FPGA encoding chip is arranged, an input first YUV4:4:4 image 1 is downsampled into a first YUV4:2:0 image 2, and then upsampled into a second YUV4:4:4 image 11. UV data is lost after the image changes from 4:4:4 to 4:2:0, even if upsampled back to a 4:4:4 image, there is a residual difference (residual) from the original image. The FPGA duplicates and calculates the UV residual, carries out lossless coding on the UV residual, or carries out lightweight lossy coding to form a first coding, and simultaneously, ASIC coding codes the first YUV4:2:0 image 2. According to the arrangement, on one hand, original image data is encoded and compressed through the FPGA and then is output in two parts, UV residual error data is reserved, the technical scheme of data loss after original image compression is changed, and the fault tolerance is improved; on the other hand, the first YUV4:2:0 image 2 and the first code are sent through a network to obtain different code streams (refer to data flow used by the video file in unit time), so that a distinguishing basis can be provided for subsequent decoding work, and the transmission is convenient.
Preferably, in the method for transmitting YUV4:4:4 image provided by the present invention, as shown in fig. 1, the decoding step of the FPGA decoding system 4 in step S4 includes:
Step S21: receiving the first code, performing lossless decoding, and restoring the first code into UV residual data;
step S22: an ASIC supporting YUV4:2:0 decoding decodes the encoded first YUV4:2:0 image 2 to generate a second YUV4:2:0 image 21;
Step S23: upsampling the second YUV4:2:0 image 21 to generate a third YUV4:4:4 image 12;
step S24: combining the third YUV4:4 image 12 with the restored UV residual data;
step S25: a fourth YUV4:4:4 image 13 is generated.
During decoding, the ASIC supporting 4:2:0 coding decodes the second code stream, changes the second code stream into a second YUV4:2:0 image, inputs the second YUV4:2:0 image to the FPGA, the FPGA restores the received first code stream into UV residual data, combines the UV residual data with the second YUV4:2:0 image 21 input into the FPGA decoding system 4, and finally restores the second YUV4:4 image 14 reversely. By arranging the FPGA decoding chip, the data is more convenient to read, and the operation efficiency is improved, so that the decoding efficiency of YUV4:4:4 images is improved. In addition, the FPGA is used for encoding and decoding the image, so that the visual lossless image quality reduction can be effectively realized.
Preferably, the FPGA programming system 3 and the FPGA decoding system 4 are both implemented by FPGA chips, including but not limited to any one of the A7 and K7 chips of Xilinx, the clone10 and Arria chips of Intel, and the Lattice chip. The FPGA chip used in the invention can realize the encoding and decoding functions only by adopting middle-low end products in the market.
Preferably, step S2 implements network transmission through a network switch.
Preferably, the decoding or encoding of the ASIC is implemented by an ASIC chip. Wherein, the coding ASIC includes but is not limited to Hai Si, rui-Chi, AMLogic, anba, a singing, etc. provide 4:2:0 encoding/decoding ASIC chip; also included are CODEC ASIC chips supporting 4:2:2 by Soxhlet et al. The farming ASIC chip only needs to support standard H.264/H.265 encoding and decoding of 4:2:0, the chips can realize YUV4:4 image transmission, the performance is stable, the reliability of YUV4:4:4 image transmission is further improved, and the production cost can be effectively reduced.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the present invention and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present invention.
Claims (6)
1. A method for YUV4:4:4 image transmission, comprising:
Step S1: acquiring data of a first YUV4:4 image;
Step S2: the FPGA programming system receives and processes data of a first YUV4:4:4 image to obtain a first YUV4:2:0 image and a first code;
step S3: the first code obtained in the step S2 is sent through a network; encoding the first YUV4:2:0 image obtained in the step S2, and transmitting the encoded image through a network;
step S4: the FPGA decoding system receives the first code obtained in the step S3, and decodes and restores the first code; decoding the encoded first YUV4:2:0 image in the step S3 to obtain a second YUV4:2:0 image;
step S5: inputting the second YUV4:2:0 image into an FPGA decoding system, and combining the second YUV4:2:0 image with the decoded first code;
step S6: generating a fourth YUV4:4:4 image;
the programming step of the FPGA programming system in step S2 includes:
Step S11: downsampling data of a first YUV4:4:4 image to generate a first YUV4:2:0 image;
step S12: upsampling the first YUV4:2:0 image to generate a second YUV4:4:4 image;
Step S13: calculating data of a first YUV4:4 image and UV residual data of a second YUV4:4 image;
step S14: performing lossless coding on the UV residual data in the step S13 to obtain a first code;
step S15: transmitting the first code to obtain a first code stream through a network;
Step S16: and encoding the first YUV4:2:0 image through an encoding ASIC supporting YUV4:2:0, and sending the encoded image through a network to obtain a second code stream.
2. The method for YUV4:4:4 image transmission according to claim 1, wherein the decoding step of the FPGA decoding system in step S4 comprises:
Step S21: receiving the first code, performing lossless decoding, and restoring the first code into UV residual data;
step S22: an ASIC supporting YUV4:2:0 decoding decodes the encoded first YUV4:2:0 image to generate a second YUV4:2:0 image;
Step S23: upsampling the second YUV4:2:0 image to generate a third YUV4:4:4 image;
Step S24: combining the third YUV4:4 image with the restored UV residual data;
step S25: a fourth YUV4:4:4 image is generated.
3. The method for transmitting the YUV4:4:4 image according to any one of claims 1-2, wherein the FPGA programming system and the FPGA decoding system are implemented by FPGA chips.
4. The method for YUV4:4:4 image transmission according to claim 1, wherein step S2 implements network transmission through a network switch.
5. The method of YUV4:4:4 image transmission according to claim 2, wherein the decoding or encoding of the ASIC is implemented by an ASIC chip.
6. The method for transmitting YUV4:4:4 image according to claim 3, wherein said FPGA chip comprises any one of Xilinx A7 and K7 chips, intel Cyclone10 chip and Arria chip and Lattice chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110799433.8A CN113473144B (en) | 2021-07-15 | 2021-07-15 | YUV4:4:4 image transmission method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110799433.8A CN113473144B (en) | 2021-07-15 | 2021-07-15 | YUV4:4:4 image transmission method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113473144A CN113473144A (en) | 2021-10-01 |
| CN113473144B true CN113473144B (en) | 2024-07-26 |
Family
ID=77880430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110799433.8A Active CN113473144B (en) | 2021-07-15 | 2021-07-15 | YUV4:4:4 image transmission method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113473144B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104919804A (en) * | 2012-10-01 | 2015-09-16 | 微软技术许可有限责任公司 | Frame packing and depacking of higher resolution chroma sampling formats |
| CN110381278A (en) * | 2019-09-05 | 2019-10-25 | 无锡思朗电子科技有限公司 | Method and apparatus for color space 4:4:4 transmission |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018160909A (en) * | 2018-05-23 | 2018-10-11 | 株式会社ニコン | Encoding device, decoding device, encoding method, and decoding method |
| US11095921B2 (en) * | 2018-12-18 | 2021-08-17 | Tencent America LLC | Method and apparatus for video encoding or decoding |
| CN209982615U (en) * | 2019-09-05 | 2020-01-21 | 无锡思朗电子科技有限公司 | Apparatus for color space 4:4:4 transmission |
| CN110855996B (en) * | 2019-09-30 | 2021-10-22 | 中国船舶重工集团公司第七0九研究所 | Image coding and decoding and network transmission method and device based on FPGA |
| CN111031388B (en) * | 2019-11-25 | 2022-05-20 | 无锡思朗电子科技有限公司 | YUV4:4:4 data coding and decoding method |
-
2021
- 2021-07-15 CN CN202110799433.8A patent/CN113473144B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104919804A (en) * | 2012-10-01 | 2015-09-16 | 微软技术许可有限责任公司 | Frame packing and depacking of higher resolution chroma sampling formats |
| CN110381278A (en) * | 2019-09-05 | 2019-10-25 | 无锡思朗电子科技有限公司 | Method and apparatus for color space 4:4:4 transmission |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113473144A (en) | 2021-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12075081B2 (en) | Super-resolution loop restoration | |
| CN101588252B (en) | Control method and control device of multipoint conference | |
| CN101594512B (en) | Terminal, multi-point control unit, system and method for realizing high definition multiple images | |
| JP4888729B2 (en) | Encoding apparatus and method, and decoding apparatus and method | |
| CN101656825B (en) | Method and system for processing signals | |
| US20170111661A1 (en) | Method and system of video coding with post-processing indication | |
| US20250310564A1 (en) | Architecture for signal enhancement coding | |
| EP2731337B1 (en) | Systems and methods for transmitting video frames | |
| US6108027A (en) | Progressive still frame mode | |
| CN101873489A (en) | Signal processing method and system | |
| EP2590415A2 (en) | Image processing apparatus and method for format conversion | |
| JPH0870440A (en) | Method and apparatus for converting video signal coded in accordance with different standard for video transmission | |
| CN108076301A (en) | The method for processing video frequency and system of VoLTE video multi-party telephones | |
| CN101237583B (en) | Encoding and decoding method and device for realizing multi-split screen | |
| JP2933132B2 (en) | Multipoint video conference control device and screen synthesis encoding method | |
| Chen et al. | HEVC-based video coding with lossless region of interest for telemedicine applications | |
| CN113473144B (en) | YUV4:4:4 image transmission method | |
| US9264709B2 (en) | Method and device for mixing video streams at the macroblock level | |
| JPH1146361A (en) | Image compression method, image compression device, digital camera, portable information terminal, image decompression device, and image transmission system | |
| CN103796020A (en) | Encoding apparatus, decoding apparatus, encoding method and decoding method | |
| JPS62200883A (en) | Graphic display device for electronic conference system | |
| US20070223573A1 (en) | Method and apparatus for encoding/decoding a first frame sequence layer based on a second frame sequence layer | |
| CN101237572A (en) | A space hierarchical video image coding and decoding method | |
| JPH0678305A (en) | Composite information transmitter | |
| Misu et al. | Real-time 8K/4K video coding system with super-resolution inter-layer prediction |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |