CN114064458B

CN114064458B - Universal JTAG debugging method and system with scalable interface

Info

Publication number: CN114064458B
Application number: CN202111242970.9A
Authority: CN
Inventors: 刘佩; 马鹏; 张伟; 任敏华; 王叶辉; 于建旺; 於健; 施陈婷
Original assignee: CETC 32 Research Institute
Current assignee: CETC 32 Research Institute
Priority date: 2021-10-25
Filing date: 2021-10-25
Publication date: 2025-10-03
Anticipated expiration: 2041-10-25
Also published as: CN114064458A

Abstract

The present invention provides a universal JTAG debugging method and system with an expandable interface, comprising: encapsulating a JTAG host controller into an IP device of a peripheral bus port; invoking the hardware resources within a development board, attaching the JTAG host IP to the hardware system, and completing the minimum hardware field programmable gate array design of the debugging system; completing the boot loader porting work according to the characteristics of the development board; compiling within the ported boot loader, and solidifying the binary file into the development board; connecting a debugging device with a host computer, and connecting the debugging device with a target debugging chip; the host computer running hyperterminal software, and completing the target chip debugging work through data JTAG debugging instructions. The present invention can be flexibly integrated into an embedded system having a processor core, RAM, ROM, GPIO pins, JTAG_MASTER, and UART devices, completing the construction of the debugging system hardware part, and has flexibility; the modular JTAGMaster controller can realize JTAG protocol conversion and simultaneously connect multiple JTAG devices with the same or different characteristics.

Description

JTAG debugging method and system with extensible interface and universality

Technical Field

The invention relates to the technical field of electronic equipment maintenance, in particular to a JTAG debugging method and system with extensible interface and universality.

Background

The integrated circuit industry develops according to moore's law, the scale of integrated circuits is larger and larger, and the circuits which can be integrated on a single chip are more and more complex. The method means that unknown failure conditions, material defects, manufacturing deviations and other risk events are easier to face in the chip development stage, so that the situation that the chips which flow back cannot work normally or the performance is not optimal according to expectations occurs. The IEEE 1149.1 standard was published in 1990 based on chip design-for-testability considerations. Currently, the ARM processor series, the PowerPC processor series and the complex control devices such as PCIE PHY, SATA PHY, EMMC controller and the like on the market integrate testability hardware logic based on IEEE 1149.1 protocol according to the characteristics of the respective devices, and provide JTAG debug interfaces, so that the on-line debugging function of the devices is supported on hardware.

The debugging system provided by each device has strong specificity and high price, and belongs to the development and development of foreign companies. For example, the JTAG debug system matched with the ARM processor series is a J-Link emulation debugger and matched software provided by SEGGER company in Germany, only an agent is provided in China at present, no domestic version exists, and the debug system matched with the PowerPC processor series is a RISCWATCH emulation debugger and matched software provided by IBM company in the United states. TRACE32 developed by Lauterbach, germany later can support debugging work of JTAG interface and BDM interface and all CPUs, but the purchase price is more expensive, and one TRACE32 purchase price is tens of thousands yuan. The debugging equipment is connected with the upper PC through a USB port, matched application software is needed to be used as an interactive interface, the application software is installed to have requirements on an operating system of the upper PC, and the support of a winning kylin type domestic operating system is not good.

The problem to be solved at present is that 1, the purchase price of debugging equipment is too high and provided by foreign companies, some foreign countries need to be vigilant to the policy at present, the related tools of chip research and development have domestic demands, 2, the debugging devices Jlink, TRACE32 and riscwatch on the market need to use USB ports, the matched application software of the host computer needs to run, the matched application software of the host computer supports the domestic operation system poorly, 3, the debugging equipment pushed on the market cannot be connected with a plurality of equipment with different characteristics at the same time to carry out debugging work, for example, an ARM processor core and a PCIE controller are integrated in one chip to be debugged jointly with another PCIE chip, the current practice is that three TRACE32 debuggers are connected with an ARM processor JTAG interface and a main PCIE PHY JTAG interface respectively, the TRACE32 software environment is limited to have three idle USB ports or three host computers need to be connected respectively, the required hardware resources are more, and if one TRACE32 is switched back and forth to be connected, the testing operation is complex and the problem positioning cannot be observed at the same time. Therefore, the invention provides a JTAG debugging system with extensible interface and universality, which is connected with an upper computer by utilizing a serial port, an interactive interface uses a serial port debugging assistant such as a super terminal, and the like, does not require the environment of the upper computer system, and is used for solving the localization problem of the debugging system and the problem of simultaneously connecting a plurality of debugging equipment with different characteristics, thereby realizing the multi-device online debugging function.

The patent document CN113268031A (application number: CN 202110631019.6) provides a system and a method for remotely debugging a tool of electronic equipment, and relates to the technical field of electronic equipment maintenance, wherein the system comprises a JTAG service program and an application program running in a Linux operating system, and is used for interacting with the remote program to perform client data transceiving and provide a data transceiving function; the hardware board provides FPGA resources to form an embedded hardware environment, the FPGA resources provided by the hardware board are used to form an embedded minimum system, the embedded minimum system is formed by adding a hardware module necessary for FPGA remote debugging, a mode of completing FPGA debugging in the Ethernet is adopted, and a service end program is designed in a JTAG data processing program, so that the remote operation of a network communication protocol becomes realistic, and the FPGA chips are accessed through a designated network address, so that the purposes of commonly accessing the same chip and debugging a plurality of FPGA chips by a plurality of persons are achieved, and the use of the FPGA debugging mode is wider and more convenient. However, the development of the firmware of the invention depends on the environment which is not Uboot system, and the firmware can not be well operated on various operating systems, and the compatibility is not enough.

The invention discloses an expandable JTAG debugging structure integrating a bidirectional CRC check function, which comprises a debugging main controller and a debugging sub-controller, wherein the debugging main controller receives data of a JTAG interface, sends the data without error to the corresponding debugging sub-controller after data check and instruction analysis, further processes and executes the data, and the debugging sub-controller receives the control of the debugging main controller and realizes the debugging operation of a debugging object and returns the debugging data according to the corresponding data instruction. However, the invention does not have a module JTAG Master controller, can not realize JTAG protocol conversion and simultaneously connect with JTAG devices with the same or different multipath characteristics, and has insufficient expandability.

The english abbreviations are explained as follows:

JTAG (Joint Test Action Group, joint test working group)

Uboot (Universal Boot Loader, boot loader)

JTAG Master (Joint Test Action Group Master, JTAG host)

ROM (Read-Only Memory)

RAM (Random Access Memory )

GPIO (General-Purpose Input/Output, general-Purpose Input and Output)

AMBA (Advanced Microcontroller Bus Architecture high-level microcontroller bus architecture)

APB (ADVANCED PERIPHERAL Bus, peripheral Bus)

TMS (Test Mode Select, test Mode selection)

TCK (Test Clock)

TDI (TEST DATA IN, test data input)

TDO (Test Data Out, test Data output)

TRSTn (TEST RESET )

TAP (TEST ACCESS Port, test access interface)

Menuconfig (menu configuration)

EDA (Electronic design automat ion electronic design automation)

Zynq-7000 (xil inx A FPGA product, official network of English abbreviation meaning description)

DDR (Double DATA RATE SDRAM Double speed synchronous dynamic random access memory)

SPI Flash (SERIAL PERIPHERAL INTERFACE FLASH, serial Flash)

UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter)

FPGA (Field Programmable GATE ARRAY field programmable gate array)

CMD (Command, order)

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a JTAG debugging method and system with extensible interface and universality.

The JTAG debugging method with extensible interface and universality provided by the invention comprises the following steps:

Step S1, packaging JTAG host controller into IP device of peripheral bus port;

s2, calling a self-contained hardware resource in a development board, and connecting a JTAG host IP to a hardware system to complete the design of a minimum hardware field programmable gate array of a debugging system;

step S3, completing the transplanting work of the boot loader according to the characteristics of the development board;

s4, compiling in the transplanted boot loader, and solidifying the binary file to a development board;

And S5, the debugging device and the upper computer are used for debugging the target chip, the upper computer runs the super terminal software, and the target chip debugging work is completed through the data JTAG debugging instruction.

Preferably, the debugging system integrates a CPU core, a serial port, a ROM, a RAM, a self-grinding JTAG host controller and general input and output pins;

The serial port is connected with the PC interactive port of the upper computer, the ROM is used for storing the solidifying debugging application software, the RAM is used for storing the storage space required by the software operation, the general input and output pins are used for JTAG external communication interfaces, and the JTAG host controller is used for realizing protocol conversion operation.

Preferably, in said step S1:

The JTAG host controller converts data into JTAG signals according to IEEE1149.1 protocol and outputs the JTAG signals, and the JTAG host controller interface design selects an AMBA APB interface protocol, so as to realize the debugging function by connecting a plurality of devices on line at the same time, and design JTAG interface signals, including test mode selection, test clock, test data output, test data input and test reset;

According to the TAP state machine design of IEEE1149.1 protocol, state transition is controlled by TMS, and JTAG MASTER controller defines 16 states for controlling TMS signal output, including ST_TLR logic reset state, ST_RTI running idle state, ST_SDR select data scan state, ST_CDR data capture state, ST_SHD data shift state, ST_E1D data exit 1 state, ST_E2D data exit 2 state, ST_PDR data transmission pause state, ST_UDR update data value state, ST_SIR select instruction scan state, ST_CIR instruction capture state, ST_SHI instruction shift state, ST_E1I instruction exit 1 state, ST_PIR instruction transmission pause state, ST_E2I instruction exit 2 state, ST_UIR update instruction value state, realizing that register configuration instruction is transferred to JTAG protocol;

The JTAG host provides registers of corresponding functionality for the JTAG interface.

Preferably, in said step S3:

the Uoot is a bootstrap program before the start of the embedded operating system, and can support various types of embedded processors.

Preferably, in said step S4:

According to the file format, command configuration option information of a JTAG host is added, a group of debugging instructions are respectively defined for JTAG interfaces, the JTAG host configuration option selects whether to add debugging system firmware into a Uoot compiling environment, after selection is successful, a bin file is generated through compiling, and contents are solidified to a debugging device through an electronic design automation tool.

The JTAG debugging system with extensible interface and universality provided by the invention comprises:

JTAG host controller is packaged into IP device of peripheral bus port;

The module M2 calls the hardware resources in the development board, and hangs the JTAG host IP to the hardware system to complete the minimum hardware field programmable gate array design of the debugging system;

The module M3 is used for completing the transplanting work of the boot loader according to the characteristics of the development board;

a module M4, compiling in the transplanted boot loader, and solidifying the binary file to a development board;

And the module M5 is used for debugging the device and the upper computer, the debugging device and the target debugging chip, the upper computer runs the super terminal software, and the target chip debugging work is completed through the data JTAG debugging instruction.

Preferably, in said module M1:

Preferably, in said module M3:

Preferably, in said module M4:

Compared with the prior art, the invention has the following beneficial effects:

1. The method can be flexibly integrated into an embedded system with a processor core, RAM, ROM, GPIO pins, JTAG_MASTER and UART devices, and the hardware part of the debugging system is built, so that the method has flexibility;

2. The self-research module JTAG Master controller can realize JTAG protocol conversion and simultaneously connect JTAG equipment with the same or different multipath characteristics, realize the on-line debugging function of multiple devices, and the number of on-line debugging hardware can be customized according to the requirement, so that the on-line debugging hardware has expandability;

3. the development of the firmware depends on the environment being a Uboot system, and the debugging command is sent only by a serial port debugging assistant of a super terminal class installed on the upper computer as an interactive interface, so that almost no excessive requirements are required on the machine performance of the upper computer system configuration, and the system can be well operated on various operating systems and has compatibility;

UBIOT is a bootstrap program before the start of an embedded operating system, is open in code source, can support various types (PowrPC, ARM, MIPS, x, XScale and the like) of an embedded processor, is high in code reliability and good in stability, means that UBIOT is selected as a firmware development environment of a debugging system, has a good hardware support basis, and also means that when the hardware design of the debugging system is applied, the type coverage PowerPC, ARM, x86 and the like of the processor can be supported, and has certain universality.

Drawings

Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:

FIG. 1 is a communication diagram of a debug system;

FIG. 2 is a hardware block diagram of a debug system;

FIG. 3 is a Jtag_Master controller state machine;

FIG. 4 is zynq-7000 building a debug system;

FIG. 5 is a debug system application interface.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.

Example 1:

Step S1, packaging JTAG host controller into IP device of peripheral bus port;

Specifically, the debugging system integrates a CPU core, a serial port, a ROM, a RAM, a self-grinding JTAG host controller and general input and output pins;

Specifically, in the step S1:

Specifically, in the step S3:

Specifically, in the step S4:

Example 2:

Example 2 is a preferable example of example 1 to more specifically explain the present invention.

A person skilled in the art may understand the JTAG debugging method with extensible interface and universality provided by the present invention as a specific implementation manner of the JTAG debugging system with extensible interface and universality, that is, the JTAG debugging system with extensible interface and universality may be implemented by executing the step flow of the JTAG debugging method with extensible interface and universality.

JTAG host controller is packaged into IP device of peripheral bus port;

Specifically, in the module M1:

Specifically, in the module M3:

Specifically, in the module M4:

Example 3:

example 3 is a preferable example of example 1 to more specifically explain the present invention.

As shown in FIG. 1, the debugging device is connected with the upper PC through a serial port, and is connected with a debugging target through a JTAG (Joint Test Action Group, joint test working group) interface signal line, the upper PC runs serial port debugging software, such as a super terminal, a serial port debugging assistant and the like, a proper baud rate is configured, the debugging device is powered on to start Uboot (Universal Boot Loader, a boot loader) and enter a command input window, a currently debugged target board (JTAG port number) can be selected according to a predefined command, and finally, the debugging target board is converted into JTAG interface signals conforming to the characteristics of a target device through a JTAG Master (Joint Test Action Group Master, JTAG host) controller, so that the multi-device online debugging action is completed.

Key point 1 flexibility of debug System

In view of the cost and flexibility of the hardware design of the debug system, as shown in fig. 2, the minimum hardware structure of the debug system Only needs to integrate CPU core, serial port, ROM (Read-Only Memory), RAM (Random Access Memory ) and self-grinding JTAG Master controller, GPIO (General-Purpose Input/Output) pins inside the debug system. The serial port supports common baud rates 115200bps, 57600bps, 38400bps and the like, interacts with an upper PC, the ROM is used for storing solidifying and debugging application software, the RAM is used for storing storage space required by software operation, the GPIO pin is used for JTAG external communication interface, and the JTAG Master controller is used for realizing protocol conversion operation.

Main point 2. JTAG Master controller design-JTAG protocol conversion and multiplexing device simultaneous connection are realized

The JTAG Master controller belongs to self-research design, converts Data into JTAG signal output according to IEEE1149.1 protocol, and selects AMBA APB (AMBA, advanced Microcontroller Bus Architecture, advanced microcontroller Bus architecture) (APB, advanced Peripheral Bus, peripheral Bus) interface protocol in consideration of universality, and designs four groups of JTAG interface (TMS, TCK, TDO, TDI, TRSTn) signals, TMS (Test Mode Select), TCK (Test Clock), TDI (TEST DATA IN, test Data input), TDO (Test Data Out), TRSTn (TEST RESET ) for realizing the debugging function of connecting a plurality of devices on line simultaneously.

According to the TAP (TEST ACCESS Port, test Access interface) state machine design of IEEE1149.1 protocol, state transition is controlled by TMS, as shown in FIG. 3, the JTAG MASTER controller defines 16 states for controlling TMS signal output, including ST_TLR (logic reset state), ST_RTI (run idle state), ST_SDR (select data scan state), ST_CDR (data capture state), ST_SHD (data shift state), ST_E1D (data exit 1 state), ST_E2D (data exit 2 state), ST_PDR (data transfer pause state), ST_UDR (update data value state), ST_SIR (select instruction scan state), ST_CIR (instruction capture state), ST_SHI (instruction shift state), ST_E1I (instruction exit 1 state), ST_PIR (instruction transfer pause state), ST_E2I (instruction exit 2 state), ST_UIR (update instruction value state), realizing transfer of register configuration instruction to a protocol-transferred JTAG device.

The JTAG Master provides four sets of registers for four JTAG interfaces, as shown in the following table, for implementing JTAG for each interface, and provides the following list of registers for support

The corresponding JTAG Master controller provides registers for the corresponding functions as shown in the following table.

The specific definition of these registers is described below.

(1) JTAGx _DATD_VALUE (x=0-3): data register

The specific definition of the register is as follows:

(2) JTAGx _INSTR_VALUE (x=0-3) instruction register

The specific definition of the register is as follows:

(3) JTAGx _control (x=0-3) CONTROL register

The specific definition of the register is as follows:

(4) JTAGx _INTR_EN (x=0-3) interrupt status and enable register

The specific definition of the register is as follows:

(5) JTAGx _INTR_STATUS (x=0-3) software mode and STATUS registers

The specific definition of the register is as follows:

Bit field	Read-write attributes	Description of the invention
			31:4	R	Reservation of
3	RW	Interrupt status bit for instruction transmission suspension, write 1 clear
			2	RW	Interrupt status bit for completing instruction transmission, write 1 zero clearing
1	RW	Data transmission pause interrupt status bit, write 1 clear
			0	RW	Data transmission completion interrupt status bit, write 1 clear

(6) JTAGx TCK CONFIG (x=0-3) TCK control register

The specific definition of the register is as follows:

the key point 3 is that firmware develops and applies Uboot environment, and designs debugging instructions based on Uboot command system

The Uoot is a guide program before the embedded operating system is started, and the code is open-source and can support the variety of embedded processors (PowrPC, ARM, MIPS, x, XScale and the like), so that the code reliability is high and the stability is good. The method means that UBoot is selected as a firmware development environment of the debugging system, has a good hardware support basis, and also means that the method can support selection of type coverage PowerPC, ARM, x, 86 and the like of a processor when the hardware design of the debugging system is applied, and has certain universality. UBoot is selected as a development environment, and because the existing command system can conveniently complete the development work of JTAG debug instructions based on the C language.

Adding Command LINE INTERFACE- > JTAG Master configuration selectable items into Uoot source code menuconfig (menu configuration), adding Command configuration option information of JTAG Master according to Uboot cmd/Kconfig file format, realizing that when a menuconfig configuration graphical interface is started, selecting a Command line interface option, and entering a next-level catalog to select a JTAG Master option (Command LINE INTERFACE- > JTAG Master option), thereby achieving the effect of adding a JTAG Command into Uboot compiling environment. This section belongs to firmware development, a set of debug instructions is defined for each of the four JTAG interfaces, the instruction definition is shown below, the JTAG Master configuration option selects whether to add debug system firmware into UBoot compiling environment, after selection succeeds, compiling generates bin files, and the content is solidified to the debug apparatus by means of an eda (Electronic des ign automation ) tool.

List of table debug instructions

Example 4:

example 4 is a preferable example of example 1 to more specifically explain the present invention.

A debugging system is built by using Zynq-7000 (an FPGA product of xilinux corporation, which is introduced by no English abbreviation meaning on a official network), as shown in fig. 4, if the Zynq-7000 is not used, an FPGA board containing processor core resources, memory resources, configurable GPIO pin resources and UART resources can be used for replacing the resources, and the corresponding firmware development thinking can be any one of PowerPC series, ARM series, x86 series and MIPS series. The FPGA board which is commonly used in the market at present and can be used as a replacement comprises Zynq-7010/Zynq-7020\Zynq UltraScale+MPSoC series with ARM processor core resources, xilinx Virtex-II Pro series FPGA boards with PowerPC processor core resources and the like.

1. Encapsulating the key point 2 into an IP device of an AMBA APB port by using an eda tool by using a self-developed JTAG Master controller;

2. Invoking self-contained hardware resources in the Zynq-7000 board, namely ARM Cortex-a9 CPU core, DDR (Double DATA RATE SDRAM, double rate synchronous dynamic random memory) controller and DDR storage particles, SPI Flash (SERIAL PERIPHERAL INTERFACE FLASH, serial Flash) controller and Flash particles, UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter) ports and GPIO pins, and hanging JTAG_Master IP to a hardware system through an AMBA APB bus to finish the design of the minimum hardware FPGA (Field Programmable GATE ARRAY ) of the debugging system;

3. completing Uboot transplanting work according to Zynq-7000 plate characteristics;

4. Adding the JTAG debug instruction mentioned in the point 3 into the transplanted Uboot by using a CMD (Command) system, and solidifying the binary file to a Zynq-7000 board after compiling successfully;

5. As shown in fig. 1, the debugging device is connected with the upper computer through a serial port line, the debugging device is connected with the target debugging chip through a JTAG flat cable, the upper computer runs super terminal software, the super terminal belongs to computer serial interactive terminal software, the target chip debugging work can be completed through serial ports, modems or Ethernet ports through data JTAG debugging instructions, as shown in fig. 5, the debugging interactive interface screenshot is obtained.

Those skilled in the art will appreciate that the systems, apparatus, and their respective modules provided herein may be implemented entirely by logic programming of method steps such that the systems, apparatus, and their respective modules are implemented as logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc., in addition to the systems, apparatus, and their respective modules being implemented as pure computer readable program code. Therefore, the system, the device and the respective modules thereof provided by the invention can be regarded as a hardware component, and the modules for realizing various programs included therein can be regarded as a structure in the hardware component, and the modules for realizing various functions can be regarded as a structure in the hardware component as well as a software program for realizing the method.

The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.

Claims

1. A universal JTAG debugging method with an extensible interface, comprising:

Step S1: The JTAG host controller is encapsulated as an IP device of a peripheral bus port;

Step S2: Call the hardware resources in the development board, connect the JTAG host IP to the hardware system, and complete the minimum hardware field programmable gate array design of the debugging system;

Step S3: According to the characteristics of the development board, complete the boot loader program transplantation work;

Step S4: compile the ported boot loader and solidify the binary file into the development board;

Step S5: The debugging device is connected to the host computer via a serial port, and the debugging device is connected to the target debugging chip via a JTAG interface signal line. The host computer runs the HyperTerminal software and completes the target chip debugging work by sending JTAG debugging instructions.

The debugging system integrates CPU core, serial port, ROM, RAM, self-developed JTAG host controller, and general input and output pins;

The serial port is connected to the host PC interactive port; ROM is used to store the fixed debugging application software; RAM is used as the storage space required for software operation; general input and output pins are used for JTAG external communication interface; JTAG host controller is used to implement protocol conversion operations;

In the step S4:

According to the file format, add command configuration option information of the JTAG host, define a set of debugging instructions for each JTAG interface, and select whether to add the debugging system firmware to the UBoot compilation environment in the JTAG host configuration option. After successful selection, compile and generate a bin file, and solidify the content into the debugging device through electronic design automation tools.

2. The JTAG debugging method with scalable and universal interface according to claim 1, wherein in step S1:

The JTAG host controller converts data into JTAG signal output according to the IEEE1149.1 protocol. The JTAG host controller interface design selects the AMBA APB interface protocol. In order to realize the online simultaneous connection of multiple devices for debugging, the JTAG interface signals are designed, including test mode selection, test clock, test data output, test data input, and test reset;

According to the TAP state machine design of the IEEE1149.1 protocol, state transition is controlled by TMS. The JTAG MASTER controller defines 16 states for controlling TMS signal output, including: ST_TLR logic reset state, ST_RTI run idle state, ST_SDR select data scan state, ST_CDR data capture state, ST_SHD data shift state, ST_E1D data exit 1 state, ST_E2D data exit 2 state, ST_PDR data transmission pause state, ST_UDR update data value state, ST_SIR select instruction scan state, ST_CIR instruction capture state, ST_SHI instruction shift state, ST_E1I instruction exit 1 state, ST_PIR instruction transmission pause state, ST_E2I instruction exit 2 state, ST_UIR update instruction value state, to realize the conversion of register configuration instructions into JTAG protocol and transmit them to the target debugging device;

The JTAG host provides registers with corresponding functions for the JTAG interface.

3. The JTAG debugging method with scalable and universal interface according to claim 1, wherein in step S3:

Firmware development that matches the hardware is based on the Uboot environment. UBoot is a boot program before the embedded operating system starts. The code is open source and can support a variety of embedded processors.

4. A universal JTAG debugging system with an extensible interface, comprising:

Module M1: JTAG host controller encapsulated as an IP device of the peripheral bus port;

Module M2: Calls the hardware resources built into the development board, connects the JTAG host IP to the hardware system, and completes the minimum hardware field programmable gate array design of the debugging system;

Module M3: Complete the boot loader porting work according to the characteristics of the development board;

Module M4: compiles the ported boot loader and fixes the binary file to the development board;

Module M5: The debugging device is connected to the host computer through the serial port, and the debugging device is connected to the target debugging chip through the JTAG interface signal line. The host computer runs the hyperterminal software and completes the target chip debugging work through the data JTAG debugging instructions;

In the module M4:

5. The universal JTAG debugging system with an expandable interface according to claim 4, wherein in the module M1:

6. The universal JTAG debugging system with an expandable interface according to claim 4, wherein in the module M3: