CN114709233B - A method for integrating germanium p-i-n photodiodes into image sensor structures - Google Patents
A method for integrating germanium p-i-n photodiodes into image sensor structures Download PDFInfo
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Abstract
The invention provides a method for integrating a germanium p-i-n photodiode into an image sensor structure, which relates to the technical field of semiconductors, and comprises the steps of determining the thickness of a germanium transfer layer by injecting hydrogen ions (H +) into a germanium donor wafer to a selected depth, separating the germanium transfer layer from the germanium donor wafer through the surfaces of a Bei Dajian germanium donor wafer and a silicon target wafer to obtain a germanium-silicon mixed wafer, grinding the surface of the germanium transfer layer of the germanium-silicon mixed wafer, injecting doped element ion boron ions (B +) into the germanium transfer layer on the top of the germanium-silicon mixed wafer, so that the part, close to the surface, of the germanium transfer layer is injected with boron to form a doped germanium layer, and forming an isolation structure between pixels in the germanium photodiode layer to define a photodiode region. The invention realizes a high-speed, small-pixel-size and CMOS compatible short-wave infrared image sensor (with a focal plane array) with a low-cost and relatively simpler manufacturing process, and is suitable for industrialized mass production.
Description
Technical Field
The invention belongs to the technical field of semiconductors, relates to a method for integrating a germanium p-i-n photodiode into an image sensor structure, and particularly relates to a method for manufacturing a vertical p-i-n photodiode of a CMOS image sensor.
Background
Currently, short-wave infrared CMOS image sensors (SWIR CMOS Image Sensor) are widely applied to the fields of small unmanned aerial vehicle systems, motor vehicle systems, intelligent agricultural systems, monitoring systems and the like. As is well known in the art, the use of silicon materials as photodiodes has low quantum efficiency for infrared absorption, and in particular has little absorption in the wavelength band above 1 μm. Compared to silicon, germanium-based short wave infrared CMOS image sensors can capture images from visible light (0.4 μm-0.75 μm) and beyond (up to 1.6 μm wavelength) and perform comparable to indium gallium arsenide (InGaAs). CMOS image sensors based on indium gallium arsenide, while capable of providing high quality Focal Plane Arrays (FPAs) with high quantum efficiency and relatively low dark current, are currently complex in fabrication process, expensive, low in yield, and difficult to be applied commercially on a large scale. In contrast to indium gallium arsenide, germanium is chemically compatible with silicon and compatible with silicon CMOS fabrication processes. Thus, the fabrication process for germanium-based photodiodes for short-wave infrared CMOS image sensors is more flexible, cost-effective and scalable, and opens up consumer/mass market applications.
In the case of manufacturing a CMOS image sensor based on germanium, the prior art generally adopts direct epitaxial growth of germanium on a silicon target wafer, but because of lattice mismatch of 4.2% between germanium and silicon, the epitaxial growth can generate misfit dislocation and threading dislocation (threading dislocation), so that defects are more, quality is lower, and detection signal to noise ratio and detection sensitivity are affected. This problem, while now ameliorated by some means of technology, can increase device structure and/or process complexity, such as selective manufacturing growth using narrow apertures. In addition, the use of direct epitaxial growth of germanium on a silicon target wafer is a low temperature growth of germanium on a silicon wafer, directly resulting in reduced quality of the germanium layer.
Based on the needs of industrial and consumer/mass market applications, there is an urgent need for a method that is simpler in process, lower in cost, and capable of efficiently and stably integrating vertical germanium p-i-n photodiodes into image sensing integrated device structures.
Disclosure of Invention
Based on the problems of the prior art, the present invention provides a method of integrating germanium p-i-n photodiodes into an image sensor structure, in particular to manufacturing vertical p-i-n photodiodes of a CMOS image sensor, preferably vertical p-i-n photodiodes of a short wave infrared CMOS image sensor.
According to an aspect of the present invention, there is provided a method of integrating a germanium p-i-n photodiode into an image sensor structure, comprising the steps of:
Step S1, providing a germanium donor wafer;
Step S2, implanting hydrogen ions (H +) into the germanium donor wafer to a selected depth to determine the thickness of a germanium transfer layer, wherein the germanium transfer layer is a germanium film to be transferred;
step S3, providing a silicon target wafer;
step S4, bei Dajian is combined with the surfaces of the germanium donor wafer and the silicon target wafer;
Step S5, separating the germanium transfer layer from the germanium donor wafer to obtain a germanium-silicon mixed wafer, namely separating the germanium transfer layer bonded and adhered on the silicon target wafer from the germanium donor wafer by using a thermal technology or a mechanical technology to obtain a mixed wafer formed by the germanium transfer layer and the silicon target wafer;
step S6, the final bonding of the germanium-silicon mixed wafer is completed;
step S7, grinding the surface of the germanium-transferring layer of the germanium-silicon mixed wafer;
S8, implanting boron ions (B +) of doping elements into the germanium transfer layer on the top of the germanium-silicon mixed wafer, so that the part of the germanium transfer layer close to the surface is implanted with boron to form a doped germanium layer, and the rest part close to the silicon target wafer is an undoped germanium layer;
step S9, forming an isolation structure between pixels in the germanium photodiode layer to define a photodiode region;
step S10, turning over the germanium-silicon mixed wafer;
In step S11, a carrier coated with a temporary adhesive is provided.
Wherein, after step S11, the method further comprises the following steps:
step S12, temporarily bonding/adhering one surface of the germanium-silicon mixed wafer with the flowable dielectric material to a carrier through a temporary adhesive;
step S13, removing most of the silicon target wafer by grinding until the bottom 13 of the pixel isolation;
Step S14, depositing a dielectric passivation layer on the surface of the outward side of the residual silicon layer;
step S15, respectively and independently forming metal connection for the residual silicon layer and the doped germanium layer;
In step S16, an alignment mark is formed on the surface of the dielectric passivation layer facing outward.
Wherein, after step S16, the method further comprises the following steps:
step S17, providing a silicon control and readout circuit wafer;
step S18, the surface of the interconnection layer of the silicon control and readout circuit wafer facing the outer side is butted with the surface of the dielectric passivation layer of the germanium photodiode layer temporarily bonded to the carrier, and the alignment of the interconnection layer and the dielectric passivation layer is ensured through the alignment marks on the surface and the surface, so that the metal connection of the germanium photodiode layer is connected with the circuit of the interconnection layer;
Step S19, annealing to finish bonding;
step S20, performing laser bond/debonding and removing the carrier;
step S21, removing the surface dielectric layer by chemical mechanical polishing;
step S22, depositing an anti-reflection layer on the surface formed by the doped germanium layer and the dielectric layer between the grooves;
in step S23, a lens layer is formed on top of the anti-reflection layer.
Preferably, in step S1, the germanium donor wafer is cleaned and dried, and then the surface of the germanium donor wafer is polished using a chemical mechanical polishing process.
More preferably, the step S1 of providing the germanium donor wafer further comprises depositing a plasma enhanced chemical vapor deposited silicon dioxide film on the germanium donor wafer, the silicon dioxide film thickness being between 10nm and 90nm to protect the surface of the germanium donor wafer during the subsequent step S2 of hydrogen ion implantation.
Further, step S1 of providing the germanium donor wafer further comprises depositing a plasma enhanced chemical vapor deposition silicon dioxide film on the germanium donor wafer, the silicon dioxide film having a thickness between 10nm and 90nm to protect the surface of the germanium donor wafer during the subsequent hydrogen ion implantation of step S2, and the silicon dioxide film is removable after the hydrogen ion implantation.
Further, the hydrogen ion implantation in step S2 employs beam line ion implantation or plasma immersion ion implantation.
Preferably, an amorphous germanium layer is deposited on top of the formed germanium transfer layer region.
Preferably, the selective stripping energy placement method employs energy pulse techniques by providing localized energy pulses.
More preferably, hydrogen ions (H +) are implanted into the germanium donor wafer, the implanted hydrogen ions trap electrons to form hydrogen gas, the hydrogen gas forms a layer of microbubbles in the bubbled layer, and the sige mixed wafer is heated and stripped along the cleaved surface.
In addition, the separated germanium donor wafer can be repeatedly used after polishing and cleaning the surface, namely, a piece of germanium donor wafer is repeatedly used as the raw material of the step S2 to generate a germanium transfer layer until the thickness of the germanium transfer layer is thin enough to be used continuously.
Additionally, in the step S6, the final bonding step adopts an annealing bonding step, and the final bonding step lasts for a plurality of hours in a process environment of 400 ℃ or less.
Compared with the prior art, the invention has the following beneficial technical effects:
1. the invention realizes the production and manufacturing process of the short-wave infrared image sensor with high speed and small pixel size by a relatively simpler manufacturing process.
2. The technical scheme of the invention realizes low-cost and CMOS compatible short-wave infrared image sensors (with focal plane arrays) which are manufactured in batches and high in production qualification rate.
3. The image sensor manufactured by the production process has lower dark current and higher sensitivity from visible light to short wave infrared wavelength.
4. The technical scheme of the invention utilizes the organic combination aiming at ion implantation, cleaning, bonding, annealing, stripping, chemical mechanical polishing and the like, so that the production process is relatively simple, the technology is mature, and the method is suitable for industrial mass production.
5. The method for integrating the germanium p-i-n photodiode into the image sensor structure adopts the germanium-silicon layer transfer technology to obtain the high-quality single crystal germanium layer of the photodiode layer, and has higher quality and fewer defects compared with the direct epitaxial growth of the germanium layer on a silicon target wafer.
6. The image sensor manufactured by the method of integrating the germanium p-i-n photodiode into the image sensor structure of the invention is a backside illuminated (BSI) sensor, and a stacked CMOS structure is adopted, namely a silicon control and readout circuit is positioned on the back of a pixel layer, so that the number of incident photons captured in the pixel layer is improved or increased, thereby reducing noise and improving overall performance.
7. The manufacturing flow design of the method for integrating the germanium p-i-n photodiode into the image sensor structure realizes the integration of the vertical photodiode, and the metal contacts of the vertical p-i-n photodiode are only contacted with the p-type region and the n-type region from the back surface, so that the irradiation of incident photons can not be blocked, and the quantity of captured incident photons is ensured.
8. In the method for integrating the germanium p-i-n photodiode into the image sensor structure, the germanium donor wafer can be reused to generate more germanium transfer layers, so that the resource utilization rate is higher, and the manufacturing cost is lower.
Drawings
Fig. 1-17 are schematic flow diagrams of a method of integrating a germanium p-i-n photodiode into an image sensor structure in accordance with the present invention.
The component names indicated by reference numerals in the drawings are as follows:
1. Germanium donor wafer, 2, germanium transfer layer, 3, silicon target wafer, 4, germanium-silicon mixed wafer, 5, doped germanium layer, 6, undoped germanium layer, 7, germanium photodiode layer, 8, isolation trench, 9, inter-trench dielectric layer, 10, surface dielectric layer, 11, carrier, 12, temporary adhesive, 13, bottom of pixel isolation, 14, remaining silicon layer, 15, metal connection, 16, dielectric passivation layer, 17, silicon control and readout circuit wafer, 18, interconnect layer, 19, antireflection layer, 20, filter layer, 21, lens layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Additionally, the scope of the invention should not be limited to the specific structures or components or specific parameters described below.
In the description of the present invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present invention and simplify the description, and do not indicate or imply that the devices or components referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
A method of integrating a germanium p-i-n photodiode into an image sensor structure is provided by implanting hydrogen ions (H +) into a germanium donor wafer to a selected depth to determine a thickness of a germanium transfer layer, separating the germanium transfer layer from the germanium donor wafer by Bei Dajian closing surfaces of the germanium donor wafer and a silicon target wafer to obtain a germanium silicon hybrid wafer, grinding the surface of the germanium transfer layer of the germanium silicon hybrid wafer, implanting boron ions (B +) of doping elements into the germanium transfer layer on top of the germanium silicon hybrid wafer such that a portion of the germanium transfer layer near the surface is implanted with boron to form a doped germanium layer, and forming a pixel-to-pixel isolation structure in the germanium photodiode layer to define a photodiode region. The invention realizes a high-speed, small-pixel-size and CMOS compatible short-wave infrared image sensor (with a focal plane array) with a low-cost and relatively simpler manufacturing process, and is suitable for industrialized mass production.
Referring to fig. 17, the image sensor based on the germanium p-i-n photodiode manufactured by the method of the present invention includes, in order from bottom to top, a silicon control and readout circuitry wafer 17, a dielectric passivation layer 16, a germanium photodiode layer 7, an anti-reflection layer 19, and a lens layer 21. The germanium photodiode layer 7 is a laminated structure and comprises, from bottom to top, a remaining silicon layer 14, an undoped germanium layer 6 and a doped germanium layer 5, wherein the undoped germanium layer 6 is an intrinsic layer, the remaining silicon layer 14 is an n-type region, the doped germanium layer 5 is a p-type region, and in other embodiments, the remaining silicon layer 14 is a p-type region, and the doped germanium layer 5 is an n-type region. The germanium photodiode layer 7 further includes an inter-trench dielectric layer 9 disposed through the stacked structure thereof, and the inter-trench dielectric layer 9 divides the germanium photodiode layer 7 into a plurality of independent pixel regions. In each pixel region, two metal connections 15 are provided on the dielectric passivation layer 16 and the germanium photodiode layer 7 from bottom to top, the first metal connection being connected to the remaining silicon layer 14 and the second metal connection being connected to the doped germanium layer 5. The upper part of the silicon control and readout circuitry wafer 17 is an interconnect layer 18 with circuitry, the circuitry of the interconnect layer 18 being connected to the metal connections 15.
Preferably, there is also a filter layer 20 between the anti-reflection layer 19 and the lens layer 21, which can selectively transmit incident light of a specific wavelength range while absorbing the remaining light.
The method of integrating the germanium p-i-n photodiode into the image sensor structure of the present invention can be divided into two types according to the upper and lower order of the p-type region and the n-type region in the germanium p-i-n photodiode, and it can be understood that the basic process principles of the two types are the same. A method a (referred to as "method a") of integrating a germanium p-i-n photodiode into an image sensor structure will be described in detail with reference to fig. 1 to 17.
In method a, boron doped germanium (p-type region) is on top, doped germanium layer 5 is the p-type region, the dopant element ions implanted into the germanium are boron ions (B +), and the remaining silicon layer 14 is the n-type region. The method A comprises the following steps:
In step S1, a germanium donor wafer 1 is provided. Fig. 1 is a schematic diagram of steps S1 to S2. In a preferred embodiment, the germanium donor wafer 1 is cleaned and dried, and then the surface of the germanium donor wafer 1 is polished, wherein the polishing adopts a chemical mechanical polishing process, the chemical mechanical polishing process comprises polishing the surface of the germanium donor wafer by adopting a polishing liquid with a pH value of a certain value, and the pH value of the polishing liquid is preferably 7-11, more preferably 9. In the grinding process, the grinding progress is controlled by adjusting the flow of the grinding liquid and applying pH value adjusting liquid according to the grinding progress and the flatness of the plane of the germanium donor wafer 1, wherein the pH value adjusting liquid is preferably deionized water. The chemical mechanical polishing equipment for the germanium donor wafer comprises a polishing turntable, a polishing pad, a polishing liquid nozzle and a pH value adjusting liquid nozzle, wherein the polishing turntable is used for fixing the germanium donor wafer to be polished and providing rotary power for the germanium donor wafer to be polished, the polishing pad is used for mechanically removing the surface layer of the germanium donor wafer to be polished in relative motion with the germanium donor wafer to be polished, the polishing liquid nozzle is arranged above the polishing pad and used for injecting polishing liquid with a certain pH value onto the polishing pad, the pH value adjusting liquid nozzle is arranged close to the polishing liquid nozzle and used for injecting the pH value adjusting liquid onto the polishing pad and mixing the polishing liquid with the certain pH value onto the polishing pad to form polishing liquid with a second pH value, and the pH value adjusting liquid nozzle is also provided with a flow controller which is used for adjusting the flow of the pH value adjusting liquid to adjust the second pH value to a target pH value. And the pH value adjusting liquid nozzle and the grinding liquid nozzle are respectively provided with a flow controller for adjusting the flow of the pH value adjusting liquid and the flow of the grinding liquid so as to adjust the second pH value to the target pH value. The chemical mechanical polishing device further comprises a pH value detector for detecting the pH value of the polishing liquid on the polishing pad.
Step S1 provides the germanium donor wafer 1 further comprising depositing a layer of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon dioxide (SiO 2) film on the germanium donor wafer 1, the silicon dioxide (SiO 2) film having a thickness between 10nm and 90nm (nanometers) to protect the surface of the germanium donor wafer 1 during the hydrogen ion implantation of the subsequent step (step S2), and the silicon dioxide film being removable after the hydrogen ion implantation. The masking film may also be selected from silicon nitride, al 2O3, or photoresist.
In step S2, hydrogen ions (H +) are implanted into the germanium donor wafer 1 to a selected depth to determine the thickness of the germanium transfer layer 2 (i.e., the germanium film to be transferred). As shown in fig. 2.
In some embodiments, hydrogen ion implantation may be performed using beam line ion implantation or plasma immersion ion implantation, e.g., at a dose ranging from 1X 10 15 atoms/cm 2 ~ 1×1018 atoms/cm 2 (preferably >10 16 atoms/cm 2), at an energy ranging from 1keV to 1MeV (typically about 50 keV), at a temperature ranging from room temperature (e.g., 25 degrees Celsius) to 600 degrees Celsius (preferably <400 degrees Celsius) to minimize escape of implanted particles by diffusion, and at a depth precision selected from + -0.03 microns to + -0.05 microns.
Alternatively, an amorphous germanium (a-Ge) layer may be deposited (e.g., by Physical Vapor Deposition (PVD)) on top of the formed germanium transfer layer 2 region. Fig. 2 is a schematic diagram showing the state after step S2.
Step S3, providing a silicon target wafer 3 (n-type), preferably polishing the surface of the silicon target wafer, wherein the polishing process or equipment adopts the chemical mechanical polishing process or equipment in step S1 or adopts the chemical mechanical polishing process or equipment similar to that in step S1. Fig. 3 is a schematic diagram illustrating steps S3 to S4.
If an amorphous germanium layer is deposited in step S2, it is further preferred that an amorphous germanium layer is also deposited (e.g. by physical vapor deposition) on the surface of the silicon target wafer 3, such that during subsequent steps S5 and S6 the combined amorphous germanium layer will be converted to crystalline germanium (c-Ge), thereby facilitating the bonding between the germanium donor wafer 1 and the silicon target wafer 3.
In step S4, beta bonds the surfaces of the germanium donor wafer 1 and the silicon target wafer 3. Wherein Bei Dajian is subjected to a cleaning step before proceeding to remove the oxide on the surface. Ultrasonic cleaning is performed on the surface of the germanium wafer by adopting acetone, methanol/ethanol and deionized water, in a preferred embodiment, further cleaning is performed by adopting deionized water and H 2O2 according to the proportion of (15-30) and diluting liquid according to the proportion of (20:1), then diluting by adopting deionized water and HF according to the proportion of (30-70) and diluting according to the proportion of (1), preferably diluting according to the proportion of (50:1), and finally cleaning again by adopting diluted H 2O2 according to the proportion of (15-30) and diluting according to the proportion of (1), preferably diluting according to the proportion of (20:1). In a preferred embodiment, the surface of the silicon wafer is cleaned in a tandem sequence using an RCA-I solution and an RCA-II solution, then cleaned using an H 2O2-H2SO4 cleaning solution, and after cleaning, the remaining liquid or particles on the wafer surface are removed using a dryer. In other embodiments, the wafer may be immersed in hydrofluoric acid instead of the cleaning process described above.
Bei Dajian the bonding process is also known as self-bonding process, etc., and includes one or two methods, specifically, for example:
in the first method, the low-temperature bonding process comprises a low-temperature heat treatment step, and clean and/or activated surfaces are pressed together under moderate pressure, preferably 0.5-2.0 MPa, so as to ensure that injected particles (hydrogen ions or microbubbles) cannot break or diffuse or exhaust. This weak bonding is caused by electrostatic interactions (van der waals forces).
And secondly, plasma clean activation, namely, striking a silicon target wafer 3 by adopting plasmas from Ar and N 2、NH3、Ne、H2O、O2, enabling the surface of the wafer to be activated by the plasmas (suspension bonds are generated on the surface of the wafer), then, attaching the surface of the activated silicon target wafer 3 to the surface of a germanium donor wafer 1, and applying pressure to the wafer to enable the wafer to be self-bonded on a layer-to-layer interface.
In step S5, the germanium-transfer layer 2 (bonded to the silicon target wafer 3) is separated (i.e., peeled off using heat, mechanical or other suitable technique) from the germanium donor wafer 1 to obtain a germanium-silicon hybrid wafer 4 (i.e., a hybrid wafer composed of the germanium-transfer layer 2 and the silicon target wafer 3). Fig. 4 is a schematic diagram of step S5.
The stripping method, such as a selective stripping energy placement step (SELECTIVE CLEAVE ENERGY PLACEMENT STEP), specifically employs an energy pulse technique, where the energy pulse is generated by providing a local (small-scale) energy pulse, such as a heat source (e.g., laser, heat lamp), a cold source, and a mechanical source, to effect, for example, torsional stripping, specifically heating (e.g., heating with a heat source of about 350 degrees celsius) or cooling or differentially heating or differentially cooling one side of the substrate (germanium donor wafer 1 or silicon target wafer 4). In another embodiment, the delamination method further includes an ion implantation bubble separation step (implantation blister-separation step), specifically, hydrogen ions (H +) are implanted into the germanium donor wafer 1, electrons are trapped by the implanted hydrogen ions to form hydrogen gas, the hydrogen gas forms a microbubble layer in the bubbling layer, the microbubble layer is parallel to the cleavage plane (cleavage plane of the crystal), the sige mixed wafer 4 is heated and delaminated along the cleavage plane, wherein the cleaning step and the self-bonding process can refer to the process in Bei Dajian.
Alternatively, the separated germanium donor wafer 1 may be repeatedly used after polishing (chemical mechanical polishing (CMP)) the surface and cleaning the surface, i.e., a piece of germanium donor wafer 1 is repeatedly used as the raw material for step S2 to produce the germanium transfer layer 2 until the thickness thereof is so thin that it cannot be used further.
And S6, finishing final bonding of the germanium-silicon mixed wafer 4.
The final bonding step employs, for example, a bonding step method one, an annealing bonding step, for several hours in a process environment of less than or equal to 400 degrees celsius, preferably for 3 hours in a process environment of 300 degrees celsius. Bonding step two, a bonding step of applying a voltage to establish a current through the hybrid wafer, limiting crystal defects introduced in the wafer, the current heating and causing bonding between the wafers, preferably bonding by localized heating of the interface (increasing series resistance).
In step S7, the surface of the germanium-transfer layer 2 of the sige mixed wafer 4 is polished. Wherein, for example, chemical mechanical grinding is adopted, specifically, the slurry contains mild grinding agents and oxidizing agents (mixed in deionized water), wherein, the grinding agents are borosilicate glass, titanium dioxide, titanium nitride, aluminum oxide, aluminum trioxide, ferric nitrate, cerium oxide, silicon dioxide (colloidal silicon dioxide or gas-phase (micro-powder) silicon dioxide), silicon nitride, silicon carbide, graphite and diamond, and the oxidizing agents are H 2O2、KIO3 and ferric nitrate.
Optionally, after polishing, a layer of plasma-enhanced chemical vapor deposited silicon dioxide film may be deposited on the germanium transfer layer 2 on top of the germanium-silicon hybrid wafer 4 to protect the surface of the germanium transfer layer 2 during subsequent boron ion implantation, and the silicon dioxide film may be removed after boron ion implantation.
In step S8, boron ions (B +) of the doping element ions are implanted into the germanium-transfer layer 2 on top of the sige mixed wafer 4, so that the portion of the germanium-transfer layer 2 near the surface is implanted with boron to form a doped germanium layer 5 (p-type region), and the remaining portion (portion near the si target wafer 3) is an undoped germanium layer 6 (boron ions cannot reach and therefore no boron is present and is an intrinsic region). An anneal is then performed to activate the dopants. Fig. 5 is a schematic diagram of step S8. Wherein the dopant, also referred to as dopant, implant, etc., is an implanted boron atom.
Fig. 6 and 7 are schematic diagrams of step S9, fig. 6 is a schematic diagram of the state after step S9.1 is completed, and fig. 7 is a schematic diagram of the state after step S9.3 is completed. Note that fig. 7 to 17 are enlarged views of a single pixel region, for example, a portion shown in fig. 6 a.
In step S9, an isolation structure is formed between pixels in the germanium photodiode layer 7 to define a photodiode region (i.e., a photodiode array, i.e., a pixel region). As shown in fig. 6, the germanium photodiode layer 7 refers to a doped germanium layer 5, an undoped germanium layer 6, and a portion of the silicon target wafer 3, that is, a portion corresponding to the germanium p-i-n photodiode layer formed in a later step, which are sequentially connected.
Step S9 further includes:
Step S9.1, forming an isolation pattern and forming an isolation trench 8 by etching to define (divide) each pixel region, for example, if the shape of the pixel to be formed is square, the isolation pattern is similar to a square grid;
Step S9.2, filling the isolation trenches 8 with a flowable dielectric material (e.g. polyimide) to form inter-trench dielectric layers 9;
In step S9.3, the flowable dielectric material is overfilled so that it overflows after filling the isolation trench 8, covering the pixel region, forming the surface dielectric layer 10.
Fig. 8 is a schematic diagram of steps S10 to S11.
Step S10, turning over the germanium-silicon mixed wafer 4.
In step S11, a carrier 11 coated with a temporary adhesive 12 is provided. The temporary bonding agent 12 (temporary bonding adhesive) may be bonded by bonding or adhesive means using known techniques.
Fig. 9 is a schematic diagram showing the state after the completion of step S12.
In step S12, the sige mixed wafer 4 (the side with the flowable dielectric material) is temporarily bonded/adhered to the carrier 11 by the temporary adhesive 12.
Fig. 10 is a schematic diagram showing the state after the completion of step S13.
In step S13, most of the silicon target wafer 3 (n-type) is removed by polishing (e.g., chemical mechanical polishing or etching (e.g., wet etching) or other suitable technique) until the bottom 13 of the pixel isolation. Thus, a remaining silicon layer 14 (n-type region) is formed (left) on top of the undoped germanium layer 6, and the remaining silicon layer 14, the undoped germanium layer 6 and the doped germanium layer 5, which are connected in sequence, together constitute a germanium p-i-n photodiode layer (i.e., the germanium photodiode layer 7). The bottom 13 of the pixel isolation refers to the level corresponding to the end of the inter-trench dielectric layer 9 away from the surface dielectric layer 10, i.e. the level corresponding to the polished surface of the remaining silicon layer 14, which is reserved according to the requirements/processes.
Fig. 11 is a schematic diagram showing the state after the completion of step S14.
In step S14, a dielectric passivation layer 16 is deposited on the outward facing surface of the remaining silicon layer 14.
Fig. 12 is a schematic diagram showing the state after completion of step S15.
In step S15, metal connections 15 are formed separately for the remaining silicon layer 14 (n-type region) and the doped germanium layer 5 (p-type region).
Step S15 further includes:
In step S15.1, metal connection patterns are formed and etched to form vias to the remaining silicon layer 14 (n-type region) and the doped germanium layer 5 (p-type region). Barrier Metal (BM) and copper (Cu) seed are formed on the sidewalls of the via by Physical Vapor Deposition (PVD), and the via is filled by copper electrochemical deposition to form metal connection 15.
In step S15.2, the surface is polished (e.g., cmp), excess copper is removed, and the copper pad and dielectric field are exposed, so that the metal connection 15 is level with the dielectric passivation layer 16. Wherein the dielectric passivation layer 16 may be thinned after chemical mechanical polishing.
In step S16, alignment marks (ALIGNMENT MARKS) are formed on the outward facing surface of the dielectric passivation layer 16 (by any suitable technique).
Fig. 13 is a schematic diagram of steps S17 to S18.
In step S17, a silicon control and readout circuit wafer 17 is provided.
The silicon control and readout circuitry wafer 17 has therein the control, readout and/or other suitable circuitry for the p-i-n photodiode array layer (i.e., the germanium photodiode layer 7), the surface adjacent to the outside is an interconnect layer 18 with circuitry, and the surface of the interconnect layer 18 towards the outside is a surface formed after chemical mechanical polishing of copper and barrier metal, i.e., the surface is exposed with the circuit metal contacts (copper pads).
And, step S17 further includes:
in step S17.1, alignment marks are formed (by any suitable technique) on the outwardly facing surface of the interconnect layer 18. This alignment mark matches the alignment mark formed on the surface of the dielectric passivation layer 16 in step S16, thereby achieving an auxiliary alignment effect at the time of subsequent combination.
In step S18, the outward facing surface of the interconnect layer 18 of the silicon control and readout circuitry wafer 17 is butted against the outward facing surface of the dielectric passivation layer 16 of the germanium photodiode layer 7 (temporarily bonded to the carrier 11), with alignment marks on both ensuring alignment, so that the metal connections 15 of the germanium photodiode layer 7 are connected to the circuitry of the interconnect layer 18. And bonding between the two is performed, for example, hybrid bonding (copper-copper bonding and oxide-oxide bonding). The copper-copper bonding process is to connect the upper copper pad and the lower copper pad (the interface of the two copper portions where the metal connection 15 and the circuit of the interconnect layer 18 interface) by copper interdiffusion during copper grain growth.
The alignment mark is also called an alignment mark in the prior art. In order for the device to be operable, the metal connections 15 of the germanium photodiode layer 7 and the circuitry of the interconnect layer 18 of the silicon control and readout circuitry wafer 17 must be aligned with each other (in electrical communication). For this purpose, at least one set of alignment marks is provided, which are high-precision features that are used as references in the combined positioning. The alignment marks may be provided according to the prior art, and will not be described in detail herein.
Fig. 14 is a schematic diagram showing the state after completion of step S18.
In step S19, annealing is performed to complete bonding. The oxide-oxide bonding process is such that, upon annealing, the upper and lower dielectric fields (connecting interconnect layer 18 and dielectric passivation layer 16) are connected by a dehydration condensation reaction.
In step S20, laser bond/debonding is performed to remove the carrier 11.
Fig. 15 is a schematic diagram showing the state after completion of step S20.
In step S21, the surface dielectric layer 10 is removed by polishing (by, for example, chemical mechanical polishing or other suitable technique). That is, the flowable dielectric material (the inter-trench dielectric layer 9 is still present) is removed from the surface portion of the pixel region, leaving the doped germanium layer 5 exposed at the surface.
Fig. 16 is a schematic diagram showing the state after completion of step S21.
In step S22, an anti-reflection layer 19 is deposited on the surface (the surface formed by the germanium doped layer 5 and the inter-trench dielectric layer 9).
In step S23, a lens layer 21 is formed on top of the anti-reflection layer 19.
Preferably, a filter layer 20 is also formed between the top of the anti-reflection layer 19 and the lens layer 21.
Fig. 17 is a schematic diagram of the state after the completion of step S22 and step S23 in the preferred embodiment, namely, a schematic diagram of the structure of the final product.
In method B, phosphorus doped germanium (n-type region) is on top, doped germanium layer 5 is an n-type region, dopant element ions implanted into the germanium are phosphorus ions (P +), and the remaining silicon layer 14 is a P-type region.
The difference from the method a is that the silicon target wafer 3 provided in the step S3 is P-type, so that the remaining silicon layer 14 is P-type region, the doped element ion implanted in the step S8 is phosphorus ion (P +), the formed doped germanium layer 5 is n-type region, and the rest of the processes and operation procedures are the same as those of the method a.
As is well known in the art, doping a group III element (e.g., boron) with a group IV element (e.g., germanium) forms a p-type semiconductor, and doping a group V element (e.g., phosphorus) with a group IV element (e.g., germanium) forms an n-type semiconductor. It is therefore apparent that these similar variant methods are obtained by the method a of the invention described in detail above.
In summary, the present invention realizes a high-speed, small pixel size, CMOS compatible short wave infrared image sensor (with focal plane array) with a low cost, relatively simpler manufacturing process, suitable for industrial mass production. Meanwhile, the image sensor manufactured by the method has lower dark current and higher sensitivity from visible light to short wave infrared wavelength. In addition, in the method of the invention, the germanium donor wafer can be recycled to generate more germanium transfer layers, so that the resource utilization rate is higher and the manufacturing cost is lower.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Claims (12)
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