CN114709255A - Heterojunction-based high-power-density tunneling semiconductor device and manufacturing process thereof - Google Patents

Abstract

The invention discloses a high power density tunneling semiconductor device based on a heterojunction and a manufacturing process thereof. The cell structure of the device comprises: an N+ substrate, a drain metal is arranged under it, and an N-drift region is arranged on it; A pair of trenches are symmetrically arranged in the N-drift region, a P+ region is arranged at the bottom of the trench, a graphene source region is arranged in the trench, a source metal is arranged on the graphene source region, and a graphene source is arranged on the N-drift region. The source region is partially overlapped with a gate dielectric layer, the gate dielectric layer is provided with a polysilicon gate, the polysilicon gate is provided with a passivation layer, and the graphene source region and the N-drift region form a heterojunction. The device structure of the present invention has low requirements on the injection process, small cell size, and large number of cells per unit area, which greatly improves the power density of the device, effectively reduces the specific on-resistance and sub-threshold swing of the device, simplifies the manufacturing process, and reduces the device cost. When the device is reverse biased and withstand voltage, the P+ region transfers the electric field peak from the boundary of the heterojunction to the boundary of the PN junction, which improves the avalanche capability of the device and increases the breakdown voltage.

Description

Heterojunction-based high power density tunneling semiconductor device and its fabrication process

technical field

The invention mainly relates to the field of high-voltage power semiconductor devices, in particular, to a high-power density tunneling semiconductor device based on a heterojunction and a manufacturing process thereof, which are suitable for automotive electronics, rail transit, photovoltaic inverter, aerospace, aviation, Oil exploration, nuclear energy, radar and communications and other application fields where extreme environments such as high temperature, high frequency, high power, and strong radiation coexist.

Background technique

Power semiconductor devices play a pivotal role in the power electronics industry and are widely used in automobiles, household appliances, high-speed rail and power grids. However, traditional power devices have many shortcomings, such as: large cell size, large on-resistance, high interface state density, complex manufacturing process and doping process will damage the semiconductor surface.

The conduction band and valence band of graphene material are symmetrical, and only intersect at the vertex of the Brillouin zone, that is, at a point on the Fermi surface, with an obvious controllable electronic band gap. According to the characteristics of the graphene material's energy band symmetry, doping or applying an external field can break the energy band symmetry, thereby opening the band gap and controlling the size of the band gap. Graphene material has the characteristics of semiconductor energy band and high electrical conductivity of metal. The characteristics of graphene materials, such as high mobility, high thermal conductivity, strong high temperature stability, and large-area fabrication, meet the needs of power semiconductor devices.

1 is a conventional silicon carbide power semiconductor device, including: an N+ type substrate 1, a drain metal 10 is connected to one side of the N+ type substrate 1, and a drain metal 10 is connected to the other side of the N+ type substrate 1 N-type drift region 2, a pair of P-type base regions 3, N+-type source region 5 and P+-type body contact region 4 are symmetrically arranged in the N-type drift region 2, and a gate is arranged on the surface of the N-type drift region 2 The oxide layer 8 is provided with a polysilicon gate 9 on the surface of the gate oxide layer 8, a passivation layer 6 is provided above the polysilicon gate 9, and a source metal 7 is connected to the N+ type source region 5 and the P+ type body contact region 4. The working principle of conventional silicon carbide power semiconductor devices is that when a sufficiently large positive voltage is applied to the polysilicon gate, an inversion channel will be generated at the interface between the P-type base region 3 and the gate oxide layer 8, and electrons can pass through the channel from N+ Type source region 5 is implanted into N-type drift region 2 . The P-type base region 3 and the N+-type source region 5 need doping to be formed. However, the cell size of the SiC device is limited by the doping process and the width of the JFET region, resulting in a cell width limit of 4-6um, which cannot be further reduced. It affects the cell density of the device and the forward current capability of the device. In addition, the ion implantation process of the silicon carbide material will also cause damage to the surface of the N-type drift region 2, resulting in a large number of interface state traps on the surface of the N-type drift region 2, which makes the effective mobility of the inversion channel carriers small and leads to The on-resistance is high. At the same time, traditional semiconductor devices are based on the thermal carrier injection mechanism, and the sub-threshold swing can only reach a minimum of 60mV/decade at room temperature. Therefore, it is urgent to propose a new type of power device with high channel electron mobility and high power density.

SUMMARY OF THE INVENTION

In view of the above problems, the present invention proposes a high power density tunneling semiconductor device based on a heterojunction and a manufacturing process thereof. On the basis of keeping the breakdown voltage unchanged, the structure uses graphene and silicon carbide substrates to form heterojunctions. Quality knot. When a positive pressure is applied to the gate, the Fermi level of graphene moves up into the conduction band, and at the same time, the electron concentration in the N-type drift region increases to form an accumulation layer. At this time, the width of the heterojunction barrier becomes narrow, and band-band tunneling occurs. The electrons in the valence band of graphene tunnel through the heterojunction barrier into the conduction band of the N-type drift region.

At the same time, the cell size of the device of the present invention is smaller than that of the conventional silicon carbide power device cell, which greatly increases the number of cells per unit area, effectively reduces the specific on-resistance of the device, improves the power density of the device, and reduces the The device subthreshold swing is greatly simplified, the manufacturing process is greatly simplified, and the device cost is reduced.

The present invention adopts the following technical solutions: a high power density tunneling semiconductor device based on a heterojunction and a manufacturing process thereof, wherein the high power density tunneling power semiconductor device based on a heterojunction is an axisymmetric structure,

It includes an N+ substrate, a drain metal is arranged under it, and an N-drift region is arranged on it; it is characterized in that a pair of graphene source regions arranged at intervals are arranged above the N-drift region, and a source region is arranged on the graphene source region pole metal, the N-drift region is provided with a gate dielectric layer partially overlapping with the graphene source region, the gate dielectric layer is provided with a polysilicon gate, the polysilicon gate is provided with a passivation layer, and the polysilicon gate and the gate dielectric layer are flush, The polysilicon gate and the source metal are spaced apart, a heterojunction is formed at the contact between the graphene source region and the N-drift region, and a triple contact surface is formed between the graphene source region, the N-type drift region and the gate dielectric layer. The tunneling effect occurs at the interface.

Further, there are two spaced grooves on the upper surface of the N-type drift region, the graphene source region is set in the grooves, and the P+ type region is set in the N-type drift region below the graphene source region.

Further, the graphene source region is arranged on the upper surface of the N-type drift region, and the P+-type region is arranged in the N-type drift region below the graphene source region.

Further, the graphene source region is disposed on the upper surface of the N-type drift region.

Further, there are two spaced grooves on the upper surface of the N-type drift region, and the graphene source region is arranged in the grooves.

Further, a P+ type region is arranged in the N-type drift region below the graphene source region, a second P+ type region is arranged in the N-type drift region under the gate dielectric layer, and the second P+ type region is connected to the graphene source. There is a certain distance between the districts.

Further, the N+ type substrate and N- type drift region are not limited by materials, and silicon carbide, gallium oxide, silicon, diamond or other materials that can form heterojunction tunneling power semiconductor device substrates and drift regions can be used. , the doping concentrations of the N+ type substrate and the N- type drift region are also not limited.

Further, the graphene source region is not limited by materials, and graphene, molybdenum disulfide, polysilicon, metal or other materials that can form the source region of a heterojunction tunneling power semiconductor device can be used.

Further, the thickness of the gate dielectric layer is not limited, and the gate dielectric layer is not limited by materials. Silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, or other gate dielectrics that can form heterojunction tunneling power semiconductor devices can be used. layer material.

A method for manufacturing a high power density tunneling semiconductor device based on a heterojunction, comprising the steps of:

Step 1: attach silicon carbide on the surface of the N+ type substrate to form an N- type drift region;

Step 2: using an etching process to form a trench on the surface of the N-type drift region;

Step 3: use a doping process to form a P+ type shielding layer at the bottom of the trench;

Step 4: forming a layer of graphene source region on the bottom of the trench;

Step 5: using a deposition process to form a gate dielectric layer on the upper surface of the N-type drift region;

Step 6: using a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer and form a polysilicon gate;

Step 7: forming an isolation passivation layer over the polysilicon gate by a deposition process;

Step 8: Finally, source metal is formed on the upper surface of the graphene source region, and drain metal is formed on the other surface of the N+ type substrate.

The source electrode of the device of the present invention adopts graphene material, and a voltage is applied through the gate to obtain lower sub-threshold swing and higher on-state current characteristics.

Principle: When a large enough positive voltage is applied to the gate, a large number of electrons will also accumulate at the interface between the N-type drift region and the gate oxide layer, which will reduce the resistance of the channel region and reduce the N-type drift under the gate. The reduction of the energy band of the N-type drift region leads to the narrowing of the heterojunction barrier width, and it is easier for the valence band electrons of the graphene source region to pass through the forbidden band to the conduction band of the N-type drift region. The band tunneling mechanism enables the power semiconductor device to generate the I-V characteristic shown in FIG. 3 in the open state, where the current path is 11 and the depletion layer distribution is shown as the dotted line 10 .

When a negative voltage is applied to the gate, the electrons in the channel region are repelled and the electron concentration decreases, raising the energy band of the N-drift region under the gate. And the conduction band and valence band gap of graphene are opened, and the width of the heterojunction barrier becomes larger, which greatly inhibits the occurrence of tunneling effect and bipolar effect, so that the power semiconductor device has a smaller leakage current in the off state. . At this time, the device is in the reverse withstand voltage state, and the homogenous PN junction formed by the P+ type region and the N- type drift region is in the reverse withstand voltage state as shown in FIG.

Compared with the prior art, the present invention has the following advantages:

(1) The source electrode of the device of the present invention adopts graphene material, and the conduction band and valence band of the graphene material are symmetrical, and only intersect at the vertex of the Brillouin zone, that is, intersect at a point on the Fermi surface, with obvious controllable electrons Bandgap. According to the characteristics of graphene's energy band symmetry, doping or applying an external electric field can destroy the energy band symmetry, thereby opening the band gap, and the graphene work function can be adjusted. Therefore, graphene has semiconductor energy band characteristics. When zero voltage is applied to the gate, the device is in an off state, and the intrinsic carrier concentration of graphene is low, showing a high resistance state. When positive pressure is applied to the gate, the Fermi level of graphene moves up and enters the conduction band, the height of the heterojunction barrier decreases, the width of the heterojunction barrier becomes narrower, and the band-band tunneling effect occurs, resulting in a forward tunneling effect. wear current.

(2) The graphene material used in the source electrode of the device of the present invention has a low doping concentration and is almost in an intrinsic state. When the intrinsic carrier concentration of graphene is low, it exhibits a high resistance state, and the leakage current is small when the reverse withstand voltage is present.

(3) The thermal conductivity of the graphene material used in the source electrode of the device of the present invention is six times that of silicon carbide and the thickness is extremely thin, so the device of the present invention has better heat dissipation characteristics than traditional power devices.

(4) When a sufficiently large positive voltage is applied to the gate, a large amount of electrons will accumulate at the interface between the N-type drift region and the gate oxide layer of the device of the present invention, which reduces the resistance of the channel region, and because the graphene channel The carrier mobility is 200000 cm ² /(V·s) in an ideal state, so the channel resistance is extremely low, so that the device of the present invention has excellent forward IV characteristics in the open state.

(5) In the freewheeling state, the device of the present invention adopts the heterojunction formed by the graphene material and the N-drift region to replace the PN homojunction formed by the ion implantation doping process of the conventional silicon carbide power semiconductor device. The heterojunction barrier is lower, the freewheeling current is larger, and the work function of graphene can be changed by doping and other means to obtain a heterojunction diode with adjustable heterojunction barrier, which further exerts the freewheeling state of the device of the present invention. down advantage.

(6) The source electrode of the device of the present invention adopts the graphene material, the graphene material and the N-drift region form a heterojunction, the tunneling effect occurs under the control of the gate voltage, and the channel is the graphene source electrode and the N-type drift. Region contact and triple contact of the gate insulating layer. For conventional silicon carbide MOS, due to the limitation of the characteristics of silicon carbide material, only a P-type base region and an N+-type source electrode can be formed through an ion implantation doping process, and then a conductive channel of the inversion layer is formed by gate control. However, the ion implantation doping process will damage the surface of the N-type drift region, resulting in low electron mobility. Compared with conventional power semiconductor devices, the channel of the device of the present invention is formed by graphene and a high-concentration electron accumulation region, which does not require an ion implantation process to form an electron inversion layer conductive channel, and does not affect the channel region. The surface of the N-drift region is damaged, and the manufacturing process is greatly simplified, the device cost is reduced, and the number of cells per unit area is greatly increased.

(7) The graphene source region, the N-type region drift region and the gate dielectric layer are in contact to form a triple contact surface, and a tunneling effect occurs at the triple contact surface, the channel density is large, and the current capability is strong.

(8) The device of the present invention is compatible with the traditional device process, and the graphene can be fabricated in a large area, and the process difficulty is small.

(9) The device of the present invention is provided with a P+-type region under the graphene source region, the P+-type region and the N-type drift region form a PN junction, and the graphene source region and the N-type drift region form a heterojunction. When the device is reverse-biased withstanding voltage, the peak of the electric field without the P+-type region is at the boundary of the heterojunction formed by the graphene source region and the N--type drift region, the reverse leakage current is large, and the breakdown voltage of the device is small. When there is a P+-type region, the electric field peak is at the boundary of the PN junction formed by the P+-type region and the N--type drift region, which improves the avalanche capability of the device, reduces the reverse bias leakage current, and increases the device breakdown voltage.

Description of drawings

1 is a front view of a conventional silicon carbide power semiconductor device structure;

2 is a front view of a semiconductor device cell according to the first embodiment of the present invention;

3 is a schematic diagram of a forward current path according to the first embodiment of the present invention;

FIG. 4 is a schematic diagram of a reverse state depletion layer distribution according to the first embodiment of the present invention;

5 is a front view of a semiconductor device cell according to a second embodiment of the present invention;

6 is a front view of a semiconductor device cell according to a third embodiment of the present invention;

7 is a front view of a semiconductor device cell according to a fourth embodiment of the present invention;

8 is a front view of a semiconductor device cell according to a fifth embodiment of the present invention.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings.

Example 1:

Referring to FIG. 2 , a high power density tunneling semiconductor device based on a heterojunction, the high power density tunneling power semiconductor device based on a heterojunction is an axisymmetric structure, comprising: an N+ type substrate 1 , in the N+ type A drain metal 8 is connected to the lower surface of the substrate 1, an N-type drift region 2 is arranged on the upper surface of the N+ type substrate 1, and a pair of P+ type regions 9 are arranged in the N-type drift region 2. A pair of graphene source regions 3 are arranged on the upper surface of the drift region 2, a source metal 4 is symmetrically arranged on the upper surface of the graphene source region 3, and a gate dielectric layer 5 is arranged on the upper surfaces of the N-type drift region 2 and the graphene source region 3, A polysilicon gate 6 is provided on the upper surface of the gate dielectric layer 5 , and a passivation layer 7 is provided on the upper surface of the polysilicon gate 6 . The upper surface of the N-type drift region 2 is grooved so that the N-type drift region 2 is divided into two parts, the N-type drift region 2.1 and the N-type drift region 2.2, at the bottom of the groove, that is, the upper surface of the N-type drift region 2.1. A pair of P+-type regions 9 are arranged, and a pair of graphene source regions 3 are symmetrically arranged in the groove on the upper surface of the N-type drift region 2. There is a certain distance between the pair of graphene source regions 3, and the N-type drift region 2.2 There is a gate dielectric layer 5 partially overlapping with the graphene source region 3, the polysilicon gate 6 and the gate dielectric layer 5 are flush, there is a certain distance between the polysilicon gate 6 and the source metal 4, and the graphene source region 3 and N A heterojunction formed at the contact surface of the -type drift region 2 .

The present invention adopts the following method to prepare:

Step 1: take an N+ type substrate 1, and attach silicon carbide on one surface of the N+ type substrate 1 to form an N- type drift region 2;

Step 2: using an etching process to form a trench on the surface of the N-type drift region 2;

Step 3: using a doping process to form a P+ type shielding layer 9 at the bottom of the trench;

Step 4: forming a layer of graphene source region 3 on the bottom of the trench;

Step 5: using a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;

Step 6: using a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;

Step 7: forming an isolation passivation layer 7 on the polysilicon gate 6 by a deposition process; finally, forming a source metal 4 on the upper surface of the graphene source region 3, and forming a drain metal 8 on the other surface of the N+ type substrate 1 .

In this structure, the P+ type region and the N-type drift region form a PN junction, and the graphene source region and the N-type drift region form a heterojunction. On the basis of keeping the breakdown voltage unchanged, the area of the heterojunction is increased by the grooving process. When a positive pressure is applied to the gate, the graphene Fermi level moves up into the conduction band, and the electron concentration in the N-type drift region increases to form an accumulation layer. At this time, the width of the heterojunction barrier becomes narrower. The band-band tunneling effect occurs at the triple contact interface of the N-type region, the drift region and the gate dielectric layer, and the electrons in the graphene valence band tunnel through the heterojunction barrier and enter the conduction band of the N-type drift region. form a current. The current path 11 is shown in FIG. 3 , and the depletion layer 10 is under the graphene and does not affect the current path 11 . When the device is reverse-biased withstanding voltage, the peak of the electric field without the P+-type region is located at the boundary of the heterojunction formed by the graphene source region and the N--type drift region, the reverse leakage current is large, and the device breakdown voltage is small. Referring to FIG. 4, when there is a P+ type region, the depletion layer 10 completely covers the graphene source region 3, shielding the electric field at the interface of the heterojunction, and the electric field peak is transferred to the PN formed by the P+ type region and the N- type drift region. At the junction boundary, the reverse bias leakage current is reduced, the avalanche capability of the device is improved, and the breakdown voltage of the device is increased. At the same time, due to the simple doping process and small doping area of the device of the present invention, the cell size of the device of the present invention is not limited by the doping process and the JFET region, so the cell size of the device of the present invention is much smaller than the conventional silicon carbide power device. , which greatly increases the number of cells per unit area, effectively reduces the specific on-resistance of the device, improves the power density of the device, reduces the subthreshold swing of the device, greatly simplifies the manufacturing process, and reduces the cost of the device.

Example 2:

Referring to FIG. 5 , a high power density tunneling semiconductor device based on a heterojunction, the high power density tunneling power semiconductor device based on a heterojunction is an axisymmetric structure, comprising: an N+ type substrate 1 , in an N+ type A drain metal 8 is connected to the lower surface of the substrate 1, an N-type drift region 2 is arranged on the upper surface of the N+ type substrate 1, and a pair of P+ type regions 9 are arranged in the upper surface of the N-type drift region 2, A pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2 , a source metal 4 is arranged symmetrically on the upper surface of the graphene source region 3 , and the upper surfaces of the N-type drift region 2 and the graphene source region 3 are arranged symmetrically. There is a gate dielectric layer 5 , a polysilicon gate 6 is provided on the upper surface of the gate dielectric layer 5 , and a passivation layer 7 is provided above the polysilicon gate 6 . A pair of P+-type regions 9 are arranged on the upper surface of the N-type drift region 2, a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2, and there is a certain distance between the pair of graphene source regions 3, The N-type drift region 2 is provided with a gate dielectric 5 partially overlapping the graphene source region 3, the polysilicon gate 6 is flush with the gate dielectric layer 5, and there is a certain distance between the polysilicon gate 6 and the source metal 4, and the graphene A heterojunction is formed at the contact surface between the source region 3 and the N-type drift region 2 .

The present invention adopts the following method to prepare:

Step 1: take an N+ type substrate 1, and attach silicon carbide on the other surface of the N+ type substrate 1 to form an N- type drift region 2;

Step 2: using a doping process to form a P+ type shielding layer 9 in the N- type drift region 2;

Step 3: forming a layer of graphene source region 3 on the N-type drift region 2;

Step 4: using a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;

Step 5: use a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;

Step 6: forming an isolation passivation layer 7 on the polysilicon gate 6 by a deposition process; finally, forming a source metal 4 on the upper surface of the graphene source region 3, and forming a drain metal 8 on the other surface of the N+ type substrate 1 .

On the basis of keeping the breakdown voltage unchanged, the structure uses graphene and silicon carbide substrate to form a heterojunction. When a positive pressure is applied to the gate, the Fermi level of graphene moves up and enters the conduction band. At the same time, N- The electron concentration in the N-type drift region increases to form an accumulation layer. At this time, the width of the heterojunction barrier becomes narrow, and the tunneling effect occurs at the triple contact point of the graphene source region, the N-type region drift region and the gate dielectric layer. Electrons from the valence band tunnel through the heterojunction barrier into the conduction band of the N-type drift region. The P+-type region and the N-type drift region form a PN junction, and the graphene source region and the N-type drift region form a heterojunction. When the device is reverse-biased withstanding voltage, the electric field peak when there is no P+-type region is located between the graphene source region and the N-type drift region. At the boundary of the heterojunction formed by the N-type drift region, the reverse leakage current is large and the breakdown voltage of the device is small. When there is a P+ type region, the electric field peak is transferred to the PN junction boundary formed by the P+ type region and the N- type drift region, which improves the avalanche capability of the device, reduces the reverse bias leakage current, and increases the device breakdown voltage. . At the same time, the cell size of the device of the present invention is smaller than that of the conventional silicon carbide power device cell, which greatly increases the number of cells per unit area, effectively reduces the specific on-resistance of the device, improves the power density of the device, and reduces the The device has sub-threshold swing, greatly simplifies the manufacturing process, and reduces the cost of the device.

Example 3:

Referring to FIG. 6 , a high power density tunneling semiconductor device based on a heterojunction, the high power density tunneling power semiconductor device based on a heterojunction is an axisymmetric structure, comprising: an N+ type substrate 1 , in an N+ type A drain metal 8 is connected to the lower surface of the substrate 1, an N-type drift region 2 is arranged on the upper surface of the N+ type substrate 1, and a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2. , the upper surface of the graphene source region 3 is symmetrically provided with a source metal 4, the upper surface of the N-type drift region 2 and the graphene source region 3 is provided with a gate dielectric layer 5, and the upper surface of the gate dielectric layer 5 is provided with a polysilicon gate 6, polysilicon A passivation layer 7 is provided above the gate 6 . A pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2, there is a certain distance between the pair of graphene source regions 3, and the N-type drift region 2 is provided with a portion overlapping with the graphene source region 3 The gate dielectric layer 5, the polysilicon gate 6 and the gate dielectric layer 5 are flush, there is a certain distance between the polysilicon gate 6 and the source metal 4, and a different contact surface is formed between the graphene source region 3 and part of the N-type drift region 2. Quality knot.

The present invention adopts the following method to prepare:

Step 1: take an N+ type substrate 1, and attach silicon carbide on the other surface of the N+ type substrate 1 to form an N- type drift region 2;

Step 2: forming a layer of graphene source region 3 on the N-type drift region 2;

Step 3: using a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;

Step 4: using a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;

Step 5: forming an isolation passivation layer 7 on the polysilicon gate 6 by a deposition process; finally, forming a source metal 4 on the upper surface of the graphene source region 3, and forming a drain metal 8 on the other surface of the N+ type substrate 1 .

A heterojunction is formed by using graphene and silicon carbide substrates. When a positive pressure is applied to the gate, the Fermi level of graphene moves up and enters the conduction band. At the same time, the electron concentration in the N-type drift region increases to form an accumulation layer. The width of the heterojunction barrier is narrowed, and the band-band tunneling effect occurs at the triple contact point of the graphene source region, the N-type region drift region and the gate dielectric layer, and the electrons in the graphene valence band tunnel through the heterojunction potential. barrier into the conduction band of the N-type drift region.

At the same time, since the three-port power device can be formed in this embodiment without the need of implantation and doping process, the cell size of the device is not limited by the doping process and the JFET region, so the cell size of the device of the present invention is larger than that of the conventional silicon carbide power device. The small cell size greatly increases the cell density of the device, effectively reduces the specific on-resistance of the device, increases the power density of the device, reduces the sub-threshold swing of the device, and greatly simplifies the manufacturing process and reduces the cost of the device. cost.

Example 4:

7, a high power density tunneling semiconductor device based on heterojunction, the high power density tunneling power semiconductor device based on heterojunction is an axisymmetric structure, including: N+ type substrate 1, in N+ type A drain metal 8 is connected to the lower surface of the substrate 1, an N-type drift region 2 is arranged on the upper surface of the N+ type substrate 1, and a pair of graphene source regions 3 are symmetrically arranged on the upper surface of the N-type drift region 2. , the upper surface of the graphene source region 3 is symmetrically provided with a source metal 4, the upper surface of the N-type drift region 2 and the graphene source region 3 is provided with a gate dielectric layer 5, and the upper surface of the gate dielectric layer 5 is provided with a polysilicon gate 6, polysilicon A passivation layer 7 is provided above the gate 6 . A groove is carved on the upper surface of the N-type drift region 2, a pair of graphene source regions 3 are symmetrically arranged in the groove of the N-type drift region 2, there is a certain distance between the pair of graphene source regions 3, and the N-type drift region 2 is provided with a gate dielectric layer 5 partially overlapping with the graphene source region 3, the polysilicon gate 6 is flush with the gate dielectric layer 5, there is a certain distance between the polysilicon gate 6 and the source metal 4, and the graphene source region 3 and the gate dielectric layer 5 are flush with each other. A heterojunction in a power device is formed at the contact surface of part of the N-type drift region 2 .

The present invention adopts the following method to prepare:

Step 1: take an N+ type substrate 1, and attach silicon carbide on the other surface of the N+ type substrate 1 to form an N- type drift region 2;

Step 2: using an etching process to form a trench on the surface of the N-type drift region 2;

Step 3: forming a layer of graphene source region 3 on the bottom of the trench;

Step 4: using a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;

Step 5: use a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;

Step 6: forming an isolation passivation layer 7 on the polysilicon gate 6 by a deposition process; finally, forming a source metal 4 on the upper surface of the graphene source region 3, and forming a drain metal 8 on the other surface of the N+ type substrate 1 .

A heterojunction is formed using graphene and silicon carbide substrates, and the area of the heterojunction is increased by a grooving process. When a positive pressure is applied to the gate, the graphene Fermi level shifts and enters the conduction band, while N- The electron concentration in the N-type drift region increases to form an accumulation layer. At this time, the width of the heterojunction barrier becomes narrow, and the band-band tunneling effect occurs at the triple contact surface of the graphene source region, the N-type region drift region and the gate dielectric layer. , the electrons in the valence band of graphene tunnel through the heterojunction barrier into the conduction band of the N-type drift region. This structure has a larger area where the band-to-band tunneling effect occurs and a higher current density.

At the same time, since the three-port power device can be formed in this embodiment without the need of implantation and doping process, the cell size of the device is not limited by the doping process and the JFET region, so the cell size of the device of the present invention is larger than that of the conventional silicon carbide power device. The small cell size greatly increases the cell density of the device, effectively reduces the specific on-resistance of the device, increases the power density of the device, reduces the sub-threshold swing of the device, and greatly simplifies the manufacturing process and reduces the cost of the device. cost.

Example 5:

Referring to FIG. 8 , a heterojunction-based high power density tunneling semiconductor device and a manufacturing process thereof, the heterojunction-based high power density tunneling power semiconductor device is an axisymmetric structure, including: an N+ type substrate 1 , a drain metal 8 is connected to the lower surface of the N+ type silicon carbide substrate 1, an N- type drift region 2 is arranged on the upper surface of the N+ type substrate 1, and a For the graphene source region 3 , the source metal 4 is symmetrically arranged on the upper surface of the graphene source region 3 . A gate dielectric layer 5 is provided on the upper surfaces of the N-type drift region 2 and the graphene source region 3, a polysilicon gate 6 is provided on the upper surface of the gate dielectric layer 5, and a passivation layer 7 is provided above the polysilicon gate 6. In the N-type drift region 2 is provided with a pair of P+ type regions 9, and a P+ type region 10 is arranged in the N- type drift region 2 under the gate dielectric layer 5. A groove is carved on the upper surface of the N-type drift region 2, a pair of P+-type regions 9 are arranged at the bottom of the groove, and a pair of graphene source regions 3 and a pair of graphene source regions 3 are symmetrically arranged in the groove of the N-type drift region 2. There is a certain distance between them, the N-type drift region 2 is provided with a gate dielectric layer 5 partially overlapping with the graphene source region 3, the polysilicon gate 6 is flush with the gate dielectric layer 5, and the polysilicon gate 6 is located between the source metal 4. There is a certain distance between them, a heterojunction is formed at the contact surface of the graphene source region 3 and the N-type drift region 2, and the graphene source region 3, the N-type region drift region 2 and the gate dielectric layer 5 are in contact, forming The triple contact point is surrounded by the depletion layer of the P+-type region 10 and the N-drift region 2 . There is a certain distance between the P+-type region 10 and the graphene source region 3, and the size of the distance is smaller than the depletion layer width of the P+-type region 10 and the N-drift region 2 when the polysilicon gate 6 applies negative pressure or zero pressure. When the depletion layer wraps the triple contact surface, and the size of the distance is larger than the depletion layer width of the P+ type region 9 and the N-drift region 2 when the polysilicon gate 6 applies positive pressure, the depletion layer does not wrap the triple contact surface. Contact point.

The present invention adopts the following method to prepare:

Step 1: take an N+ type substrate 1, and attach silicon carbide on the other surface of the N+ type substrate 1 to form an N- type drift region 2;

Step 2: using an etching process to form a trench on the surface of the N-type drift region 2;

Step 3: using a doping process to form a P+ type shielding layer 9 at the bottom of the trench, and doping a group III element on the surface of the N- type drift region 2 to form a P+ type shielding layer 10;

Step 4: forming a layer of graphene source region 3 on the bottom of the trench;

Step 5: using a deposition process to form a gate dielectric layer 5 on the upper surface of the N-type drift region 2;

Step 6: using a deposition process to deposit polysilicon on the upper surface of the gate dielectric layer 5 and form a polysilicon gate 6;

Step 7: forming an isolation passivation layer 7 on the polysilicon gate 6 by a deposition process; finally, forming a source metal 4 on the upper surface of the graphene source region 3, and forming a drain metal 8 on the other surface of the N+ type substrate 1 .

A heterojunction is formed by using graphene and silicon carbide substrates, and the Fermi level of graphene is moved up by applying positive pressure to the gate to enter the conduction band, and at the same time, the electron concentration in the N-type drift region is increased to form an accumulation layer. The electron accumulation region narrows the depletion layer between the P+ type region and the N- drift region under the gate dielectric layer, and no longer encloses the triple contact point. At this time, sufficient positive pressure is applied to the gate, and the band-band tunneling effect occurs at the triple contact surface of the graphene source region, the N-type region drift region and the gate dielectric layer, and the electrons in the graphene valence band tunnel through the heterojunction potential. barrier into the conduction band of the N-type drift region. When a negative voltage or zero voltage is applied to the gate, the depletion layer between the P+ type region and the N-drift region under the gate dielectric layer wraps the triple contact point. When the device is reverse biased, the P+ region 9 transfers the electric field peak from the boundary of the heterojunction to the boundary of the PN junction, which improves the avalanche capability of the device, reduces the reverse bias leakage current, and increases the breakdown voltage. The P+ region 10 The electric field of the gate dielectric layer 5 is shielded, and the gate oxide reliability of the device is improved.

The structure improves the reliability of the gate oxide of the device, reduces the gate-to-drain capacitance, and improves the switching characteristics without sacrificing the forward conduction capability of the high power density tunneling power semiconductor device based on the heterojunction.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. It should be regarded as the protection scope of the present invention.

Claims (10)

1. A high-power density tunneling semiconductor device based on a heterojunction is of an axisymmetric structure and comprises an N + substrate, a drain electrode metal arranged below the N + substrate, and an N-drift region arranged on the N + substrate; the tunneling junction transistor is characterized in that a pair of graphene source regions arranged at intervals are arranged above the N-drift region, source metal is arranged on the graphene source regions, a gate dielectric layer partially overlapped with the graphene source regions is arranged on the N-drift region, a polysilicon gate is arranged on the gate dielectric layer, a passivation layer is arranged on the polysilicon gate, the polysilicon gate and the source metal are arranged at intervals, a heterojunction is formed at the contact position of the graphene source region and the N-drift region, triple contact surfaces are formed among the graphene source region, the N-type region drift region and the gate dielectric layer, and tunneling effect occurs at the triple contact surfaces.

2. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein two spaced grooves are present on the upper surface of the N-type drift region (2), the graphene source region (3) is disposed in the grooves, and the P + -type region (9) is disposed in the N-type drift region (2) below the graphene source region (3).

3. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein the graphene source region (3) is disposed on the upper surface of the N-type drift region (2), and a P + type region (9) is disposed in the N-type drift region (2) below the graphene source region (3).

4. A heterojunction-based high power density tunneling semiconductor device according to claim 1, wherein the graphene source region (3) is disposed on the upper surface of the N-type drift region (2).

5. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein two spaced grooves exist on the upper surface of the N-type drift region (2), and the graphene source region (3) is arranged in the grooves.

6. The heterojunction-based high-power-density tunneling semiconductor device according to claim 1, wherein a P + type region (9) is disposed in the N-type drift region (2) below the graphene source region (3), a second P + type region (10) is disposed in the N-type drift region (2) below the gate dielectric layer (5), and the second P + type region (10) is spaced from the graphene source region (3).

7. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein the N + type substrate (1) and the N-type drift region (2) are not limited by materials, silicon carbide, gallium oxide, silicon, diamond or other materials capable of forming the heterojunction tunneling power semiconductor device substrate and drift region can be used, and the doping concentrations of the N + type substrate (1) and the N-type drift region (2) are not limited.

8. A heterojunction based high power density tunneling semiconductor device according to claim 1, wherein the graphene source region (3) is not limited by materials, and graphene, molybdenum disulfide, polysilicon, metal or other materials that can form the source region of the heterojunction tunneling semiconductor device can be used.

9. The heterojunction-based high-power-density tunneling semiconductor device and the manufacturing process thereof according to claim 1, wherein the thickness of the gate dielectric layer (5) is not limited, and the gate dielectric layer (5) is not limited by materials, and silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide or other materials capable of forming the gate dielectric layer of the heterojunction tunneling semiconductor device can be used.

10. A manufacturing method of a heterojunction-based high-power-density tunneling semiconductor device is characterized by comprising the following steps:

step 1: attaching silicon carbide on the surface of an N + type substrate (1) to form an N-type drift region (2);

step 2: forming a groove on the surface of the N-type drift region (2) by using an etching process;

and step 3: forming a P + type shielding layer (9) at the bottom of the groove by using a doping process;

and 4, step 4: forming a layer of graphene source region (3) on the bottom of the trench;

and 5: forming a gate dielectric layer (5) on the upper surface of the N-type drift region (2) by using a deposition process;

step 6: depositing polysilicon on the upper surface of the gate dielectric layer (5) by using a deposition process and forming a polysilicon gate (6);

and 7: forming an isolation passivation layer (7) above the polysilicon gate (6) by a deposition process;

and 8: and finally, forming a source metal (4) on the upper surface of the graphene source region (3), and manufacturing a drain metal (8) on the other surface of the N + type substrate (1).

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