CN115242588A - Signal demodulation processing method, communication device, and storage medium - Google Patents
Signal demodulation processing method, communication device, and storage medium Download PDFInfo
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Abstract
The invention provides a signal demodulation processing method, a communication device and a storage medium, wherein the method comprises the following steps: determining constellation map information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1; determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation map information, wherein the LLR calculation mode of at least one bit in the M bits is calculated by adopting 1 piecewise function; and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any one of the M bits. The invention can improve the calculation efficiency of calculating the LLR value of the bit.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a signal demodulation processing method, a communication device, and a storage medium.
Background
After the communication device acquires the received signal, the communication device demodulates the received signal to obtain demodulation information of the received signal. The demodulation process of the received signal includes calculating Log-likelihood Ratio (LLR) values of bits of the received signal. However, when calculating LLR values of bits at present, the LLR calculation method corresponding to each bit is to calculate by using a plurality of piecewise functions, that is, the LLR calculation formula of each bit includes a plurality of piecewise functions, for example: for 10 bits, LLR values are calculated, and 130 segment functions are included in the LLR calculation method corresponding to the 10 bits. Such LLR calculation methods use too many piecewise functions, which results in inefficient calculation of LLR values for bits.
Disclosure of Invention
Embodiments of the present invention provide a signal demodulation processing method, a communication device, and a storage medium, so as to solve the problem of low computation efficiency of computing LLR values of bits.
The embodiment of the invention provides a signal demodulation processing method, which comprises the following steps:
determining constellation map information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation map information, wherein the LLR calculation mode of at least one bit in the M bits is calculated by adopting 1 piecewise function;
and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any one of the M bits.
Optionally, the constellation information includes at least one of:
symmetry on a constellation diagram, a boundary on the constellation diagram, and a region symmetry line on the constellation diagram;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method of the odd bits of the M bits is as follows: multiplying the first constant by a first target value;
the first constant is determined in accordance with the symmetry;
the first target value is determined based on a real part of the received signal, or the first target value is determined based on at least one of the boundary and the regional symmetry line, and the real part of the received signal.
Optionally, the first constant in the LLR calculation method for the first odd-numbered bit is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd-numbered bit;
the first odd-numbered bit is an odd-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second odd-numbered bit is an odd-numbered bit of the M bits that is symmetric on the constellation diagram.
Optionally, the first target value in the LLR calculation method for the first odd-bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd-bit includes:
the difference between the absolute value of the real part of the received signal and the value of the boundary; or
The absolute difference is the difference between the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method of the first odd-bit is as follows: 4r 1 D；
The LLR calculation method for the second odd-numbered bit without a region symmetry line on the constellation diagram is as follows: -4D (| r) 1 |-Δ)；
The LLR calculation method of the second odd-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 Is the real part, Δ isThe dividing line takes the value delta i Dereferencing at least one symmetry line corresponding to the second odd-bit, | | r 1 |-δ i And | represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
Optionally, the LLR calculation method for the second odd-numbered bit having 1 region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ 1 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 2 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 3 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
Optionally, the LLR calculation method for even bits of the M bits is as follows: multiplying the second constant by a second target value;
the second constant is determined in accordance with the symmetry;
the second target value is determined based on an imaginary part of the received signal, or the second target value is determined based on at least one of the dividing line and the area symmetry line, and the imaginary part of the received signal.
Optionally, the second constant in the LLR calculation method for the first even-numbered bit is a positive number;
and in the LLR calculation mode of the second even-numbered bit, the second constant is a negative number.
The first even-numbered bit is an even-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second even-numbered bit is an even-numbered bit of the M bits that is symmetric on the constellation diagram.
Optionally, the second target value in the LLR calculation manner for the first even-numbered bit is an imaginary part of the received signal;
the second target value in the LLR calculation for the second even-numbered bit includes:
the difference value between the absolute value of the imaginary part of the received signal and the value of the boundary; or
A difference between an absolute difference value and the dividing line value, wherein the absolute difference value is an absolute value of a difference between an absolute value of an imaginary part of the received signal and the symmetrical line value;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method of the first even bit is as follows: 4r 2 D；
The LLR calculation method of the second even-numbered bit without the region symmetry line on the constellation diagram is as follows: -4D (| r) 2 |-Δ)；
The LLR calculation method of the second even-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, Δ is the value of the dividing line, δ i Dereferencing for at least one symmetry line corresponding to the second even-numbered bit, | | r 2 |-δ i And | represents the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line.
Optionally, the LLR calculation method of the second even-numbered bit with 1 region symmetry line on the constellation diagram is as follows: -4D (| | r) 2 |-δ 1 |-Δ)；
The LLR calculation method of the second even-numbered bit having 2 area symmetry lines on the constellation diagram is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-Δ)；
The LLR calculation method of the second even-numbered bit having 3 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
An embodiment of the present invention further provides a communication device, including: a memory, a transceiver, and a processor, wherein:
a memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the following operations:
determining constellation map information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation map information, wherein the LLR calculation mode of at least one bit in the M bits is calculated by adopting 1 piecewise function;
and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any one of the M bits.
Optionally, the constellation information includes at least one of:
symmetry on a constellation diagram, a boundary on the constellation diagram, and a region symmetry line on the constellation diagram;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method of the odd bits of the M bits is as follows: multiplying the first constant by a first target value;
the first constant is determined in accordance with the symmetry;
the first target value is determined based on a real part of the received signal, or the first target value is determined based on at least one of the boundary and the regional symmetry line, and the real part of the received signal.
Optionally, the first constant in the LLR calculation method for the first odd-numbered bit is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd-numbered bit;
the first odd-numbered bit is an odd-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second odd-numbered bit is an odd-numbered bit of the M bits that is symmetric on the constellation diagram.
Optionally, the first target value in the LLR calculation manner for the first odd-numbered bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd-numbered bit includes:
the difference between the absolute value of the real part of the received signal and the value of the boundary; or
The absolute difference value is the absolute value of the difference value between the real part of the received signal and the value of the symmetric line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method of the first odd-bit is as follows: 4r 1 D；
The LLR calculation method for the second odd-numbered bit without a region symmetry line on the constellation map is as follows: -4D (| r) 1 |-Δ)；
The LLR calculation method of the second odd-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 For the real part, Δ is taken at the boundary, δ i Dereferencing at least one symmetry line corresponding to the second odd-bit, | | r 1 |-δ i And | represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
Optionally, the LLR calculation method for even bits of the M bits is as follows: multiplying the second constant by a second target value;
the second constant is determined in accordance with the symmetry;
the second target value is determined based on an imaginary part of the received signal, or the second target value is determined based on at least one of the dividing line and the area symmetry line, and the imaginary part of the received signal.
Optionally, the second constant in the LLR calculation method for the first even-numbered bit is a positive number;
the second constant is a negative number in the LLR calculation method for the second even-numbered bit.
The first even-numbered bit is an even-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second even-numbered bit is an even-numbered bit of the M bits that is symmetric on the constellation diagram.
An embodiment of the present invention further provides a communication device, including:
a first determining module, configured to determine constellation information of each bit in M bits, where the M bits are M bits corresponding to a modulation scheme in a received signal, and M is an integer greater than 1;
a second determining module, configured to determine a log-likelihood ratio LLR calculation manner for each bit according to the constellation information, where an LLR calculation manner for at least one bit of the M bits is calculated by using 1 piece function;
and the calculating module is used for calculating the LLR value of the target bit according to the LLR calculating mode of the target bit, wherein the target bit is any one bit in the M bits.
Optionally, the constellation information includes at least one of:
symmetry on a constellation diagram, a boundary on the constellation diagram, and a region symmetry line on the constellation diagram;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method of the odd bits of the M bits is: multiplying the first constant by a first target value;
the first constant is determined in accordance with the symmetry;
the first target value is determined based on a real part of the received signal, or the first target value is determined based on at least one of the boundary and the regional symmetry line, and the real part of the received signal.
Optionally, the LLR calculation method for even bits of the M bits is as follows: multiplying the second constant by a second target value;
the second constant is determined in accordance with the symmetry;
the second target value is determined based on an imaginary part of the received signal, or the second target value is determined based on at least one of the dividing line and the area symmetry line, and the imaginary part of the received signal.
The embodiment of the invention also provides a processor-readable storage medium, which stores a computer program, and the computer program is used for enabling the processor to execute the signal demodulation processing method provided by the embodiment of the invention.
In the embodiment of the invention, the constellation map information of each bit in M bits is determined, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1; determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation map information, wherein the number of the piecewise functions of the LLR calculation mode of at least one bit in the M bits is 1; and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any one of the M bits. In this way, because the LLR calculation method for at least one bit of the M bits uses 1 piece function to calculate, compared with the LLR calculation method for each bit in the prior art that uses multiple piece functions to calculate, the LLR calculation efficiency for calculating the bit can be improved because the number of piece functions is reduced.
Drawings
FIG. 1 is a schematic diagram of a network architecture in which the present invention may be implemented;
fig. 2 is a flowchart of a signal demodulation processing method according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 5 is a schematic diagram of another distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 7 is a schematic diagram of another distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 8 is a block diagram of a communication device according to an embodiment of the present invention;
fig. 9 is a block diagram of another communication device according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
The term "and/or" in the embodiments of the present invention describes an association relationship of associated objects, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
The term "plurality" in the embodiments of the present invention means two or more, and other terms are similar thereto.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Embodiments of the present invention provide a signal demodulation processing method, a communication device, and a storage medium, so as to solve a problem that an LLR value of a calculation bit is low in calculation efficiency.
The method and the device are based on the same application concept, and because the principles of solving the problems of the method and the device are similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated.
The technical scheme provided by the embodiment of the invention can be suitable for various systems, particularly 6G systems. For example, the applicable system may be a global system for mobile communication (GSM) system, a Code Division Multiple Access (CDMA) system, a Wideband Code Division Multiple Access (WCDMA) General Packet Radio Service (GPRS) system, a long term evolution (long term evolution, LTE) system, an LTE Frequency Division Duplex (FDD) system, an LTE Time Division Duplex (TDD) system, an LTE-a (long term evolution) system, a universal mobile system (universal mobile telecommunications system, UMTS), a universal internet Access (WiMAX) system, a New Radio Access (WiMAX) system, a Radio Access (NR 5, new NR 6, etc. These various systems include terminal devices and network devices. The System may further include a core network portion, such as an Evolved Packet System (EPS), a 5G System (5 GS), and the like.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a network architecture to which the present invention is applicable, and as shown in fig. 1, includes a terminal 11 and a network device 12.
The terminal according to the embodiments of the present invention may be a device providing voice and/or data connectivity to a user, a handheld device having a wireless connection function, or another processing device connected to a wireless modem. In different systems, the names of the terminal devices may be different, for example, in a 5G system, the terminal device may be referred to as a User Equipment (UE). A wireless terminal device, which may be a mobile terminal device such as a mobile phone (or called a "cellular" phone) and a computer having a mobile terminal device, for example, a portable, pocket, hand-held, computer-included or vehicle-mounted mobile device, may communicate with one or more Core Networks (CNs) via a Radio Access Network (RAN), and may exchange languages and/or data with the RAN. Examples of the Wireless Communication devices include Personal Communication Service (PCS) phones, cordless phones, session Initiation Protocol (SIP) phones, wireless Local Loop (WLL) stations, personal Digital Assistants (PDAs), and Redcap terminals. The wireless terminal device may also be referred to as a system, a subscriber unit (subscriber unit), a subscriber station (subscriber station), a mobile station (mobile), a remote station (remote station), an access point (access point), a remote terminal device (remote terminal), an access terminal device (access terminal), a user terminal device (user terminal), a user agent (user agent), and a user device (user device), which are not limited in the embodiments of the present invention.
The network device related to the embodiment of the present invention may be a base station, and the base station may include a plurality of cells for providing services to the terminal. A base station may also be referred to as an access point, or a device in an access network that communicates over the air-interface, through one or more sectors, with wireless terminal devices, or by other names, depending on the particular application. The network device may be configured to exchange received air frames with Internet Protocol (IP) packets as a router between the wireless terminal device and the rest of the access network, which may include an Internet Protocol (IP) communication network. The network device may also coordinate attribute management for the air interface. For example, the network device according to the embodiment of the present invention may be a Base Transceiver Station (BTS) in a Global System for Mobile communications (GSM) or a Code Division Multiple Access (CDMA), may be a network device (NodeB) in a Wideband Code Division Multiple Access (WCDMA), may be an evolved Node B (eNB) or an e-NodeB) in a Long Term Evolution (LTE) System, may be a Base Station in a 5G Base Station (gNB) or a 6G Base Station in a 5G network architecture (next generation System), may be a Home evolved Node B (Home evolved Node B, heNB), a relay Node (relay Node), a Home Base Station (pico) or a pico Base Station (pico) in the embodiment of the present invention, and is not limited. In some network architectures, a network device may include a Centralized Unit (CU) node and a Distributed Unit (DU) node, which may also be geographically separated.
The network device and the terminal may each use one or more antennas for Multiple Input Multiple Output (MIMO) transmission, and the MIMO transmission may be Single User MIMO (SU-MIMO) or Multi-User MIMO (MU-MIMO). The MIMO transmission may be 2D-MIMO, 3D-MIMO, FD-MIMO, or massive-MIMO, or may be diversity transmission, precoding transmission, beamforming transmission, or the like, depending on the form and number of root antenna combinations.
Referring to fig. 2, fig. 2 is a flowchart of a signal demodulation processing method according to an embodiment of the present invention, as shown in fig. 2, including the following steps:
The received signal is a received signal acquired by a communication device, and the communication device may be a terminal or a network side device.
In the embodiment of the present invention, the number of bits corresponding to different modulation schemes may be different, for example: if the modulation mode is Quadrature Phase Shift Keying (QPSK), the corresponding bit number M =2; if the Modulation is 16 Quadrature Amplitude Modulation (QAM), the corresponding bit number M =4; if 64QAM, the corresponding bit number M =6; if 256QAM, the corresponding number of bits M =8; if the QAM is 1024QAM, the corresponding bit quantity M =10; in case of 2048QAM, the corresponding number of bits M =12.
The modulation method in step 201 may be set according to actual requirements. The M bits may be specifically determined according to the above relationship. It should be noted that, in the embodiment of the present invention, a correspondence between a modulation mode and a bit number is not limited, and the correspondence may be specifically configured according to an actual requirement or predefined by a protocol.
In addition, in the embodiment of the present invention, different modulation modes correspond to respective constellation diagrams, and a protocol may be specifically adopted for the constellation diagram defined for each modulation mode. And the constellation diagram information of each bit is the distribution characteristic information of each bit on the constellation diagram corresponding to the modulation mode. For example: symmetry on a constellation diagram, a boundary on the constellation diagram, a regional symmetry line on the constellation diagram, etc. In addition, the constellation map information of each bit in the M bits is determined according to a preset rule, or the constellation map information of each bit is configured in advance. For example: a first bit of the M bits is asymmetric in the constellation and has no regional symmetry line, a second bit of the M bits is asymmetric in the constellation and has no regional symmetry line, a third bit of the M bits is symmetric in the constellation and has no regional symmetry line, a fourth bit of the M bits is symmetric in the constellation and has no regional symmetry line, a fifth bit of the M bits is symmetric in the constellation and has a boundary line and a regional symmetry line, a sixth bit of the M bits is symmetric in the constellation and has a boundary line and a regional symmetry line, etc., which are not listed here.
The determining of the LLR calculation manner for each bit according to the constellation information may be determining a respective LLR calculation manner according to the constellation information for each bit, that is, the LLR calculation manner for each bit is associated with the respective constellation information. Specifically, constellation-related constants in the LLR calculation mode, which is composed of the constants and the real part or the imaginary part of the received signal, may be determined according to the constellation information of the bits. In the embodiment of the invention, the LLR calculation mode can be an LLR calculation formula, namely an LLR calculation mode is adopted to calculate LLR values.
In this embodiment of the present invention, the LLR calculation method for at least one bit of the M bits is to calculate by using 1 piecewise function, which may be understood that the number of the piecewise functions of the LLR calculation formula for at least one bit of the M bits is 1, for example: the number of the piecewise functions of the LLR calculation formula for each of the M bits is 1, which can further improve the calculation efficiency. Of course, in some embodiments or scenarios, the number of the segment functions of the LLR calculation formula for a part of bits may be 1, and the LLR calculation formula for another part of bits includes a plurality of segment functions, which may also improve the calculation efficiency. In addition, in the embodiment of the present invention, the piecewise function may also be referred to as a branch function.
The calculating of the LLR value of the target bit according to the LLR calculation method of the target bit may be that, for each bit, an LLR calculation method is used to calculate an LLR value, so as to obtain an LLR value of the M bits.
In the embodiment of the invention, the LLR calculation mode of M bits can be determined through the steps, and the LLR calculation mode of at least one bit in the M bits is calculated by adopting 1 piece-wise function, so that compared with the prior art that the LLR calculation mode of each bit is calculated by adopting a plurality of piece-wise functions, the calculation efficiency of calculating the LLR value of the bit can be improved due to the reduction of the number of the piece-wise functions, and further, the cost of hardware resources can be saved due to the reduction of the number of the piece-wise functions in the LLR calculation mode.
As an optional implementation manner, the constellation information includes at least one of the following:
symmetry on a constellation diagram, a boundary on the constellation diagram, and a region symmetry line on the constellation diagram;
the constellation diagram corresponds to the modulation mode.
The symmetry on the constellation diagram may indicate whether the bits are symmetric on the constellation diagram, and further may indicate whether the bits are symmetric on a specific coordinate axis on the constellation diagram. For example: the above symmetry on the constellation diagram may represent the number r of bits on the constellation diagram 1 =0 or r 2 =0 is the symmetry of the axis of symmetry.
The above-mentioned boundary on the constellation diagram may be a boundary of bits between 0 and 1, or a boundary of 1 and-1, respectively, of the constellation diagram.
The region symmetry line on the constellation diagram may be a symmetry line of a bit in a partial region of the constellation diagram.
The following is an example of an odd bit of the M bits:
m/2 odd bits among the M bits are: a is n N =1,2, …, M/2, i.e. (a) 1 ,a 2 ,…,a M/2 ) The bits are represented by r on the constellation diagram 1 =0 denotes symmetry of the symmetry axis, a boundary line, and a local symmetry line.
For n =1, i.e. the first odd bit, not r 1 =0 left-right symmetry, the dividing line of the bits being r 1 = Δ, and Δ =0, the number of regional symmetry lines of the bit is 0, and there is no regional symmetry line. For example: taking 1024QAM as an example of the modulation scheme, the bit (i.e., a) 1 Bits) may be distributed over the constellation as shown in fig. 3, not with r 1 =0 bilateral symmetry, the dividing line being r 1 = Δ, and Δ =0, the number of regional symmetry lines is 0, that is, there is no regional symmetry line.
For n =2, i.e. the second odd bit, with r 1 =0 left-right symmetry, the bit dividing line being r 1 = Δ, and Δ =2 (M/2-1) D, the number of the area symmetry lines of the bit is 0, and the area symmetry lines are not.
In this embodiment, D is an energy normalization factor of a constellation point, and for a given constellation point, D is a constant, for example: if the modulation scheme is QPSK, then
If the modulation scheme is 16QAM
If the modulation scheme is 64QAM
If the modulation scheme is 256QAM
If the modulation mode is 1024QAM
For example: taking 1024QAM as an example of the modulation scheme, n =2 bits (i.e. a) 2 Bits) may be distributed over the constellation as shown in fig. 4, with r 1 =0 bilateral symmetry with a dividing line r 1 = Δ, and Δ =16D, the number of area symmetry lines is 0, and no area symmetry line exists.
For n>=3, i.e. for odd-numbered bit 3 and odd-numbered bits after odd-numbered bit 3, with r 1 Left-right symmetry of =0, the bit boundaries being r 1 ＝Δ，Δ＝2 (M/2-1-(n-2)) D, the number of the symmetry lines of the bit regions is n-2, and the symmetry line of the region is r 1 ＝δ i And δ i ＝2 (M/2-1-(i-1)) D,i＝1,…,n-2。
For example: for example, n =3 bits (a) with a modulation scheme of 1024QAM 3 Bits) may be distributed over the constellation as shown in fig. 5, with r 1 =0 bilateral symmetry, the dividing line being r 1 = Δ, Δ =8D, the number of area symmetry lines is 1, and the area symmetry line is r 1 ＝δ 1 And δ 1 ＝16D。
For example: taking 1024QAM as an example of a modulation scheme, n =4 bits (a) 4 Bits) distribution over the constellation diagram can be as shown in fig. 6, with r 1 =0 bilateral symmetry with a dividing line r 1 = Δ, Δ =4D, the number of area symmetry lines is 2, and the area symmetry line is r 1 ＝δ 1 And r 1 ＝δ 2 And δ 1 =16D, and δ 2 ＝8D。
For example: taking 1024QAM as an example of a modulation scheme, n =5 bits (a) 5 Bits) distribution over the constellation diagram can be as shown in fig. 7, with r 1 =0 bilateral symmetry, the dividing line being r 1 = Δ, Δ =2D, the number of area symmetry lines is 3, and the area symmetry line is r 1 ＝δ 1 ，r 1 ＝δ 2 And r is 1 ＝δ 3 And δ 1 ＝16D，δ 2 =8D, and δ 3 ＝4D。
The following is an example of even bits of the M bits:
the M/2 even bits of the M bits are: b is a mixture of n N =1,2, …, M/2, i.e. (b) 1 ,b 2 ,…,b M/2 ) The bits are represented by r on the constellation diagram 2 =0 denotes symmetry of the symmetry axis, a boundary line, and a local symmetry line.
For n =1, i.e. the first even bit, not with r 2 =0 left-right symmetry, the bit dividing line being r 2 = Δ, and Δ =0, the number of area symmetry lines of the bit is 0, and there is no area symmetry line.
For n =2, i.e. the second even bit, with r 2 =0 left-right symmetry, the dividing line of the bits being r 2 = Δ, and Δ =2 (M/2-1) D, the number of the area symmetry lines of the bit is 0, and the area symmetry lines are not.
For n>=3, i.e. for the 3 rd even bit and the even bits after the 3 rd even bit, with r 2 Left-right symmetry of =0, the bit boundaries being r 2 ＝Δ，Δ＝2 (M/2-1-(n-2)) D, the number of the symmetry lines of the bit regions is n-2, and the symmetry line of the regions is r 2 ＝δ i And δ i ＝2 (M/2-1-(i-1)) D,i＝1,…,n-2。
In the embodiment of the present invention, the distribution of each bit of the M bits on the constellation diagram is determined according to a modulation rule, or is configured in advance, or is predefined by a protocol.
As an optional implementation manner, the LLR calculation manner of the odd bits of the M bits is as follows: multiplying the first constant by a first target value;
the first constant is determined in accordance with the symmetry;
the first target value is determined based on a real part of the received signal, or the first target value is determined based on at least one of the boundary and the regional symmetry line, and the real part of the received signal.
The LLR calculation method for the odd bits of the M bits is as follows: the first constant is multiplied by the first target value, which allows the LLR calculation for odd bits to be performed using 1 piece function, because the first constant multiplied by the first target value is a piece function.
The first constant may be a predetermined constant determined according to symmetry, for example: 4D or-4D, it should be noted that 4D or-4D is only an optional implementation, for example: in some scenarios or embodiments, it may also be: 8D or-8D, 2D or-2D and the like, and the specific value can be set according to the actual requirement or the protocol is predefined.
The first target value may be determined according to the real part of the received signal, and the first target value may be determined according to only the real part of the received signal, for example, the first target value is the real part of the received signal.
The first target value may be determined based on at least one of the boundary and the local symmetry line, and the real part of the received signal, and the first target value may be calculated based on at least one of the boundary and the local symmetry line, and the real part of the received signal.
In this embodiment, since the LLR calculation method is to multiply the first constant by the first target value, 1 piece function may be used in the LLR calculation method to perform calculation, and the LLR calculation method may also be simplified to further improve the calculation efficiency. It should be noted that, in the embodiment of the present invention, not limited to that, the LLR calculation method for the odd bits of the M bits is as follows: the first constant is multiplied by a first target value, for example: in some scenarios or services, the LLR calculation method for odd bits is as follows: the first constant is multiplied by the first target value, and the constant is added, wherein the constant can be associated with services and scenes, so that different LLR calculation modes can be adopted for different services and scenes.
Optionally, the first constant in the LLR calculation method for the first odd-numbered bit is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd-numbered bit;
the first odd-numbered bit is an odd-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second odd-numbered bit is an odd-numbered bit of the M bits that is symmetric on the constellation diagram.
The first odd-numbered bit may be a first odd-numbered bit of the M bits, because the first odd-numbered bit is asymmetric in a constellation diagram, and the second odd-numbered bit may include two, a third, a fourth, a fifth, and the like odd-numbered bits, which are symmetric in the constellation diagram.
For example: the first odd-bit is asymmetrical on the constellation diagram, the first constant of the LLR calculation mode of the bit is 4D, the second, third, fourth and other odd-bit bits are symmetrical on the constellation diagram, and the first constant of the LLR calculation mode of the bit is-4D.
Optionally, the first target value in the LLR calculation method for the first odd-bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd-numbered bit includes:
the difference between the absolute value of the real part of the received signal and the value of the boundary; or
The absolute difference value is the absolute value of the difference value between the real part of the received signal and the value of the symmetric line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
The absolute difference may be an absolute value of a difference between the absolute value of the real part of the received signal and the value of the symmetry line, and may include at least one of:
for a bit with only one line of symmetry, the absolute difference of the bit is: receiving the absolute value of the difference value between the absolute value of the real part of the signal and the value of the symmetric line;
for a bit with two symmetry lines, the absolute difference of the bit is obtained as follows: subtracting the value difference of one symmetrical line from the absolute value of the real part of the received signal, subtracting the value difference of the other symmetrical line from the absolute value of the difference, and taking the absolute value of the difference;
for bits of three and more symmetry lines, the absolute difference of the bits is obtained by: subtracting the value difference of one symmetrical line from the absolute value of the real part of the received signal, subtracting the value difference of another symmetrical line from the absolute value of the difference, subtracting the value of another symmetrical line from the absolute value of the difference until the values of all the symmetrical lines are subtracted, and taking the absolute value of the final difference.
In this embodiment, the LLR calculation method for the first odd-numbered bit may be implemented as follows: the first constant is multiplied by the real part of the received signal, and the LLR calculation method for the second odd-bit is as follows: the difference between the absolute value of the real part of the received signal and the value of the boundary is multiplied by the first constant, or the difference between the absolute value and the value of the boundary is multiplied by the first constant, so that the calculation efficiency can be improved.
For example: taking the first constant of 4D or-4D as an example, the LLR calculation method for the first odd-bit is as follows: 4r of 1 D；
The LLR calculation method for the second odd-numbered bit without a region symmetry line on the constellation map is as follows: -4D (| r) 1 |-Δ)；
The LLR calculation method of the second odd-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 Is the real part, delta is the value of the dividing line, delta i And taking a value for at least one symmetry line corresponding to the second odd-numbered bit.
Wherein, | | r 1 |-δ i And | represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line. For example: the absolute difference for the second odd-bit with 1 region symmetry line on the constellation is | | r 1 |-δ 1 L, |; the absolute difference for the second odd-bit with 2 region symmetry lines on the constellation is: | | | r 1 |-δ 1 |-δ 2 L, |; the absolute difference for the second odd bit with 3 region symmetry lines on the constellation is: | | | r 1 |-δ 1 |-δ 2 |-δ 3 L, |; wherein, delta 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
Optionally, the LLR calculation method for the second odd-numbered bit having 1 region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ 1 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 2 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 3 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
In this embodiment, the LLR calculation method described above can further improve the calculation efficiency.
For example: for n =1, i.e. the 1 st odd bit, not r 1 If 0 is bilaterally symmetric, then LLR(a 1 )＝4r 1 D；
For n =2, i.e. the 2 nd odd bit, with r 1 If 0 is left-right symmetric, then LLR (a) 2 )＝-4D(|r 1 I- Δ), where Δ =2 (M/2-1) D；
For n =3, i.e. the 3 rd odd bit, with r 1 =0 bilateral symmetry, if the number of regional symmetry lines is n-2 and is 1, then LLR (a) 3 )＝-4D(||r 1 |-δ 1 I- Δ), wherein Δ =2 (M/2-2) D，δ 1 ＝2 (M/2-1) D；
For n =4, i.e. the 4 th odd bit, with r 1 If the number of regional symmetry lines is n-2 and 2, then LLR (a) is obtained 4 )＝-4D(|||r 1 |-δ 1 |-δ 2 I- Δ), wherein Δ =2 (M/2-3) D，δ 1 ＝2 (M/2-1) D, and δ 2 ＝2 (M/2-2) D。
For n =5, i.e. the 5 th odd bit, with r 1 If the number of regional symmetry lines is n-2 and 3, then LLR (a) is obtained 5 )＝-4D(||||r 1 |-δ 1 |-δ 2 |-δ 3 I- Δ), wherein Δ =2 (M/2-4) D，δ 1 ＝2 (M/2-1) D，δ 2 ＝2 (M/2-2) D, and delta 3 ＝2 (M/2-3) D。
Wherein r is 1 Is the real part of the received signal.
When the modulation mode is 1024QAM, M =10, M bit is a 1 ,b 1 ,a 2 ,b 2 ,a 3 ,b 3 ,a 4 ,b 4 ,a 5 ,b 5 Then a is 1 ,a 2 ,a 3 ,a 4 ,a 5 The LLR calculation methods of (a) are as follows:
LLR(a 1 )＝4r 1 D；
LLR(a 2 )＝-4D(|r 1 |-16D)；
LLR(a 3 )＝-4D(||r 1 |-16D|-8D)；
LLR(a 4 )＝-4D(|||r 1 |-16D|-8D|-4D)；
LLR(a 5 )＝-4D(||||r 1 |-16D|-8D|-4D|-2D)。
it should be noted that, the above description mainly refers to bits without region symmetry line on the constellation diagram, and bits with 1,2, and 3 region symmetry lines on the constellation diagram, for example:
the LLR calculation method for the second odd-bit bits having 4 region symmetry lines on the constellation diagram is as follows: -4D (| | | | r) 1 |-δ 1 |-δ 2 |-δ 3 |-δ 4 |-Δ)；
The LLR calculation method for the second odd-bit bits having 5 region symmetry lines on the constellation diagram is as follows: -4D (| | | | r) 1 |-δ 1 |-δ 2 |-δ 3 |-δ 4 |-δ 5 |-Δ)。
δ 1 ，δ 2 ，δ 3 ，δ 4 ，δ 5 Respectively taking values of 5 area symmetry lines.
Reference may be made specifically to-4D (| | r) mentioned above 1 |-δ i | Δ), where | | r 1 |-δ i And | represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
As an optional implementation, the LLR calculation method for even bits of the M bits is as follows: multiplying the second constant by a second target value;
the second constant is determined in accordance with the symmetry;
the second target value is determined based on an imaginary part of the received signal, or the second target value is determined based on at least one of the dividing line and the area symmetry line, and the imaginary part of the received signal.
The second constant may refer to the description of the first constant, and in some embodiments, the second constant may be equal to the first constant, for example: the second constant may be 4D or-4D. The second target value may be referred to in the description of the first target data value, except that the real part of the first target data value is replaced by the imaginary part.
Optionally, the second constant in the LLR calculation method for the first even-numbered bit is a positive number;
the second constant is a negative number in the LLR calculation method for the second even-numbered bit.
The first even-numbered bit is an even-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second even-numbered bit is an even-numbered bit of the M bits that is symmetric on the constellation diagram.
Wherein the symmetry may be r of a constellation diagram 2 Upper and lower symmetry of = 0.
Optionally, the second target value in the LLR calculation manner for the first even-numbered bit is an imaginary part of the received signal;
the second target value in the LLR calculation for the second even-numbered bit includes:
the difference value between the absolute value of the imaginary part of the received signal and the value of the boundary; or
A difference between an absolute difference value and the dividing line value, wherein the absolute difference value is an absolute value of a difference between an absolute value of an imaginary part of the received signal and the symmetrical line value;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
The second target value may refer to the relevant description of the first target data value, and only the real part in the first target data value is replaced by the imaginary part.
Optionally, the LLR calculation method of the first even bit is as follows: 4r 2 D；
The LLR calculation method of the second even-numbered bit without the region symmetry line on the constellation diagram is as follows: -4D (| r) 2 |-Δ)；
The LLR calculation method of the second even-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, Δ is the value of the dividing line, δ i And taking values of at least one symmetrical line corresponding to the second even-numbered bit.
Wherein, | | r 2 |-δ i And | represents the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line. For example: the absolute difference for the second even bit with 1 region symmetry line on the constellation diagram is | | r 2 |-δ 1 L, |; the absolute difference for the second even bit with 2 region symmetry lines on the constellation is: | | | r 2 |-δ 1 |-δ 2 L, |; the absolute difference for the second even bit with 3 regional symmetry lines on the constellation is: | | | r 2 |-δ 1 |-δ 2 |-δ 3 L, |; wherein, delta 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
In addition, the above 4r 2 D、-4D(|r 2 | Δ) is-4D (| | r) 2 |-δ i I-a) are 3 different piecewise functions, respectively.
Optionally, the LLR calculation method of the second even-numbered bit with 1 region symmetry line on the constellation diagram is as follows: -4D (| | r) 2 |-δ 1 |-Δ)；
The LLR calculation method of the second even-numbered bit having 2 area symmetry lines on the constellation diagram is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-Δ)；
The LLR calculation method of the second even-numbered bit having 3 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
In this embodiment, the LLR calculation method described above can further improve the calculation efficiency.
For example: for n =1, i.e. the 1 st even bit, not with r 2 If =0 is vertically symmetrical, LLR (b) 1 )＝4r 2 D；
For n =2, i.e. the 2 nd odd bit, with r 2 If =0 is vertically symmetrical, LLR (b) 2 )＝-4D(|r 2 I- Δ), where Δ =2 (M/2-1) D；
For n =3, i.e. the 3 rd even bit, with r 2 If the number of regional symmetry lines is n-2 and 1, then LLR (b) is obtained 3 )＝-4D(||r 2 |-δ 1 I- Δ), wherein Δ =2 (M/2-2) D，δ 1 ＝2 (M/2-1) D；
For n =4, i.e. the 4 th even bit, with r 2 =0 top-bottom symmetry, the number of regional symmetry lines is n-2 and is 2, and LLR (b) 4 )＝-4D(|||r 2 |-δ 1 |-δ 2 I- Δ), wherein Δ =2 (M/2-3) D，δ 1 ＝2 (M/2-1) D, and δ 2 ＝2 (M/2-2) D。
For n =5, i.e. the 5 th even bit, with r 2 If the number of regional symmetry lines is n-2 and 3, then LLR (b) is obtained 5 )＝-4D(||||r 2 |-δ 1 |-δ 2 |-δ 3 I- Δ), wherein Δ =2 (M/2-4) D，δ 1 ＝2 (M/2-1) D，δ 2 ＝2 (M/2-2) D, and δ 3 ＝2 (M/2-3) D。
Wherein r is 2 Is the imaginary part of the received signal.
When the modulation mode is 1024QAM, M =10, M bit is a 1 ,b 1 ,a 2 ,b 2 ,a 3 ,b 3 ,a 4 ,b 4 ,a 5 ,b 5 Then b is 1 ,b 2 ,b 3 ,b 4 ,b 5 The LLR calculation methods of (a) are as follows:
LLR(b 1 )＝4r 2 D；
LLR(b 2 )＝-4D(|r 2 |-16D)；
LLR(b 3 )＝-4D(||r 2 |-16D|-8D)；
LLR(b 4 )＝-4D(|||r 2 |-16D|-8D|-4D)；
LLR(b 5 )＝-4D(||||r 2 |-16D|-8D|-4D|-2D)。
specifically, with the method provided by the embodiment of the present invention, when a 1024QAM modulation scheme is adopted, the M bits may be represented as a 1 ,b 1 ,a 2 ,b 2 ,a 3 ,b 3 ,a 4 ,b 4 ,a 5 ,b 5 ，a 1 ,b 1 ,a 2 ,b 2 ,a 3 ,b 3 ,a 4 ,b 4 ,a 5 ,b 5 The LLR value method of (1) is as follows:
LLR(a 1 )＝4r 1 D
LLR(a 2 )＝-4D(|r 1 |-16D)
LLR(a 3 )＝-4D(||r 1 |-16D|-8D)
LLR(a 4 )＝-4D(|||r 1 |-16D|-8D|-4D)
LLR(a 5 )＝-4D(||||r 1 |-16D|-8D|-4D|-2D)
LLR(b 1 )＝4r 2 D
LLR(b 2 )＝-4D(|r 2 |-16D)
LLR(b 3 )＝-4D(||r 2 |-16D|-8D)
LLR(b 4 )＝-4D(|||r 2 |-16D|-8D|-4D)
LLR(b 5 )＝-4D(||||r 2 |-16D|-8D|-4D|-2D)
d is the energy normalization factor for the constellation point, D is a constant for a given constellation point,
LLR is the LLR value of each bit;
wherein, a 1 ,a 2 ,a 3 ,a 4 ,a 5 1 to 5 bits of the constellation points with the same real part, wherein b 1 ,b 2 ,b 3 ,b 4 ,b 5 Respectively 1 to 5 bits of the constellation points with the same imaginary part; r is 1 For receiving messagesReal part of the signal, r 2 Is the imaginary part of the received signal;
in the embodiment of the invention, the number of the piecewise functions is reduced, thereby accelerating the demodulation speed, reducing the time delay and reducing the hardware resource overhead.
In the embodiment of the invention, the constellation map information of each bit in M bits is determined, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1; determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation map information, wherein the number of the piecewise functions of the LLR calculation mode of at least one bit in the M bits is 1; and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any one of the M bits. In this way, the LLR calculation method for at least one bit of the M bits uses a piecewise function to calculate, so that the calculation efficiency of calculating the LLR value of the bit can be improved.
Referring to fig. 8, fig. 8 is a structural diagram of a communication device according to an embodiment of the present invention, as shown in fig. 8, including a memory 820, a transceiver 800, and a processor 810:
a memory 820 for storing a computer program; a transceiver 800 for transceiving data under the control of the processor 810; a processor 810 for reading the computer program in the memory 820 and performing the following operations:
the embodiment of the invention provides a signal demodulation processing method, which comprises the following steps:
determining constellation map information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation map information, wherein the LLR calculation mode of at least one bit in the M bits is calculated by adopting 1 piecewise function;
and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any one of the M bits.
Wherein in fig. 8 the bus architecture may include any number of interconnected buses and bridges, with one or more processors represented by processor 810 and various circuits of memory represented by memory 820 being linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The transceiver 800 may be a number of elements including a transmitter and a receiver that provide a means for communicating with various other apparatus over transmission media including wireless channels, wired channels, fiber optic cables, and the like. The user interface 830 may also be an interface capable of interfacing with a desired device for different user devices, including but not limited to a keypad, a display, a speaker, a microphone, a joystick, etc.
The processor 810 is responsible for managing the bus architecture and general processing, and the memory 820 may store data used by the processor 800 in performing operations.
Alternatively, the processor 810 may be a CPU (central processing unit), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a CPLD (Complex Programmable Logic Device), and the processor may also have a multi-core architecture.
The processor is used for executing any method provided by the embodiment of the invention according to the obtained executable instructions by calling the computer program stored in the memory. The processor and memory may also be physically separated.
Optionally, the constellation information includes at least one of:
symmetry on a constellation diagram, a boundary on the constellation diagram, and a region symmetry line on the constellation diagram;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method of the odd bits of the M bits is: multiplying the first constant by a first target value;
the first constant is determined in accordance with the symmetry;
the first target value is determined based on a real part of the received signal, or the first target value is determined based on at least one of the boundary and the regional symmetry line, and the real part of the received signal.
Optionally, the first constant in the LLR calculation method for the first odd-numbered bit is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd-numbered bit;
the first odd-numbered bit is an odd-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second odd-numbered bit is an odd-numbered bit of the M bits that is symmetric on the constellation diagram.
Optionally, the first target value in the LLR calculation method for the first odd-bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd-bit includes:
the difference between the absolute value of the real part of the received signal and the value of the boundary; or
The absolute difference is the difference between the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method of the first odd-numbered bit is as follows: 4r 1 D；
The LLR calculation method for the second odd-numbered bit without a region symmetry line on the constellation map is as follows: -4D (| r) 1 |-Δ)；
The LLR calculation method of the second odd-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 For the real part, Δ is taken at the boundary, δ i Dereferencing at least one symmetry line corresponding to the second odd-bit, | | r 1 |-δ i And | represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetric line.
Optionally, the LLR calculation method of the second odd-numbered bit with 1 region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ 1 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 2 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 3 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
Optionally, the LLR calculation method for even bits of the M bits is as follows: multiplying the second constant by a second target value;
the second constant is determined in accordance with the symmetry;
the second target value is determined based on an imaginary part of the received signal, or the second target value is determined based on at least one of the dividing line and the area symmetry line, and the imaginary part of the received signal.
Optionally, the second constant in the LLR calculation method for the first even-numbered bit is a positive number;
and in the LLR calculation mode of the second even-numbered bit, the second constant is a negative number.
The first even-numbered bit is an even-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second even-numbered bit is an even-numbered bit of the M bits that is symmetric on the constellation diagram.
Optionally, the second target value in the LLR calculation manner for the first even-numbered bit is an imaginary part of the received signal;
the second target value in the LLR calculation for the second even-numbered bit includes:
the difference value between the absolute value of the imaginary part of the received signal and the value of the boundary; or
A difference between an absolute difference value and the dividing line value, wherein the absolute difference value is an absolute value of a difference between an absolute value of an imaginary part of the received signal and the symmetrical line value;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method of the first even bit is as follows: 4r 2 D；
The LLR calculation method of the second even-numbered bit without the region symmetry line on the constellation diagram is as follows: -4D (| r) 2 |-Δ)；
The LLR calculation method of the second even-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, Δ is the value of the dividing line, δ i Dereferencing for at least one symmetry line corresponding to the second even-numbered bit, | | r 2 |-δ i And | represents the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line.
Optionally, the LLR calculation method of the second even-numbered bit with 1 region symmetry line on the constellation diagram is as follows: -4D (| | r) 2 |-δ 1 |-Δ)；
The LLR calculation method of the second even-numbered bit having 2 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-Δ)；
The second even-numbered bit having 3 region symmetry lines on the constellation diagramThe LLR calculation method is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 region symmetry lines are respectively taken.
It should be noted that, the communication device provided in the embodiment of the present invention can implement all the method steps implemented by the method embodiment and can achieve the same technical effects, and detailed descriptions of the same parts and beneficial effects as those of the method embodiment in this embodiment are omitted here.
Referring to fig. 9, fig. 9 is a structural diagram of another communication device according to an embodiment of the present invention, and as shown in fig. 9, a communication device 900 includes:
a first determining module 901, configured to determine constellation map information of each bit of M bits, where the M bits are M bits corresponding to a modulation scheme in a received signal, and M is an integer greater than 1;
a second determining module 902, configured to determine, according to the constellation information, a log-likelihood ratio LLR calculation manner for each bit, where an LLR calculation manner for at least one bit of the M bits is calculated by using 1 piece function;
a calculating module 903, configured to calculate an LLR value of a target bit according to an LLR calculation manner of the target bit, where the target bit is any one of the M bits.
Optionally, the constellation information includes at least one of:
symmetry on a constellation diagram, a boundary on the constellation diagram, and a region symmetry line on the constellation diagram;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method of the odd bits of the M bits is as follows: multiplying the first constant by a first target value;
the first constant is determined in accordance with the symmetry;
the first target value is determined based on a real part of the received signal, or the first target value is determined based on at least one of the boundary and the regional symmetry line, and the real part of the received signal.
Optionally, the first constant in the LLR calculation method for the first odd-numbered bit is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd-numbered bit;
the first odd-numbered bit is an odd-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second odd-numbered bit is an odd-numbered bit of the M bits that is symmetric on the constellation diagram.
Optionally, the first target value in the LLR calculation method for the first odd-bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd-bit includes:
the difference between the absolute value of the real part of the received signal and the value of the boundary; or
The absolute difference is the difference between the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method of the first odd-bit is as follows: 4r of 1 D；
The LLR calculation method for the second odd-numbered bit without a region symmetry line on the constellation map is as follows: -4D (| r) 1 |-Δ)；
The LLR calculation method for the second odd-numbered bit having a region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 Is the real part, delta is the value of the dividing line, delta i Dereferencing at least one symmetry line corresponding to the second odd-bit, | | r 1 |-δ i And | represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
Optionally, the LLR calculation method for the second odd-numbered bit having 1 region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ 1 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 2 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 3 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
Optionally, the LLR calculation method for even bits of the M bits is as follows: multiplying the second constant by a second target value;
the second constant is determined in accordance with the symmetry;
the second target value is determined based on an imaginary part of the received signal, or the second target value is determined based on at least one of the dividing line and the area symmetry line, and the imaginary part of the received signal.
Optionally, the second constant in the LLR calculation method for the first even-numbered bit is a positive number;
the second constant is a negative number in the LLR calculation method for the second even-numbered bit.
The first even-numbered bit is an even-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second even-numbered bit is an even-numbered bit of the M bits that is symmetric on the constellation diagram.
Optionally, the second target value in the LLR calculation manner for the first even-numbered bit is an imaginary part of the received signal;
the second target value in the LLR calculation method for the second even-numbered bit includes:
a difference between an absolute value of an imaginary part of the received signal and a value of a boundary; or
A difference between an absolute difference value and the dividing line value, wherein the absolute difference value is an absolute value of a difference between an absolute value of an imaginary part of the received signal and the symmetrical line value;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method of the first even bit is as follows: 4r 2 D；
The LLR calculation method of the second even-numbered bit without the region symmetry line on the constellation diagram is as follows: -4D (| r) 2 |-Δ)；
The LLR calculation method of the second even-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, Δ is the value of the dividing line, δ i Dereferencing for at least one symmetry line corresponding to the second even-numbered bit, | | r 2 |-δ i And | represents the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line.
Optionally, the LLR calculation method of the second even-numbered bit with 1 region symmetry line on the constellation diagram is as follows: -4D (| | r) 2 |-δ 1 |-Δ)；
The LLR calculation method of the second even-numbered bit having 2 area symmetry lines on the constellation diagram is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-Δ)；
The LLR calculation method of the second even-numbered bit having 3 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
It should be noted that, the communication device provided in the embodiment of the present invention can implement all the method steps implemented by the method embodiment and achieve the same technical effect, and detailed descriptions of the same parts and beneficial effects as the method embodiment in this embodiment are omitted here.
It should be noted that the division of the unit in the embodiment of the present invention is schematic, and is only a logic function division, and there may be another division manner in actual implementation. In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.
The integrated unit, if implemented as a software functional unit and sold or used as a stand-alone product, may be stored in a processor readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The embodiment of the invention also provides a processor-readable storage medium, which stores a computer program, and the computer program is used for enabling the processor to execute the signal demodulation processing method provided by the embodiment of the invention.
The processor-readable storage medium can be any available medium or data storage device that can be accessed by a processor, including, but not limited to, magnetic memory (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical memory (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor memory (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND FLASH), solid State Disks (SSDs)), etc.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These processor-executable instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (25)
1. A signal demodulation processing method, comprising:
determining constellation map information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation map information, wherein the LLR calculation mode of at least one bit in the M bits adopts 1 piecewise function to calculate;
and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any one bit in the M bits.
2. The method of claim 1, wherein the constellation information comprises at least one of:
symmetry on a constellation diagram, a boundary on the constellation diagram, and a region symmetry line on the constellation diagram;
the constellation diagram corresponds to the modulation mode.
3. The method of claim 2, wherein the LLRs for odd-numbered bits of the M bits are calculated by: multiplying the first constant by a first target value;
the first constant is determined in accordance with the symmetry;
the first target value is determined based on a real part of the received signal, or the first target value is determined based on at least one of the boundary and the regional symmetry line, and the real part of the received signal.
4. The method of claim 3, wherein the LLR calculation for the first odd-bit is such that the first constant is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd-numbered bit;
the first odd-numbered bit is an odd-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second odd-numbered bit is an odd-numbered bit of the M bits that is symmetric on the constellation diagram.
5. The method of claim 4, wherein the first target value in the LLR calculation for the first odd-bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd-bit includes:
the difference between the absolute value of the real part of the received signal and the value of the boundary; or alternatively
The absolute difference is the difference between the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
6. The method of claim 5, wherein the LLR for the first odd-bit is calculated by: 4r of 1 D；
The LLR calculation method for the second odd-numbered bit without a region symmetry line on the constellation diagram is as follows: -4D (| r) 1 |-Δ)；
The LLR calculation method of the second odd-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 Is the real part, delta is the value of the dividing line, delta i Dereferencing at least one symmetry line corresponding to the second odd-numbered bit, | | r 1 |-δ i And | represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
7. The method of claim 6, wherein LLRs for the second odd-bit bits for which there are 1 region symmetry lines on the constellation diagram are calculated as: -4D (| | r) 1 |-δ 1 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 2 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-Δ)；
The LLR calculation method for the second odd-numbered bit having 3 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 area symmetry lines are respectively taken.
8. The method of claim 2, wherein the LLRs for even-numbered bits of the M bits are calculated by: multiplying the second constant by a second target value;
the second constant is determined in accordance with the symmetry;
the second target value is determined based on an imaginary part of the received signal, or the second target value is determined based on at least one of the dividing line and the area symmetry line, and the imaginary part of the received signal.
9. The method of claim 8 wherein the LLR calculation for the first even-bit bits is such that the second constant is a positive number;
the second constant is a negative number in the LLR calculation method for the second even-numbered bit.
The first even-numbered bit is an even-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second even-numbered bit is an even-numbered bit of the M bits that is symmetric on the constellation diagram.
10. The method of claim 9, wherein the second target value in the LLR calculation for the first even-bit bits is an imaginary part of the received signal;
the second target value in the LLR calculation method for the second even-numbered bit includes:
a difference between an absolute value of an imaginary part of the received signal and a value of a boundary; or
A difference between an absolute difference value and the dividing line value, wherein the absolute difference value is an absolute value of a difference between an absolute value of an imaginary part of the received signal and the symmetrical line value;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
11. The method of claim 10, wherein the LLR for the first even-bit bits is calculated by: 4r 2 D；
The LLR calculation method of the second even-numbered bit without the region symmetry line on the constellation diagram is as follows: -4D (| r) 2 |-Δ)；
The LLR calculation method of the second even-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, Δ is the value of the dividing line, δ i Dereferencing for at least one symmetry line corresponding to the second even-numbered bit, | | r 2 |-δ i And | represents the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line.
12. The method of claim 11, wherein LLRs for the second even bit bits for which there are 1 region symmetry lines on the constellation diagram are calculated by: -4D (| | r) 2 |-δ 1 |-Δ)；
The LLR calculation method of the second even-numbered bit having 2 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-Δ)；
The LLR calculation method of the second even-numbered bit having 3 region symmetry lines on the constellation diagram is as follows: -4D (| | | r) 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And 3 region symmetry lines are respectively taken.
13. A communication device, comprising: a memory, a transceiver, and a processor, wherein:
a memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the following operations:
determining constellation map information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer larger than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation map information, wherein the LLR calculation mode of at least one bit in the M bits is calculated by adopting 1 piecewise function;
and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any one of the M bits.
14. The communications device of claim 13, wherein said constellation information includes at least one of:
symmetry on a constellation diagram, a boundary on the constellation diagram, and a region symmetry line on the constellation diagram;
the constellation diagram corresponds to the modulation mode.
15. The communications device of claim 14, wherein the LLR for odd-numbered bits of the M bits is calculated by: multiplying the first constant by a first target value;
the first constant is determined in accordance with the symmetry;
the first target value is determined based on a real part of the received signal, or the first target value is determined based on at least one of the boundary and the regional symmetry line, and the real part of the received signal.
16. The communication device of claim 15, wherein the LLR calculation for the first odd-bit is such that the first constant is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd-numbered bit;
the first odd-numbered bit is an odd-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second odd-numbered bit is an odd-numbered bit of the M bits that is symmetric on the constellation diagram.
17. The communications device of claim 16, wherein the first target value in the LLR calculation for the first odd-bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd-bit includes:
the difference between the absolute value of the real part of the received signal and the value of the boundary; or
The absolute difference value is the absolute value of the difference value between the real part of the received signal and the value of the symmetric line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
18. The communications device of claim 17, wherein the LLR for the first odd-bit is calculated by: 4r 1 D；
The LLR calculation method for the second odd-numbered bit without a region symmetry line on the constellation map is as follows: -4D (| r) 1 |-Δ)；
The LLR calculation method of the second odd-numbered bit having the region symmetry line on the constellation diagram is as follows: -4D (| | r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 Is the real part, delta is the value of the dividing line, delta i Dereferencing at least one symmetry line corresponding to the second odd-numbered bit, | | r 1 |-δ i And | represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
19. The communications device of claim 14 wherein the LLRs for the even-numbered bits of the M bits are calculated by: multiplying the second constant by a second target value;
the second constant is determined in accordance with the symmetry;
the second target value is determined based on an imaginary part of the received signal, or the second target value is determined based on at least one of the dividing line and the area symmetry line, and the imaginary part of the received signal.
20. The communication device of claim 19, wherein the LLR calculation for the first even-numbered bits is such that the second constant is a positive number;
the second constant is a negative number in the LLR calculation method for the second even-numbered bit.
The first even-numbered bit is an even-numbered bit of the M bits that is asymmetric on the constellation diagram;
the second even-numbered bit is an even-numbered bit of the M bits that is symmetric on the constellation diagram.
21. A communication device, comprising:
a first determining module, configured to determine constellation map information of each bit of M bits, where the M bits are M bits corresponding to a modulation scheme in a received signal, and M is an integer greater than 1;
a second determining module, configured to determine, according to the constellation information, a log-likelihood ratio LLR calculation manner for each bit, where an LLR calculation manner for at least one bit of the M bits is calculated by using 1 piece function;
and the calculation module is used for calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any one bit in the M bits.
22. The communications device of claim 21, wherein said constellation information includes at least one of:
symmetry on a constellation diagram, a boundary on the constellation diagram, and a region symmetry line on the constellation diagram;
the constellation diagram corresponds to the modulation mode.
23. The communications device of claim 22, wherein the LLRs for odd-numbered bits of the M bits are calculated by: multiplying the first constant by a first target value;
the first constant is determined in accordance with the symmetry;
the first target value is determined based on a real part of the received signal, or the first target value is determined based on at least one of the boundary and the regional symmetry line, and the real part of the received signal.
24. The communications device of claim 22, wherein LLRs for even bits of the M bits are calculated by: multiplying the second constant by a second target value;
the second constant is determined in accordance with the symmetry;
the second target value is determined based on an imaginary part of the received signal, or the second target value is determined based on at least one of the dividing line and the area symmetry line, and the imaginary part of the received signal.
25. A processor-readable storage medium, characterized in that the processor-readable storage medium stores a computer program for causing the processor to execute the signal demodulation processing method according to any one of claims 1 to 12.
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