CN115242588B - Signal demodulation processing method, communication device, and storage medium - Google Patents

Signal demodulation processing method, communication device, and storage medium Download PDF

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CN115242588B
CN115242588B CN202110447697.7A CN202110447697A CN115242588B CN 115242588 B CN115242588 B CN 115242588B CN 202110447697 A CN202110447697 A CN 202110447697A CN 115242588 B CN115242588 B CN 115242588B
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bit
value
constellation
bits
llr
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CN115242588A (en
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李传军
宋月霞
张艳
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Datang Mobile Communications Equipment Co Ltd
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Datang Mobile Communications Equipment Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2649—Demodulators

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

本发明提供一种信号解调处理方法、通信设备和存储介质，该方法包括：确定M个比特中每个比特的星座图信息，所述M个比特为接收信号中与调制方式对应的M个比特，M为大于1的整数；依据所述星座图信息，确定每个比特的对数似然比LLR计算方式，所述M个比特中至少一个比特的LLR计算方式为采用1个分段函数进行计算；依据目标比特的LLR计算方式，计算所述目标比特的LLR值，所述目标比特为所述M个比特中的任一比特。本发明可以提高计算比特的LLR值的计算效率。

The present invention provides a signal demodulation processing method, communication equipment and storage medium, the method comprising: determining constellation diagram information of each bit in M bits, the M bits are M bits corresponding to the modulation mode in the received signal, and M is an integer greater than 1; determining the log likelihood ratio LLR calculation method of each bit according to the constellation diagram information, the LLR calculation method of at least one bit in the M bits is to use a piecewise function for calculation; according to the LLR calculation method of the target bit, calculating the LLR value of the target bit, the target bit is any bit in the M bits. The present invention can improve the calculation efficiency of calculating the LLR value of the bit.

Description

Signal demodulation processing method, communication device, and storage medium
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a signal demodulation processing method, a communication device, and a storage medium.
Background
After the communication device acquires the received signal, the communication device demodulates the received signal to obtain demodulation information of the received signal. The demodulation of the received signal includes calculating Log-likelihood Ratio (LLR) values of bits of the received signal. However, when calculating the LLR value of a bit, the LLR calculation mode corresponding to each bit is to calculate by using a plurality of piecewise functions, that is, the LLR calculation formula of each bit includes a plurality of piecewise functions, for example: the LLR values are calculated for 10 bits, and 130 piecewise functions are included in the LLR calculation method corresponding to the 10 bits. The LLR calculation mode adopts excessive piecewise functions, so that the calculation efficiency of LLR values of calculation bits is low.
Disclosure of Invention
The embodiment of the invention provides a signal demodulation processing method, communication equipment and a storage medium, which are used for solving the problem of low calculation efficiency of calculating LLR values of bits.
The embodiment of the invention provides a signal demodulation processing method, which comprises the following steps:
determining constellation information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the LLR calculation mode of at least one bit in M bits is calculated by adopting 1 piecewise function;
and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any bit in the M bits.
Optionally, the constellation information includes at least one of:
symmetry on a constellation, a dividing line on the constellation, and a regional symmetry line on the constellation;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method for the odd bit in the M bits is: multiplying a first constant by a first target value;
the first constant is determined from the symmetry;
The first target value is determined from the real part of the received signal or from at least one of the dividing line and the region symmetry line, and the real part of the received signal.
Optionally, in the LLR calculation mode of the first odd bit, the first constant is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd bit;
the first odd-bit is an odd-bit of the M bits that is asymmetric on the constellation;
the second odd-bit is an odd-bit of the M bits that is symmetrical on the constellation.
Optionally, the first target value in the LLR calculation mode of the first odd bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd bit includes:
the absolute value of the real part of the received signal is different from the boundary line; or alternatively
The absolute difference value is the difference value between the absolute value of the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method for the first odd bit is: 4r 1 D；
The LLR calculation mode of the second odd bit without the area symmetry line on the constellation diagram is as follows: -4D (|r) 1 |-Δ)；
The LLR calculation mode of the second odd bit with the area symmetry line on the constellation diagram is as follows: -4D (||r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 For the real part, delta is the dividing line value, delta i Valuing at least one symmetry line corresponding to the second odd bit, ||r 1 |-δ i And I represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
Optionally, the LLR calculation method for the second odd bit having 1 region symmetry line on the constellation is as follows: -4D (||r) 1 |-δ 1 |-Δ)；
The LLR for the second odd bit with 2 regional symmetry lines on the constellation is calculated by: -4D% r is I R 1 |-δ 1 |-δ 2 |-Δ)；
There are 3 regional symmetries on the constellationThe LLR calculation mode of the second odd bit of the line is as follows: -4D (|) r is I R 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
Optionally, the LLR calculation method for the even bit in the M bits is: multiplying the second constant by a second target value;
the second constant is determined from the symmetry;
The second target value is determined in accordance with an imaginary part of the received signal or in accordance with at least one of the dividing line and the region symmetry line, and the imaginary part of the received signal.
Optionally, in the LLR calculation mode of the first even bit, the second constant is a positive number;
the second constant is negative in the LLR calculation mode for the second even bit.
The first even bit is an even bit of the M bits that is asymmetric on the constellation;
the second even bit is an even bit of the M bits that is symmetrical on the constellation.
Optionally, the second target value in the LLR calculation mode of the first even bit is an imaginary part of the received signal;
the second target value in the LLR calculation mode for the second even bit includes:
a difference between the absolute value of the imaginary part of the received signal and the boundary value; or alternatively
The absolute difference value is the difference value between the absolute value of the imaginary part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method for the first even bit is: 4r 2 D；
The LLR for the second even bit bits for which there is no regional symmetry line on the constellation is calculated by: -4D (|r) 2 |-Δ)；
The LLR for the second even bit bits with a regional symmetry line on the constellation is calculated by: -4D (||r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, delta is the boundary value, delta i Valuing at least one symmetry line corresponding to the second even bit, ||r 2 |-δ i And the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line is represented.
Optionally, the LLR calculation method for the second even bit having 1 region symmetry line on the constellation is as follows: -4D (||r) 2 |-δ 1 |-Δ)；
The LLR for the second even bit with 2 regional symmetry lines on the constellation is calculated by: -4D% r is I R 2 |-δ 1 |-δ 2 |-Δ)；
The LLR for the second even bit with 3 regional symmetry lines on the constellation is calculated by: -4D (|) r is I R 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
The embodiment of the invention also provides a communication device, which comprises: memory, transceiver, and processor, wherein:
a memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the following operations:
Determining constellation information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the LLR calculation mode of at least one bit in M bits is calculated by adopting 1 piecewise function;
and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any bit in the M bits.
Optionally, the constellation information includes at least one of:
symmetry on a constellation, a dividing line on the constellation, and a regional symmetry line on the constellation;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method for the odd bit in the M bits is: multiplying a first constant by a first target value;
the first constant is determined from the symmetry;
the first target value is determined from the real part of the received signal or from at least one of the dividing line and the region symmetry line, and the real part of the received signal.
Optionally, in the LLR calculation mode of the first odd bit, the first constant is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd bit;
the first odd-bit is an odd-bit of the M bits that is asymmetric on the constellation;
the second odd-bit is an odd-bit of the M bits that is symmetrical on the constellation.
Optionally, the first target value in the LLR calculation mode of the first odd bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd bit includes:
the absolute value of the real part of the received signal is different from the boundary line; or alternatively
The absolute difference value is the difference value between the absolute value of the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method for the first odd bit is: 4r 1 D；
The LLR calculation mode of the second odd bit without the area symmetry line on the constellation diagram is as follows: -4D (|r) 1 |-Δ)；
The LLR calculation mode of the second odd bit with the area symmetry line on the constellation diagram is as follows: -4D (||r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 For the real part, delta is the dividing line value, delta i Valuing at least one symmetry line corresponding to the second odd bit, ||r 1 |-δ i And I represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
Optionally, the LLR calculation method for the even bit in the M bits is: multiplying the second constant by a second target value;
the second constant is determined from the symmetry;
the second target value is determined in accordance with an imaginary part of the received signal or in accordance with at least one of the dividing line and the region symmetry line, and the imaginary part of the received signal.
Optionally, in the LLR calculation mode of the first even bit, the second constant is a positive number;
the second constant is negative in the LLR calculation mode for the second even bit.
The first even bit is an even bit of the M bits that is asymmetric on the constellation;
the second even bit is an even bit of the M bits that is symmetrical on the constellation.
The embodiment of the invention also provides a communication device, which comprises:
a first determining module, configured to determine constellation information of each bit in M bits, where the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
the second determining module is used for determining a Log Likelihood Ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the LLR calculation mode of at least one bit in the M bits is calculated by adopting 1 piecewise function;
and the calculation module is used for calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any bit in the M bits.
Optionally, the constellation information includes at least one of:
symmetry on a constellation, a dividing line on the constellation, and a regional symmetry line on the constellation;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method for the odd bit in the M bits is: multiplying a first constant by a first target value;
the first constant is determined from the symmetry;
the first target value is determined from the real part of the received signal or from at least one of the dividing line and the region symmetry line, and the real part of the received signal.
Optionally, the LLR calculation method for the even bit in the M bits is: multiplying the second constant by a second target value;
the second constant is determined from the symmetry;
the second target value is determined in accordance with an imaginary part of the received signal or in accordance with at least one of the dividing line and the region symmetry line, and the imaginary part of the received signal.
The embodiment of the invention also provides a processor readable storage medium, and the processor readable storage medium stores a computer program, and the computer program is used for enabling the processor to execute the signal demodulation processing method provided by the embodiment of the invention.
In the embodiment of the invention, the constellation information of each bit in M bits is determined, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1; determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the number of piecewise functions of the LLR calculation mode of at least one bit in the M bits is 1; and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any bit in the M bits. Therefore, the LLR calculation mode of at least one bit in the M bits is to calculate by adopting 1 piecewise function, and compared with the LLR calculation mode of each bit in the prior art, the LLR calculation mode of each bit is to calculate by adopting a plurality of piecewise functions, and the LLR calculation efficiency of calculating the bit can be improved due to the reduction of the number of the piecewise functions.
Drawings
FIG. 1 is a schematic diagram of a network architecture to which the present invention is applicable;
fig. 2 is a flowchart of a signal demodulation processing method according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 5 is a schematic diagram of another distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 7 is a schematic diagram of another distribution of bits on a constellation diagram according to an embodiment of the present invention;
fig. 8 is a block diagram of a communication device according to an embodiment of the present invention;
fig. 9 is a block diagram of another communication device according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
In the embodiment of the invention, the term "and/or" describes the association relation of the association objects, which means that three relations can exist, for example, a and/or B can be expressed as follows: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, and it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The embodiment of the invention provides a signal demodulation processing method, communication equipment and a storage medium, which are used for solving the problem of low calculation efficiency of LLR values of calculation bits.
The method and the device are based on the same application, and because the principles of solving the problems by the method and the device are similar, the implementation of the device and the method can be referred to each other, and the repetition is not repeated.
The technical scheme provided by the embodiment of the invention can be suitable for various systems, in particular to a 6G system. For example, applicable systems may be global system for mobile communications (global system of mobile communication, GSM), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (Wideband Code Division Multiple Access, WCDMA) universal packet Radio service (general packet Radio service, GPRS), long term evolution (long term evolution, LTE), LTE frequency division duplex (frequency division duplex, FDD), LTE time division duplex (time division duplex, TDD), long term evolution-advanced (long term evolution advanced, LTE-a), universal mobile system (universal mobile telecommunication system, UMTS), worldwide interoperability for microwave access (worldwide interoperability for microwave access, wiMAX), 5G New air interface (New Radio, NR), 6G, and the like. Terminal devices and network devices are included in these various systems. Core network parts such as evolved packet system (Evloved Packet System, EPS), 5G system (5 GS) etc. may also be included in the system.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a network architecture applicable to the implementation of the present invention, as shown in fig. 1, including a terminal 11 and a network device 12.
The terminal according to the embodiment of the invention can be a device for providing voice and/or data connectivity for a user, a handheld device with a wireless connection function, or other processing devices connected to a wireless modem, etc. The names of the terminal devices may also be different in different systems, for example in a 5G system, the terminal devices may be referred to as User Equipment (UE). The wireless terminal device may communicate with one or more Core Networks (CNs) via a radio access Network (Radio Access Network, RAN), which may be mobile terminal devices such as mobile phones (or "cellular" phones) and computers with mobile terminal devices, e.g., portable, pocket, hand-held, computer-built-in or vehicle-mounted mobile devices that exchange voice and/or data with the radio access Network. Such as personal communication services (Personal Communication Service, PCS) phones, cordless phones, session initiation protocol (Session Initiated Protocol, SIP) phones, wireless local loop (Wireless Local Loop, WLL) stations, personal digital assistants (Personal Digital Assistant, PDAs), redcap terminals, and the like. The wireless terminal device may also be referred to as a system, subscriber unit (subscriber unit), subscriber station (subscriber station), mobile station (mobile), remote station (remote station), access point (access point), remote terminal device (remote terminal), access terminal device (access terminal), user terminal device (user terminal), user agent (user agent), user equipment (user device), and embodiments of the present invention are not limited in this respect.
The network device according to the embodiment of the present invention may be a base station, where the base station may include a plurality of cells for providing services for the terminal. A base station may also be called an access point or may be a device in an access network that communicates over the air-interface, through one or more sectors, with wireless terminal devices, or other names, depending on the particular application. The network device may be operable to exchange received air frames with internet protocol (Internet Protocol, IP) packets as a router between the wireless terminal device and the rest of the access network, which may include an Internet Protocol (IP) communication network. The network device may also coordinate attribute management for the air interface. For example, the network device according to the embodiment of the present invention may be a network device (Base Transceiver Station, BTS) in a global system for mobile communications (Global System for Mobile communications, GSM) or code division multiple access (Code Division Multiple Access, CDMA), a network device (NodeB) in a wideband code division multiple access (Wide-band Code Division Multiple Access, WCDMA), an evolved network device (evolutional Node B, eNB or e-NodeB) in a long term evolution (long term evolution, LTE) system, a 5G base station (gNB) in a 5G network architecture (next generation system), a base station in 6G, a home evolved base station (Home evolved Node B, heNB), a relay node (relay node), a home base station (femto), a pico base station (pico), etc., which are not limited in the embodiment of the present invention. In some network structures, the network device may include a Centralized Unit (CU) node and a Distributed Unit (DU) node, which may also be geographically separated.
Multiple-input Multiple-output (Multi Input Multi Output, MIMO) transmissions, which may be Single-User MIMO (SU-MIMO) or Multiple-User MIMO (MU-MIMO), may each be performed between a network device and a terminal using one or more antennas. The MIMO transmission may be 2D-MIMO, 3D-MIMO, FD-MIMO, or massive-MIMO, or may be diversity transmission, precoding transmission, beamforming transmission, or the like, depending on the form and number of the root antenna combinations.
Referring to fig. 2, fig. 2 is a flowchart of a signal demodulation processing method according to an embodiment of the present invention, as shown in fig. 2, including the following steps:
step 201, determining constellation information of each bit in M bits, where M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
step 202, determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the LLR calculation mode of at least one bit in M bits is calculated by adopting 1 piecewise function;
step 203, calculating LLR values of target bits according to LLR calculation modes of the target bits, wherein the target bits are any one bit of the M bits.
The received signal is a received signal acquired by a communication device, and the communication device may be a terminal or a network side device.
In the embodiment of the present invention, the number of bits corresponding to different modulation modes may be different, for example: if quadrature phase shift keying (Quadrature Phase Shift Keying, QPSK) modulation, the corresponding number of bits m=2; in the case of 16 quadrature amplitude modulation (Quadrature Amplitude Modulation, QAM), the corresponding number of bits m=4; if 64QAM, the corresponding number of bits m=6; if 256QAM, the corresponding number of bits m=8; if 1024QAM, the corresponding number of bits m=10; in the case of 2048QAM, the corresponding number of bits m=12.
The modulation method in the step 201 may be set according to the actual requirement. The M bits may be specifically determined according to the relationship. It should be noted that, in the embodiment of the present invention, the correspondence between the modulation mode and the bit number is not limited, and the correspondence may be specifically configured or predefined according to the actual requirement.
In addition, in the embodiment of the present invention, different modulation modes correspond to respective constellations, and specifically, a constellation defined by a protocol for each modulation mode may be adopted. The constellation information of each bit is distribution characteristic information of each bit on a constellation corresponding to the modulation scheme. For example: symmetry on a constellation, a dividing line on the constellation, a region symmetry line on the constellation, etc. In addition, the constellation information of each of the M bits is determined according to a preset rule, or the constellation information of each of the M bits is preconfigured. For example: the first of the M bits is asymmetric in the constellation and has no area symmetry line, the second of the M bits is asymmetric in the constellation and has no area symmetry line, the third of the M bits is symmetric in the constellation and has no area symmetry line, the fourth of the M bits is symmetric in the constellation and has no area symmetry line, the fifth of the M bits is symmetric in the constellation and has a dividing line and an area symmetry line, the sixth of the M bits is symmetric in the constellation and has a dividing line and an area symmetry line, etc., not listed here.
The above-mentioned method for determining the LLR calculation for each bit according to the constellation information may be a method for determining the respective LLR calculation for each bit according to the constellation information of each bit, that is, the LLR calculation for each bit is associated with the respective constellation information. In particular, constants associated with the constellation in the LLR calculation mode, which is composed of the constants and the real part or the imaginary part of the received signal, may be determined according to the constellation information of the bits. In the embodiment of the invention, the LLR calculation mode may be an LLR calculation formula, that is, an LLR calculation mode is adopted to calculate LLR values.
In the embodiment of the present invention, the LLR calculation manner of at least one of the M bits is to calculate using 1 piecewise function, which may be understood that the number of piecewise functions of the LLR calculation formula of at least one of the M bits is 1, for example: the number of piecewise functions of the LLR calculation formula for each of the M bits is 1, which can further improve the calculation efficiency. Of course, in some embodiments or scenarios, the number of piecewise functions of the partial bit LLR calculation formula may be 1, and the other partial bit LLR calculation formula may include a plurality of piecewise functions, which may also improve the calculation efficiency. In addition, in the embodiment of the present invention, the piecewise function may also be referred to as a branching function.
The calculating the LLR values of the target bits according to the LLR calculation method of the target bits may be calculating the LLR values of each bit by using a respective LLR calculation method to obtain the LLR values of the M bits.
In the embodiment of the invention, the LLR calculation mode of M bits can be determined through the steps, and the LLR calculation mode of at least one bit in the M bits is calculated by adopting 1 piecewise function, so that compared with the LLR calculation mode of each bit in the prior art, the LLR calculation mode of each bit is calculated by adopting a plurality of piecewise functions, the LLR calculation efficiency of calculating the LLR values of the bits can be improved due to the reduction of the number of the piecewise functions, and further, the cost of hardware resources can be saved due to the reduction of the number of the piecewise functions in the LLR calculation mode.
As an alternative embodiment, the constellation information includes at least one of:
symmetry on a constellation, a dividing line on the constellation, and a regional symmetry line on the constellation;
the constellation diagram corresponds to the modulation mode.
The symmetry on the constellation may indicate whether the bits are symmetrical on the constellation, and further, may indicate whether the bits are symmetrical on a specific coordinate axis on the constellation. For example: the symmetry in the constellation can be expressed as r of bits in the constellation 1 =0 or r 2 =0 is symmetry of the symmetry axis.
The above-mentioned boundary line on the constellation diagram may be a boundary line of bits between 0 and 1 or a boundary line of 1 and-1 corresponding to the constellation diagram.
The region symmetry line on the constellation may be a symmetry line of a bit in a partial region in the constellation.
The following is illustrated with odd ones of the M bits:
m/2 odd bits of the M bits are: a, a n N=1, 2, …, M/2, i.e. (a) 1 ,a 2 ,…,a M/2 ) The bits are represented by r on the constellation diagram 1 =0 is symmetry of symmetry axis, parting line, and regional symmetry line.
For n=1, i.e. the first odd bit, r is not taken as 1 Symmetric about 0, the bit boundary is r 1 The number of the regional symmetry lines of the bit is 0, and the regional symmetry lines are absent. For example: taking a modulation scheme of 1024QAM as an example, the bit (i.e. a 1 Bits) may be distributed over a constellation as shown in fig. 3, without r 1 =0 bilateral symmetry, dividing line r 1 The number of the regional symmetry lines is 0, i.e. the regional symmetry lines are absent.
For n=2, the second odd bit, r 1 Symmetric about 0, the bit boundary is r 1 =Δ, and Δ=2 (M/2-1) And D, the number of the regional symmetry lines of the bit is 0, and the regional symmetry lines are absent.
In this embodiment, D is an energy normalization factor of a constellation point, and for a given constellation point, D is a constant, for example: if the modulation scheme is QPSK, thenIf the modulation scheme is 16QAM, then +.>If the modulation scheme is 64QAM, then +.>If the modulation scheme is 256QAM, then +.>If the modulation scheme is 1024QAM, then
For example: taking a modulation scheme of 1024QAM as an example, n=2 bits (i.e., a 2 Bits) may be distributed over a constellation diagram as shown in fig. 4, with r 1 =0 bilateral symmetry, dividing line r 1 The number of the regional symmetry lines is 0, and the regional symmetry lines are absent.
For n>=3, i.e. for the 3 rd odd bit and the odd bit following the 3 rd odd bit, r 1 Symmetric about=0, the bit boundaries are r 1 ＝Δ，Δ＝2 (M/2-1-(n-2)) D, the number of the symmetry lines of the bit regions is n-2, and the symmetry line of the region is r 1 ＝δ i And delta i ＝2 (M/2-1-(i-1)) D,i＝1,…,n-2。
For example: taking a modulation scheme of 1024QAM as an example, n=3 bits (a 3 Bits) on the constellation can be as shown in fig. 5, with r 1 =0 bilateral symmetry, dividing line r 1 =Δ, Δ=8d, the number of regional symmetry lines is 1, and the regional symmetry line is r 1 ＝δ 1 And delta 1 ＝16D。
For example: taking a modulation scheme of 1024QAM as an example, n=4 bits (a 4 Bits) on the constellation can be as shown in fig. 6, with r 1 =0 bilateral symmetry, dividing line r 1 =Δ, Δ=4d, the number of regional symmetry lines is 2, and the regional symmetry line is r 1 ＝δ 1 And r 1 ＝δ 2 And delta 1 =16d, and δ 2 ＝8D。
For example: taking a modulation scheme of 1024QAM as an example, n=5 bits (a 5 Bits) on the constellation can be as shown in fig. 7, with r 1 =0 bilateral symmetry, dividing line r 1 =Δ, Δ=2d, the number of regional symmetry lines is 3, and the regional symmetry line is r 1 ＝δ 1 ，r 1 ＝δ 2 And r 1 ＝δ 3 And delta 1 ＝16D，δ 2 =8d, and δ 3 ＝4D。
The following is further exemplified by even bits of the M bits:
m/2 even bits of the M bits are: b n N=1, 2, …, M/2, i.e. (b) 1 ,b 2 ,…,b M/2 ) The bits are represented by r on the constellation diagram 2 =0 is symmetry of symmetry axis, parting line, and regional symmetry line.
For n=1, i.e. the first even bit, r is not taken as 2 Symmetric about 0, the bit boundary is r 2 The number of the regional symmetry lines of the bit is 0, and the regional symmetry lines are absent.
For n=2, the second even bit, r 2 Symmetric about 0, the bit boundary is r 2 =Δ, and Δ=2 (M/2-1) And D, the number of the regional symmetry lines of the bit is 0, and the regional symmetry lines are absent.
For n>=3, i.e. for the 3 rd even bit and the even bit after the 3 rd even bit, r 2 Symmetric about=0, the bit boundaries are r 2 ＝Δ，Δ＝2 (M/2-1-(n-2)) D, the number of the symmetry lines of the bit regions is n-2, and the symmetry line of the region is r 2 ＝δ i And delta i ＝2 (M/2-1-(i-1)) D,i＝1,…,n-2。
In the embodiment of the present invention, the distribution of each bit in the M bits on the constellation map is determined according to a modulation rule, or is preconfigured, or is predefined by a protocol.
As an optional implementation manner, the LLR calculation manner of the odd bit of the M bits is: multiplying a first constant by a first target value;
the first constant is determined from the symmetry;
the first target value is determined from the real part of the received signal or from at least one of the dividing line and the region symmetry line, and the real part of the received signal.
Wherein, the LLR calculation mode of the odd bit in the M bits is as follows: the first constant is multiplied by the first target value so that the LLR for the odd bits can be calculated using 1 piecewise function, since the first constant is multiplied by the first target value as a piecewise function.
The first constant may be a predetermined constant determined according to symmetry, for example: 4D or-4D, it should be noted that 4D or-4D herein is only an alternative embodiment, such as: in some scenarios or embodiments, it may also be: 8D or-8D, 2D or-2D, etc., which can be specifically set according to actual requirements or predefined by a protocol.
The first target value may be determined according to the real part of the received signal, and may be determined according to only the real part of the received signal, for example, the first target value is the real part of the received signal.
The first target value may be determined based on at least one of the dividing line and the region symmetry line, and the real part of the received signal, and the first target value may be calculated based on at least one of the dividing line and the region symmetry line, and the real part of the received signal.
In this embodiment, since the LLR calculation mode is that the first constant is multiplied by the first target value, the LLR calculation mode can be calculated by using 1 piecewise function, and the LLR calculation mode can be simplified, so that the calculation efficiency can be further improved. Note that in the embodiment of the present invention, the LLR calculation method for the odd bit of the M bits is not limited to: the first constant is multiplied by a first target value, such as: in some scenarios or services, the LLR for the odd bits is calculated by: the first constant is multiplied by a first target value and added with the constant, and the constant can be associated with the service and the scene, so that different LLR calculation modes can be adopted for realizing different services and scenes.
Optionally, in the LLR calculation mode of the first odd bit, the first constant is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd bit;
the first odd-bit is an odd-bit of the M bits that is asymmetric on the constellation;
the second odd-bit is an odd-bit of the M bits that is symmetrical on the constellation.
The first odd bit may be a first odd bit of the M bits, because the first odd bit is asymmetric in the constellation diagram, and the second odd bit may include two, third, fourth, fifth, etc. odd bits, which are symmetric in the constellation diagram.
For example: the first odd bit is asymmetric on the constellation diagram, the first constant in the LLR calculation mode of the bit is 4D, the second, third, fourth and other odd bit is symmetric on the constellation diagram, and the first constant in the LLR calculation mode of the bit is-4D.
Optionally, the first target value in the LLR calculation mode of the first odd bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd bit includes:
The absolute value of the real part of the received signal is different from the boundary line; or alternatively
The absolute difference value is the difference value between the absolute value of the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
The absolute value of the absolute difference value, which is the difference between the absolute value of the real part of the received signal and the symmetry line value, may include at least one of:
for a bit with only one symmetry line, the absolute difference of the bit is: the absolute value of the difference between the absolute value of the real part of the received signal and the value of the symmetry line;
for a bit with two symmetry lines, the absolute difference of the bit is the absolute difference obtained by: subtracting the value of one symmetry line from the absolute value of the real part of the received signal, subtracting the value of the other symmetry line from the absolute value of the difference, and taking the absolute value of the difference;
for three or more bits of symmetry, the absolute difference of the bits is the absolute difference obtained by: subtracting the value of one symmetry line from the absolute value of the real part of the received signal, subtracting the value of the other symmetry line from the absolute value of the difference, and subtracting the values of all symmetry lines until the values of all symmetry lines are subtracted, and finally subtracting the absolute value from the absolute value of the final difference.
In this embodiment, the LLR calculation mode for the first odd bit may be implemented as follows: the first constant is multiplied by the real part of the received signal, and the LLR of the second odd bit is calculated by the following method: the difference between the absolute value of the real part of the received signal and the boundary value is multiplied by the first constant, or the difference between the absolute value and the boundary value is multiplied by the first constant, so that the calculation efficiency can be improved.
For example: taking the first constant as 4D or-4D as an example, the LLR calculation method of the first odd bit is as follows: 4r 1 D；
The LLR calculation mode of the second odd bit without the area symmetry line on the constellation diagram is as follows: -4D (|r) 1 |-Δ)；
The LLR calculation mode of the second odd bit with the area symmetry line on the constellation diagram is as follows: -4D (||r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 For the real part, delta is the dividing line value, delta i And taking the value of at least one symmetrical line corresponding to the second odd bit.
Wherein ||r 1 |-δ i And I represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line. For example: the absolute difference for the second odd bit, where there are 1 regional symmetry lines on the constellation, is r 1 |-δ 1 I (I); the absolute difference for the second odd bit for which there are 2 regional symmetry lines on the constellation is: r is I R 1 |-δ 1 |-δ 2 I (I); the absolute difference for the second odd bit where there are 3 regional symmetry lines on the constellation is: i r is |r 1 |-δ 1 |-δ 2 |-δ 3 I (I); wherein delta 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
Optionally, the LLR calculation method for the second odd bit having 1 region symmetry line on the constellation is as follows: -4D (||r) 1 |-δ 1 |-Δ)；
The LLR for the second odd bit with 2 regional symmetry lines on the constellation is calculated by: -4D% r is I R 1 |-δ 1 |-δ 2 |-Δ)；
The LLR for the second odd bit with 3 regional symmetry lines on the constellation is calculated by: -4D (|) r is I R 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
In this embodiment, the above-described LLR calculation method can further improve the calculation efficiency.
For example: for n=1, i.e. the 1 st odd bit, r is not taken as 1 =0 bilateral symmetry, then LLR (a 1 )＝4r 1 D；
For n=2, i.e. the 2 nd odd bit, r 1 =0 bilateral symmetry, then LLR (a 2 )＝-4D(|r 1 I- Δ), where Δ=2 (M/2-1) D；
For n=3, i.e. the 3 rd odd bit, r 1 When=0 bilateral symmetry, the number of the region symmetry lines is n-2 and 1, and LLR (a 3 )＝-4D(||r 1 |-δ 1 I- Δ), wherein Δ=2 (M/2-2) D，δ 1 ＝2 (M/2-1) D；
For n=4, i.e. the 4 th odd bit, r 1 The number of the regional symmetry lines is =0 bilateral symmetryn-2 is 2, LLR (a 4 )＝-4D(|||r 1 |-δ 1 |-δ 2 I- Δ), wherein Δ=2 (M/2-3) D，δ 1 ＝2 (M/2-1) D, and delta 2 ＝2 (M/2-2) D。
For n=5, i.e. the 5 th odd bit, r 1 When=0 bilateral symmetry, the number of the region symmetry lines is n-2 and 3, and LLR (a 5 )＝-4D(||||r 1 |-δ 1 |-δ 2 |-δ 3 I- Δ), wherein Δ=2 (M/2-4) D，δ 1 ＝2 (M/2-1) D，δ 2 ＝2 (M/2-2) D, and delta 3 ＝2 (M/2-3) D。
Wherein r is 1 Is the real part of the received signal.
When the modulation mode is 1024QAM, m=10, and M bits are a 1 ,b 1 ,a 2 ,b 2 ,a 3 ,b 3 ,a 4 ,b 4 ,a 5 ,b 5 Then a 1 ,a 2 ,a 3 ,a 4 ,a 5 The LLR calculation method of (2) is as follows:
LLR(a 1 )＝4r 1 D；
LLR(a 2 )＝-4D(|r 1 |-16D)；
LLR(a 3 )＝-4D(||r 1 |-16D|-8D)；
LLR(a 4 )＝-4D(|||r 1 |-16D|-8D|-4D)；
LLR(a 5 )＝-4D(||||r 1 |-16D|-8D|-4D|-2D)。
it should be noted that the above description is mainly given with bits where there are no regional symmetry lines on the constellation, and bits where there are 1, 2, and 3 regional symmetry lines on the constellation, for example:
the LLR for the second odd bit with 4 regional symmetry lines on the constellation is calculated by: -4D (|) I r is |r 1 |-δ 1 |-δ 2 |-δ 3 |-δ 4 |-Δ)；
LLR meter for the second odd bit having 5 regional symmetry lines on the constellation diagramThe calculation method is as follows: -4D (||) I r is |r 1 |-δ 1 |-δ 2 |-δ 3 |-δ 4 |-δ 5 |-Δ)。
δ 1 ，δ 2 ，δ 3 ，δ 4 ，δ 5 And respectively taking values of 5 area symmetry lines.
Specific reference may be made to the above-mentioned-4D (||r) 1 |-δ i I- Δ), wherein i r 1 |-δ i And I represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
As an optional implementation manner, the LLR calculation manner of the even bit in the M bits is: multiplying the second constant by a second target value;
The second constant is determined from the symmetry;
the second target value is determined in accordance with an imaginary part of the received signal or in accordance with at least one of the dividing line and the region symmetry line, and the imaginary part of the received signal.
Wherein the second constant may be referred to in the description of the first constant, and in some embodiments, the second constant may be equal to the first constant, for example: the second constant may be 4D or-4D. The second target value may be referred to in the description of the first target data value, except that the real part of the first target data value is replaced by the imaginary part.
Optionally, in the LLR calculation mode of the first even bit, the second constant is a positive number;
the second constant is negative in the LLR calculation mode for the second even bit.
The first even bit is an even bit of the M bits that is asymmetric on the constellation;
the second even bit is an even bit of the M bits that is symmetrical on the constellation.
Wherein the symmetry can be represented by r of constellation diagram 2 Up-down symmetry of =0.
Optionally, the second target value in the LLR calculation mode of the first even bit is an imaginary part of the received signal;
the second target value in the LLR calculation mode for the second even bit includes:
a difference between the absolute value of the imaginary part of the received signal and the boundary value; or alternatively
The absolute difference value is the difference value between the absolute value of the imaginary part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
The second target value may refer to the description about the first target data value, where only the real part is replaced by the imaginary part in the first target data value.
Optionally, the LLR calculation method for the first even bit is: 4r 2 D；
The LLR for the second even bit bits for which there is no regional symmetry line on the constellation is calculated by: -4D (|r) 2 |-Δ)；
The LLR for the second even bit bits with a regional symmetry line on the constellation is calculated by: -4D (||r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, delta is the boundary value, delta i And taking the value of at least one symmetrical line corresponding to the second even bit.
Wherein ||r 2 |-δ i And the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line is represented. For example: the absolute difference for the second even bit with 1 region symmetry line on the constellation is ||r 2 |-δ 1 I (I); the absolute difference for the second even bit for which there are 2 regional symmetry lines on the constellation is: r is I R 2 |-δ 1 |-δ 2 I (I); for the presence of 3 region pairs on the constellationThe absolute difference of the second even bit of the line is: i r is |r 2 |-δ 1 |-δ 2 |-δ 3 I (I); wherein delta 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
The above 4r 2 D、-4D(|r 2 -delta) is-4D (|r) 2 |-δ i I-delta) are 3 different piecewise functions, respectively.
Optionally, the LLR calculation method for the second even bit having 1 region symmetry line on the constellation is as follows: -4D (||r) 2 |-δ 1 |-Δ)；
The LLR for the second even bit with 2 regional symmetry lines on the constellation is calculated by: -4D% r is I R 2 |-δ 1 |-δ 2 |-Δ)；
The LLR for the second even bit with 3 regional symmetry lines on the constellation is calculated by: -4D (|) r is I R 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
In this embodiment, the above-described LLR calculation method can further improve the calculation efficiency.
For example: for n=1, i.e. the 1 st even bit, r is not taken as 2 =0 up-down symmetry, then LLR (b 1 )＝4r 2 D；
For n=2, i.e. the 2 nd odd bit, r 2 =0 up-down symmetry, then LLR (b 2 )＝-4D(|r 2 I- Δ), where Δ=2 (M/2-1) D；
For n=3, i.e. the 3 rd even bit, r 2 When=0 is symmetric up and down, the number of the region symmetry lines is n-2 and 1, and LLR (b 3 )＝-4D(||r 2 |-δ 1 I- Δ), wherein Δ=2 (M/2-2) D，δ 1 ＝2 (M/2-1) D；
For n=4, i.e. the 4 th even bit, r 2 When=0 is symmetrical up and down, the number of the region symmetry lines is n-2 and 2LLR(b 4 )＝-4D(|||r 2 |-δ 1 |-δ 2 I- Δ), wherein Δ=2 (M/2-3) D，δ 1 ＝2 (M/2-1) D, and delta 2 ＝2 (M/2-2) D。
For n=5, i.e. the 5 th even bit, r 2 When=0 is symmetric up and down, the number of the region symmetry lines is n-2 and 3, and LLR (b 5 )＝-4D(||||r 2 |-δ 1 |-δ 2 |-δ 3 I- Δ), wherein Δ=2 (M/2-4) D，δ 1 ＝2 (M/2-1) D，δ 2 ＝2 (M/2-2) D, and delta 3 ＝2 (M/2-3) D。
Wherein r is 2 Is the imaginary part of the received signal.
When the modulation mode is 1024QAM, m=10, and M bits are a 1 ,b 1 ,a 2 ,b 2 ,a 3 ,b 3 ,a 4 ,b 4 ,a 5 ,b 5 B is then 1 ,b 2 ,b 3 ,b 4 ,b 5 The LLR calculation method of (2) is as follows:
LLR(b 1 )＝4r 2 D；
LLR(b 2 )＝-4D(|r 2 |-16D)；
LLR(b 3 )＝-4D(||r 2 |-16D|-8D)；
LLR(b 4 )＝-4D(|||r 2 |-16D|-8D|-4D)；
LLR(b 5 )＝-4D(||||r 2 |-16D|-8D|-4D|-2D)。
specifically, by the method provided by the embodiment of the present invention, when a 1024QAM modulation scheme is adopted, the M bits may be denoted as a 1 ,b 1 ,a 2 ,b 2 ,a 3 ,b 3 ,a 4 ,b 4 ,a 5 ,b 5 ，a 1 ,b 1 ,a 2 ,b 2 ,a 3 ,b 3 ,a 4 ,b 4 ,a 5 ,b 5 The LLR value mode of (2) is specifically as follows:
LLR(a 1 )＝4r 1 D
LLR(a 2 )＝-4D(|r 1 |-16D)
LLR(a 3 )＝-4D(||r 1 |-16D|-8D)
LLR(a 4 )＝-4D(|||r 1 |-16D|-8D|-4D)
LLR(a 5 )＝-4D(||||r 1 |-16D|-8D|-4D|-2D)
LLR(b 1 )＝4r 2 D
LLR(b 2 )＝-4D(|r 2 |-16D)
LLR(b 3 )＝-4D(||r 2 |-16D|-8D)
LLR(b 4 )＝-4D(|||r 2 |-16D|-8D|-4D)
LLR(b 5 )＝-4D(||||r 2 |-16D|-8D|-4D|-2D)
d is the energy normalization factor of the constellation point, for a given constellation point, D is a constant,
LLR is LLR value of each bit;
wherein a is 1 ,a 2 ,a 3 ,a 4 ,a 5 1 st to 5 th bits of constellation points with the same real part respectively, wherein b 1 ,b 2 ,b 3 ,b 4 ,b 5 1 st to 5 th bits of constellation points with the same imaginary part respectively; r is (r) 1 For receiving the real part of the signal r 2 For receiving an imaginary part of the signal;
in the embodiment of the invention, the number of the piecewise functions is reduced, so that the demodulation speed is increased, the time delay is reduced, and the hardware resource expenditure is reduced.
In the embodiment of the invention, the constellation information of each bit in M bits is determined, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1; determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the number of piecewise functions of the LLR calculation mode of at least one bit in the M bits is 1; and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any bit in the M bits. Therefore, the LLR calculation mode of at least one bit in the M bits is to calculate by adopting a piecewise function, so that the calculation efficiency of calculating the LLR value of the bit can be improved.
Referring to fig. 8, fig. 8 is a block diagram of a communication device according to an embodiment of the present invention, as shown in fig. 8, including a memory 820, a transceiver 800, and a processor 810:
A memory 820 for storing a computer program; a transceiver 800 for transceiving data under the control of the processor 810; a processor 810 for reading the computer program in the memory 820 and performing the following operations:
the embodiment of the invention provides a signal demodulation processing method, which comprises the following steps:
determining constellation information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the LLR calculation mode of at least one bit in M bits is calculated by adopting 1 piecewise function;
and calculating the LLR value of the target bit according to the LLR calculation mode of the target bit, wherein the target bit is any bit in the M bits.
Wherein in fig. 8, a bus architecture may comprise any number of interconnected buses and bridges, and in particular one or more processors represented by processor 810 and various circuits of memory represented by memory 820, linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and, therefore, will not be described further herein. The bus interface provides an interface. Transceiver 800 may be a number of elements, including a transmitter and a receiver, providing a means for communicating with various other apparatus over transmission media, including wireless channels, wired channels, optical cables, etc. The user interface 830 may also be an interface capable of interfacing with an inscribed desired device for a different user device, including but not limited to a keypad, display, speaker, microphone, joystick, etc.
The processor 810 is responsible for managing the bus architecture and general processing, and the memory 820 may store data used by the processor 800 in performing operations.
Alternatively, the processor 810 may be a CPU (Central processing Unit), ASIC (Application Specific Integrated Circuit ), FPGA (Field-Programmable Gate Array, field programmable Gate array) or CPLD (Complex Programmable Logic Device ), and the processor may also employ a multicore architecture.
The processor is operable to perform any of the methods provided by embodiments of the present invention in accordance with the obtained executable instructions by invoking a computer program stored in a memory. The processor and the memory may also be physically separate.
Optionally, the constellation information includes at least one of:
symmetry on a constellation, a dividing line on the constellation, and a regional symmetry line on the constellation;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method for the odd bit in the M bits is: multiplying a first constant by a first target value;
the first constant is determined from the symmetry;
the first target value is determined from the real part of the received signal or from at least one of the dividing line and the region symmetry line, and the real part of the received signal.
Optionally, in the LLR calculation mode of the first odd bit, the first constant is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd bit;
the first odd-bit is an odd-bit of the M bits that is asymmetric on the constellation;
the second odd-bit is an odd-bit of the M bits that is symmetrical on the constellation.
Optionally, the first target value in the LLR calculation mode of the first odd bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd bit includes:
the absolute value of the real part of the received signal is different from the boundary line; or alternatively
The absolute difference value is the difference value between the absolute value of the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method for the first odd bit is: 4r 1 D；
The LLR calculation mode of the second odd bit without the area symmetry line on the constellation diagram is as follows: -4D (|r) 1 |-Δ)；
The LLR calculation mode of the second odd bit with the area symmetry line on the constellation diagram is as follows: -4D (||r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 For the real part, delta is the dividing line value, delta i Valuing at least one symmetry line corresponding to the second odd bit, ||r 1 |-δ i And I represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
Optionally, the LLR calculation method for the second odd bit having 1 region symmetry line on the constellation is as follows: -4D (||r) 1 |-δ 1 |-Δ)；
LLR calculation method for the second odd bit having 2 regional symmetry lines on the constellation diagramThe formula is: -4D% r is I R 1 |-δ 1 |-δ 2 |-Δ)；
The LLR for the second odd bit with 3 regional symmetry lines on the constellation is calculated by: -4D (|) r is I R 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
Optionally, the LLR calculation method for the even bit in the M bits is: multiplying the second constant by a second target value;
the second constant is determined from the symmetry;
the second target value is determined in accordance with an imaginary part of the received signal or in accordance with at least one of the dividing line and the region symmetry line, and the imaginary part of the received signal.
Optionally, in the LLR calculation mode of the first even bit, the second constant is a positive number;
the second constant is negative in the LLR calculation mode for the second even bit.
The first even bit is an even bit of the M bits that is asymmetric on the constellation;
the second even bit is an even bit of the M bits that is symmetrical on the constellation.
Optionally, the second target value in the LLR calculation mode of the first even bit is an imaginary part of the received signal;
the second target value in the LLR calculation mode for the second even bit includes:
a difference between the absolute value of the imaginary part of the received signal and the boundary value; or alternatively
The absolute difference value is the difference value between the absolute value of the imaginary part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method for the first even bit is: 4r 2 D；
The LLR for the second even bit bits for which there is no regional symmetry line on the constellation is calculated by: -4D (|r) 2 |-Δ)；
The LLR for the second even bit bits with a regional symmetry line on the constellation is calculated by: -4D (||r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, delta is the boundary value, delta i Valuing at least one symmetry line corresponding to the second even bit, ||r 2 |-δ i And the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line is represented.
Optionally, the LLR calculation method for the second even bit having 1 region symmetry line on the constellation is as follows: -4D (||r) 2 |-δ 1 |-Δ)；
The LLR for the second even bit with 2 regional symmetry lines on the constellation is calculated by: -4D% r is I R 2 |-δ 1 |-δ 2 |-Δ)；
The LLR for the second even bit with 3 regional symmetry lines on the constellation is calculated by: -4D (|) r is I R 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
It should be noted that, the above communication device provided by the embodiment of the present invention can implement all the method steps implemented by the embodiment of the method and achieve the same technical effects, and the same parts and beneficial effects as those of the embodiment of the method in the embodiment are not described in detail herein.
Referring to fig. 9, fig. 9 is a block diagram of another communication device according to an embodiment of the present invention, as shown in fig. 9, a communication device 900 includes:
A first determining module 901, configured to determine constellation information of each of M bits, where the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
a second determining module 902, configured to determine, according to the constellation information, a log-likelihood ratio LLR calculation manner of each bit, where the LLR calculation manner of at least one bit of the M bits is calculated by using 1 piecewise function;
the calculating module 903 is configured to calculate an LLR value of a target bit according to an LLR calculation manner of the target bit, where the target bit is any bit of the M bits.
Optionally, the constellation information includes at least one of:
symmetry on a constellation, a dividing line on the constellation, and a regional symmetry line on the constellation;
the constellation diagram corresponds to the modulation mode.
Optionally, the LLR calculation method for the odd bit in the M bits is: multiplying a first constant by a first target value;
the first constant is determined from the symmetry;
the first target value is determined from the real part of the received signal or from at least one of the dividing line and the region symmetry line, and the real part of the received signal.
Optionally, in the LLR calculation mode of the first odd bit, the first constant is a positive number;
the first constant is a negative number in the LLR calculation mode of the second odd bit;
the first odd-bit is an odd-bit of the M bits that is asymmetric on the constellation;
the second odd-bit is an odd-bit of the M bits that is symmetrical on the constellation.
Optionally, the first target value in the LLR calculation mode of the first odd bit is a real part of the received signal;
the first target value in the LLR calculation method for the second odd bit includes:
the absolute value of the real part of the received signal is different from the boundary line; or alternatively
The absolute difference value is the difference value between the absolute value of the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method for the first odd bit is: 4r 1 D；
The LLR calculation mode of the second odd bit without the area symmetry line on the constellation diagram is as follows: -4D (|r) 1 |-Δ)；
The LLR calculation mode of the second odd bit with the area symmetry line on the constellation diagram is as follows: -4D (||r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 For the real part, delta is the dividing line value, delta i Valuing at least one symmetry line corresponding to the second odd bit, ||r 1 |-δ i And I represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
Optionally, the LLR calculation method for the second odd bit having 1 region symmetry line on the constellation is as follows: -4D (||r) 1 |-δ 1 |-Δ)；
The LLR for the second odd bit with 2 regional symmetry lines on the constellation is calculated by: -4D% r is I R 1 |-δ 1 |-δ 2 |-Δ)；
The LLR for the second odd bit with 3 regional symmetry lines on the constellation is calculated by: -4D (|) r is I R 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
Optionally, the LLR calculation method for the even bit in the M bits is: multiplying the second constant by a second target value;
the second constant is determined from the symmetry;
the second target value is determined in accordance with an imaginary part of the received signal or in accordance with at least one of the dividing line and the region symmetry line, and the imaginary part of the received signal.
Optionally, in the LLR calculation mode of the first even bit, the second constant is a positive number;
the second constant is negative in the LLR calculation mode for the second even bit.
The first even bit is an even bit of the M bits that is asymmetric on the constellation;
the second even bit is an even bit of the M bits that is symmetrical on the constellation.
Optionally, the second target value in the LLR calculation mode of the first even bit is an imaginary part of the received signal;
the second target value in the LLR calculation mode for the second even bit includes:
a difference between the absolute value of the imaginary part of the received signal and the boundary value; or alternatively
The absolute difference value is the difference value between the absolute value of the imaginary part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
Optionally, the LLR calculation method for the first even bit is: 4r 2 D；
The LLR for the second even bit bits for which there is no regional symmetry line on the constellation is calculated by: -4D (|r) 2 |-Δ)；
The LLR for the second even bit bits with a regional symmetry line on the constellation is calculated by: -4D (||r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, delta is the boundary value, delta i Valuing at least one symmetry line corresponding to the second even bit, ||r 2 |-δ i And the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line is represented.
Optionally, the LLR calculation method for the second even bit having 1 region symmetry line on the constellation is as follows: -4D (||r) 2 |-δ 1 |-Δ)；
The LLR for the second even bit with 2 regional symmetry lines on the constellation is calculated by: -4D% r is I R 2 |-δ 1 |-δ 2 |-Δ)；
The LLR for the second even bit with 3 regional symmetry lines on the constellation is calculated by: -4D (|) r is I R 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
It should be noted that, the above communication device provided by the embodiment of the present invention can implement all the method steps implemented by the embodiment of the method and achieve the same technical effects, and the same parts and beneficial effects as those of the embodiment of the method in the embodiment are not described in detail herein.
It should be noted that, in the embodiment of the present invention, the division of the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice. In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a processor-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The embodiment of the invention also provides a processor readable storage medium, and the processor readable storage medium stores a computer program, and the computer program is used for enabling the processor to execute the signal demodulation processing method provided by the embodiment of the invention.
The processor-readable storage medium may be any available medium or data storage device that can be accessed by a processor, including, but not limited to, magnetic storage (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical storage (e.g., CD, DVD, BD, HVD, etc.), semiconductor storage (e.g., ROM, EPROM, EEPROM, nonvolatile storage (NAND FLASH), solid State Disk (SSD)), and the like.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These processor-executable instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (17)

1. A signal demodulation processing method, characterized by comprising:
determining constellation information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the LLR calculation mode of at least one bit in M bits is calculated by adopting 1 piecewise function;
according to an LLR calculation mode of a target bit, calculating an LLR value of the target bit, wherein the target bit is any bit in the M bits;
the constellation information includes at least one of:
symmetry on a constellation, a dividing line on the constellation, and a regional symmetry line on the constellation;
the constellation diagram corresponds to the modulation mode;
the LLR calculation mode of the odd bit in the M bits is as follows: multiplying a first constant by a first target value;
the first constant is determined from the symmetry;
the first target value is determined from the real part of the received signal or from at least one of the dividing line and the region symmetry line, and the real part of the received signal;
The first target value in the LLR calculation mode of the first odd bit is the real part of the received signal;
the first target value in the LLR calculation method for the second odd bit includes:
the absolute value of the real part of the received signal is different from the boundary line; or alternatively
The absolute difference value is the difference value between the absolute value of the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
2. The method of claim 1 wherein the first constant is a positive number in the LLR calculation for the first odd bit;
the first constant is a negative number in the LLR calculation mode of the second odd bit;
the first odd-bit is an odd-bit of the M bits that is asymmetric on the constellation;
the second odd-bit is an odd-bit of the M bits that is symmetrical on the constellation.
3. The method of claim 1 wherein the LLR for the first odd bit is calculated by: 4r 1 D；
The LLR calculation mode of the second odd bit without the area symmetry line on the constellation diagram is as follows: -4D (|r) 1 |-Δ)；
The LLR calculation mode of the second odd bit with the area symmetry line on the constellation diagram is as follows: -4D (||r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 For the real part, delta is the dividing line value, delta i Valuing at least one symmetry line corresponding to the second odd bit, ||r 1 |-δ i And I represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
4. A method according to claim 3, wherein the LLR for the second odd bit for which there are 1 regional symmetry lines on the constellation is calculated by: -4D (||r) 1 |-δ 1 |-Δ)；
The LLR for the second odd bit with 2 regional symmetry lines on the constellation is calculated by: -4D% r is I R 1 |-δ 1 |-δ 2 |-Δ)；
The LLR for the second odd bit with 3 regional symmetry lines on the constellation is calculated by: -4D (|) r is I R 1 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
5. The method of claim 1, wherein the LLR for even bits of the M bits is calculated by: multiplying the second constant by a second target value;
the second constant is determined from the symmetry;
The second target value is determined in accordance with an imaginary part of the received signal or in accordance with at least one of the dividing line and the region symmetry line, and the imaginary part of the received signal.
6. The method of claim 5 wherein said second constant is a positive number in the LLR calculation for the first even bit;
the second constant is a negative number in the LLR calculation mode of the second even bit;
the first even bit is an even bit of the M bits that is asymmetric on the constellation;
the second even bit is an even bit of the M bits that is symmetrical on the constellation.
7. The method of claim 6 wherein said second target value in said LLR calculation for said first even bit is an imaginary part of said received signal;
the second target value in the LLR calculation mode for the second even bit includes:
a difference between the absolute value of the imaginary part of the received signal and the boundary value; or alternatively
The absolute difference value is the difference value between the absolute value of the imaginary part of the received signal and the value of the symmetry line;
The boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
8. The method of claim 7 wherein the LLR for the first even bit is calculated by: 4r 2 D；
The LLR for the second even bit bits for which there is no regional symmetry line on the constellation is calculated by: -4D (|r) 2 |-Δ)；
The LLR for the second even bit bits with a regional symmetry line on the constellation is calculated by: -4D (||r) 2 |-δ i |-Δ)；
Wherein D is a constant, r 2 For the imaginary part, delta is the boundary value, delta i Valuing at least one symmetry line corresponding to the second even bit, ||r 2 |-δ i And the absolute value of the difference between the absolute value of the imaginary part and the value of at least one symmetry line is represented.
9. The method of claim 8 wherein the LLR for the second even bit bits for which there are 1 regional symmetry line on the constellation is calculated by: -4D (||r) 2 |-δ 1 |-Δ)；
The LLR for the second even bit with 2 regional symmetry lines on the constellation is calculated by: -4D% r is I R 2 |-δ 1 |-δ 2 |-Δ)；
The LLR for the second even bit with 3 regional symmetry lines on the constellation is calculated by: -4D (|) r is I R 2 |-δ 1 |-δ 2 |-δ 3 |-Δ)；
δ 1 ，δ 2 ，δ 3 And respectively taking values of the symmetry lines of the 3 areas.
10. A communication device, comprising: memory, transceiver, and processor, wherein:
a memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the following operations:
determining constellation information of each bit in M bits, wherein the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
determining a log-likelihood ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the LLR calculation mode of at least one bit in M bits is calculated by adopting 1 piecewise function;
according to an LLR calculation mode of a target bit, calculating an LLR value of the target bit, wherein the target bit is any bit in the M bits;
the constellation information includes at least one of:
symmetry on a constellation, a dividing line on the constellation, and a regional symmetry line on the constellation;
the constellation diagram corresponds to the modulation mode;
the LLR calculation mode of the odd bit in the M bits is as follows: multiplying a first constant by a first target value;
The first constant is determined from the symmetry;
the first target value is determined from the real part of the received signal or from at least one of the dividing line and the region symmetry line, and the real part of the received signal;
the first target value in the LLR calculation mode of the first odd bit is the real part of the received signal;
the first target value in the LLR calculation method for the second odd bit includes:
the absolute value of the real part of the received signal is different from the boundary line; or alternatively
The absolute difference value is the difference value between the absolute value of the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
11. The communication device of claim 10, wherein the first constant is a positive number in the LLR calculation for the first odd bit;
the first constant is a negative number in the LLR calculation mode of the second odd bit;
The first odd-bit is an odd-bit of the M bits that is asymmetric on the constellation;
the second odd-bit is an odd-bit of the M bits that is symmetrical on the constellation.
12. The communications device of claim 10, wherein the LLR for the first odd bit is calculated by: 4r 1 D；
The LLR calculation mode of the second odd bit without the area symmetry line on the constellation diagram is as follows: -4D (|r) 1 |-Δ)；
The LLR calculation mode of the second odd bit with the area symmetry line on the constellation diagram is as follows: -4D (||r) 1 |-δ i |-Δ)；
Wherein D is a constant, r 1 For the real part, delta is the dividing line value, delta i Valuing at least one symmetry line corresponding to the second odd bit, ||r 1 |-δ i And I represents the absolute value of the difference between the absolute value of the real part and the value of at least one symmetry line.
13. The communication device of claim 10, wherein the LLR for even bits of the M bits is calculated by: multiplying the second constant by a second target value;
the second constant is determined from the symmetry;
the second target value is determined in accordance with an imaginary part of the received signal or in accordance with at least one of the dividing line and the region symmetry line, and the imaginary part of the received signal.
14. The communication device of claim 13, wherein the second constant is a positive number in the LLR calculation for the first even bit;
the second constant is a negative number in the LLR calculation mode of the second even bit;
the first even bit is an even bit of the M bits that is asymmetric on the constellation;
the second even bit is an even bit of the M bits that is symmetrical on the constellation.
15. A communication device, comprising:
a first determining module, configured to determine constellation information of each bit in M bits, where the M bits are M bits corresponding to a modulation mode in a received signal, and M is an integer greater than 1;
the second determining module is used for determining a Log Likelihood Ratio (LLR) calculation mode of each bit according to the constellation diagram information, wherein the LLR calculation mode of at least one bit in the M bits is calculated by adopting 1 piecewise function;
a calculation module, configured to calculate an LLR value of a target bit according to an LLR calculation manner of the target bit, where the target bit is any bit of the M bits;
the constellation information includes at least one of:
Symmetry on a constellation, a dividing line on the constellation, and a regional symmetry line on the constellation;
the constellation diagram corresponds to the modulation mode;
the LLR calculation mode of the odd bit in the M bits is as follows: multiplying a first constant by a first target value;
the first constant is determined from the symmetry;
the first target value is determined from the real part of the received signal or from at least one of the dividing line and the region symmetry line, and the real part of the received signal;
the first target value in the LLR calculation mode of the first odd bit is the real part of the received signal;
the first target value in the LLR calculation method for the second odd bit includes:
the absolute value of the real part of the received signal is different from the boundary line; or alternatively
The absolute difference value is the difference value between the absolute value of the real part of the received signal and the value of the symmetry line;
the boundary value is the value of the boundary on the constellation diagram, and the symmetry line value is the value of the symmetry line on the constellation diagram.
16. The communications device of claim 15, wherein the LLR for even bits of the M bits is calculated by: multiplying the second constant by a second target value;
the second constant is determined from the symmetry;
the second target value is determined in accordance with an imaginary part of the received signal or in accordance with at least one of the dividing line and the region symmetry line, and the imaginary part of the received signal.
17. A processor-readable storage medium, characterized in that the processor-readable storage medium stores a computer program for causing the processor to execute the signal demodulation processing method according to any one of claims 1 to 9.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101057440A (en) * 2004-11-03 2007-10-17 松下电器产业株式会社 Method and transmitter structure removing phase ambiguity by repetition rearrangement
CN101854329A (en) * 2010-02-01 2010-10-06 新邮通信设备有限公司 A Fast Demodulation Method
CN104283835A (en) * 2013-07-02 2015-01-14 大唐联诚信息系统技术有限公司 Quadrature amplitude modulation qubit demodulation method and device
CN107809402A (en) * 2016-09-09 2018-03-16 电信科学技术研究院 A kind of method and apparatus being demodulated

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102021314B1 (en) * 2015-05-15 2019-09-16 한국전자통신연구원 Apparatus and method for soft-decision demodulating in Non-square Quadrature Amplitude Modulation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101057440A (en) * 2004-11-03 2007-10-17 松下电器产业株式会社 Method and transmitter structure removing phase ambiguity by repetition rearrangement
CN101854329A (en) * 2010-02-01 2010-10-06 新邮通信设备有限公司 A Fast Demodulation Method
CN104283835A (en) * 2013-07-02 2015-01-14 大唐联诚信息系统技术有限公司 Quadrature amplitude modulation qubit demodulation method and device
CN107809402A (en) * 2016-09-09 2018-03-16 电信科学技术研究院 A kind of method and apparatus being demodulated

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KDDI.R1-060914 "Twin Turbo Performance with Swapping Constellation Re-Arrangement for Repetition Transmission".3GPP tsg_ran\WG1_RL1.2006,(TSGR1_44bis),1-3页. *
一种简化的16QAM 软解映射算法;兰霞;《舰船电子工程》;64-67页 *

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