CN118868942A - Sampling reset circuit, method, analog-to-digital converter and analog-to-digital conversion system - Google Patents

Sampling reset circuit, method, analog-to-digital converter and analog-to-digital conversion system Download PDF

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Publication number
CN118868942A
CN118868942A CN202410882553.8A CN202410882553A CN118868942A CN 118868942 A CN118868942 A CN 118868942A CN 202410882553 A CN202410882553 A CN 202410882553A CN 118868942 A CN118868942 A CN 118868942A
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Prior art keywords
capacitor
sampling
module
reset
signal
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池浩
邬蓉
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Shanghai Lianying Microelectronics Technology Co ltd
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Shanghai Lianying Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本申请涉及一种采样复位电路、方法、模数转换器和模数转换系统，其中，采样复位电路包括采样电容模块、控制模块、第一信号模块、第二信号模块和比较器；第一信号模块和第二信号模块均与采样电容模块连接，第一信号模块中的复位电压端与第二信号模块中的复位电压端连接，且第一信号模块和第二信号模块均未连接外部复位器件，控制模块分别与采样电容模块和比较器连接，基于此，控制模块在采样阶段、比较阶段以及复位阶段，对应控制采样电容模块中每个电容与共模电压端的连接状态，从而能够通过电荷重分配实现复位。通过本申请，解决了无法在不产生额外功耗的情况下实现复位的问题，实现了在不产生额外功耗的情况下复位至共模电平。

The present application relates to a sampling reset circuit, method, analog-to-digital converter and analog-to-digital conversion system, wherein the sampling reset circuit includes a sampling capacitor module, a control module, a first signal module, a second signal module and a comparator; the first signal module and the second signal module are both connected to the sampling capacitor module, the reset voltage terminal in the first signal module is connected to the reset voltage terminal in the second signal module, and the first signal module and the second signal module are not connected to an external reset device, and the control module is respectively connected to the sampling capacitor module and the comparator, based on which, the control module controls the connection state of each capacitor in the sampling capacitor module and the common mode voltage terminal in the sampling phase, the comparison phase and the reset phase, so that reset can be achieved through charge redistribution. Through this application, the problem of being unable to achieve reset without generating additional power consumption is solved, and reset to the common mode level is achieved without generating additional power consumption.

Description

Sampling reset circuit, sampling reset method, analog-to-digital converter and analog-to-digital conversion system
Technical Field
The present application relates to the field of analog electronics, and in particular, to a sampling reset circuit, a sampling reset method, an analog-to-digital converter, and an analog-to-digital conversion system.
Background
When processing multiple channel signals using an analog-to-digital converter (Analog to Digital Converter, abbreviated ADC), it is often necessary to perform a reset operation, i.e., to empty or set the charge on the ADC sampling capacitance to a fixed value so that each channel sees the same amount of charge to maintain consistent linearity.
In the existing reset method, the charge amount is generally reset through a Buffer (Buffer) or a power supply, but both methods require larger additional power consumption, and the reset cannot be realized without generating additional power consumption.
Aiming at the problem that the reset can not be realized without generating extra power consumption in the related art, no effective solution is proposed at present.
Disclosure of Invention
In this embodiment, a sampling reset circuit, a method, an analog-to-digital converter, and an analog-to-digital conversion system are provided to solve the problem that in the related art, reset cannot be achieved without generating additional power consumption.
In a first aspect, in this embodiment, there is provided a sampling reset circuit, the circuit including: the device comprises a sampling capacitor module, a control module, a first signal module, a second signal module and a comparator; wherein,
The control module is respectively connected with the sampling capacitor module and the comparator;
The first signal module and the second signal module are connected with the sampling capacitor module;
the reset voltage end in the first signal module is connected with the reset voltage end in the second signal module, and the first signal module and the second signal module are not connected with an external reset device.
In some embodiments, the control module is configured to control a connection state of each capacitor in the sampling capacitor module and a common-mode voltage end according to different signal processing stages of the circuit;
Wherein the signal processing stage comprises a sampling stage, a comparing stage and a resetting stage.
In some embodiments, the reset rate of the capacitor is determined according to the capacitance value of each capacitor in the sampling capacitor module and the on-resistance of the switch corresponding to the reset voltage terminal.
In some embodiments thereof, the sampling capacitance module comprises a first capacitance array and a second capacitance array;
The first capacitor array is respectively connected with the first signal module and the control module;
The second capacitor array is respectively connected with the second signal module and the control module.
In some embodiments, the control module includes a first control switch and a second control switch;
the first control switch is respectively connected with the first capacitor array and the positive input end of the comparator and is used for controlling the connection state of each capacitor in the first capacitor array and a preset common-mode voltage end;
the second control switch is respectively connected with the second capacitor array and the negative input end of the comparator and is used for controlling the connection state of each capacitor in the second capacitor array and the common-mode voltage end.
In some embodiments thereof, the first signal module further comprises a first differential input signal terminal; the second signal module further comprises a second differential input signal end;
when the sampling capacitor module samples, each capacitor in the first capacitor array is connected with the first differential input signal end through a corresponding first selection switch;
Each capacitor in the second capacitor array is connected with the second differential input signal end through a corresponding second selection switch.
In some embodiments, the capacitive array is a bridged capacitive array.
In some embodiments thereof, the first signal module further comprises a first reference voltage terminal and a second reference voltage terminal; the second signal module further comprises the first reference voltage terminal and the second reference voltage terminal;
When the comparator compares signals, each capacitor in the sampling capacitor module is controlled to be connected with the first reference voltage end or the second reference voltage end according to a comparison result.
In a second aspect, in this embodiment, there is provided a sampling reset method, which is applicable to the sampling reset circuit described in the first aspect; the method comprises the following steps:
When the sampling reset circuit performs sampling, a first capacitor array and a second capacitor array in the sampling capacitor module are controlled to be connected with a common-mode voltage end;
When the sampling reset circuit compares signals, the first capacitor array and the second capacitor array are controlled to be disconnected with a common-mode voltage end;
And when the signal comparison is finished, controlling the first capacitor array and the second capacitor array to be connected through a reset voltage end, and controlling each capacitor in the capacitor array to be connected with a common-mode voltage end.
In a third aspect, in this embodiment, there is provided an analog-to-digital converter, including the sample reset circuit described in the first aspect.
In a fourth aspect, in this embodiment, an analog-to-digital conversion system is provided, where the analog-to-digital conversion system includes a multi-channel analog front end and the analog-to-digital converter described in the third aspect above.
Compared with the related art, the sampling reset circuit, the sampling reset method, the analog-to-digital converter and the analog-to-digital conversion system provided in the embodiment comprise a sampling capacitor module, a control module, a first signal module, a second signal module and a comparator; the control module is respectively connected with the sampling capacitor module and the comparator; the first signal module and the second signal module are connected with the sampling capacitor module; the reset voltage end in the first signal module is connected with the reset voltage end in the second signal module, and the first signal module and the second signal module are not connected with an external reset device; therefore, each capacitor in the sampling capacitor module can be controlled to be connected with the common-mode voltage end when the sampling capacitor module samples; when the comparator compares signals, each capacitor in the sampling capacitor module is controlled to be disconnected with the common-mode voltage end; and when the signal comparison is finished, the first capacitor array and the second capacitor array in the sampling capacitor module are controlled to be connected through the reset voltage end, and each capacitor in the capacitor array is connected with the common mode voltage end, so that the problem that the reset can not be realized under the condition that no additional power consumption is generated is solved, and the reset to the common mode level under the condition that no additional power consumption is generated is realized.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a schematic diagram of a sampling reset circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a sampling reset circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a sampling reset circuit according to an embodiment of the present application;
FIG. 4 is a flowchart of a sample reset method according to an embodiment of the present application;
fig. 5 is a schematic diagram of an analog-to-digital conversion system according to an embodiment of the present application.
In the figure: 100. a sampling capacitor module; 200. a control module; 300. a first signal module; 400. a second signal module; 500. a comparator; 600. and resetting the voltage terminal.
Detailed Description
The present application will be described and illustrated with reference to the accompanying drawings and examples for a clearer understanding of the objects, technical solutions and advantages of the present application.
Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these" and similar terms in this application are not intended to be limiting in number, but may be singular or plural. The terms "comprising," "including," "having," and any variations thereof, as used herein, are intended to encompass non-exclusive inclusion; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this disclosure, merely distinguish similar objects and do not represent a particular ordering for objects.
In this embodiment, a sampling reset circuit is provided, fig. 1 is a schematic diagram of the sampling reset circuit of this embodiment, as shown in fig. 1, and the circuit includes: the sampling capacitor module 100, the control module 200, the first signal module 300, the second signal module 400 and the comparator 500; the first signal module 300 and the second signal module 400 are both connected with the sampling capacitor module 100, the reset voltage end 600 in the first signal module 300 is connected with the reset voltage end 600 in the second signal module 400, and the first signal module 300 and the second signal module 400 are not connected with external reset devices;
The control module 200 is respectively connected with the sampling capacitor module 100 and the comparator 500;
The control module 200 is used for controlling each capacitor in the sampling capacitor module 100 to be connected with the common-mode voltage end when the sampling capacitor module 100 performs sampling;
when the comparator 500 performs signal comparison, each capacitor in the sampling capacitor module 100 is controlled to be disconnected with the common-mode voltage end;
at the end of the signal comparison, each capacitor in the control sampling capacitance module 100 is connected to the common mode voltage terminal.
Specifically, the sampling reset circuit includes a sampling capacitor module 100, a control module 200, a first signal module 300, a second signal module 400 and a comparator 500, wherein the first signal module 300 and the second signal module 400 are both connected with the sampling capacitor module 100, a reset voltage terminal 600 in the first signal module 300 is connected with a reset voltage terminal 600 in the second signal module 400, and the control module 200 is respectively connected with the sampling capacitor module 100 and the comparator 500.
The first signal module 300 and the second signal module 400 include a differential input signal terminal and a reference voltage terminal in addition to the reset voltage terminal 600. Based on this, when the sampling capacitor module 100 performs sampling, the sampling plate of each capacitor in the sampling capacitor module 100, that is, the bottom plate or the top plate of the capacitor is connected with the differential input signal end, and the input signal and the two ends of the comparator 500 implement capacitor establishment, at this time, the sampling plate of each capacitor in the sampling capacitor module 100 is controlled by the control module 200 to be connected with the common mode voltage end.
Until sampling is finished, the control module 200 controls the sampling electrode plate of each capacitor in the sampling capacitor module 100 to be disconnected from the common-mode voltage end, so that the capacitance of the capacitor is frozen, that is, the stored charge amount is kept unchanged. Further, when the comparator 500 performs signal comparison, the sampling plates of each capacitor are correspondingly connected to different reference voltage terminals according to the comparison result, and the process only affects the voltage value of the sampling plate of the capacitor, but does not affect the charge amount stored on the capacitor.
After that, when the signal comparison is finished, the sampling plates of the capacitors in the sampling capacitor module 100 are connected to the reset voltage terminal 600 in the signal module, i.e. enter the reset phase, and meanwhile, the sampling plates of each capacitor are controlled to be connected to the common mode voltage terminal through the control module 200.
At this time, since the total charge amount of each capacitor will not change, (Vcm-Vip)Cpdac+(Vcm-Vin)Cndac＝(Vcm-Vreset)(Cpdac+Cndac), is obtained according to the law of conservation of charge, where V reset represents the voltage of the reset voltage terminal, V cm represents the common mode voltage corresponding to the input signal, V ip represents the input level corresponding to each capacitor at the positive input terminal (P terminal) of the comparator 500 in the sampling capacitor module 100, V in represents the input level corresponding to each capacitor at the negative input terminal (N terminal) of the comparator 500 in the sampling capacitor module 100, C pdac represents the capacitance corresponding to the P terminal capacitor in the sampling capacitor module 100, and C ndac represents the capacitance corresponding to the N terminal capacitor in the sampling capacitor module 100; according to the same capacitance of the P end and the N end, the above formula is simplifiedThat is, after the comparison is completed, the sampling electrode plate of each capacitor is controlled to be connected with the common-mode voltage end, and the sampling electrode plates of the capacitors in the sampling capacitor module 100 are all connected to the reset voltage end 600 in the signal module, so that the function of resetting to the common-mode voltage is realized, and no additional power consumption is required in the resetting process.
It should be noted that, in the circuit architecture provided in this embodiment, the type, size and arrangement of the capacitor array, the applied analog-to-digital converter architecture, the magnitude of each voltage value, and the like may be adaptively selected and adjusted according to the actual situation.
In the existing analog-to-digital converter resetting method, the charge amount is generally reset through a buffer or a power supply, but the two methods require larger additional power consumption, and the resetting can not be realized without generating the additional power consumption.
Compared with the prior art, the sampling reset circuit of the present application comprises a sampling capacitor module 100, a control module 200, a first signal module 300, a second signal module 400 and a comparator 500; the first signal module 300 and the second signal module 400 are both connected with the sampling capacitor module 100, and a reset voltage end 600 in the first signal module 300 is connected with a reset voltage end 600 in the second signal module 400; the control module 200 is respectively connected with the sampling capacitor module 100 and the comparator 500; the control module 200 is used for controlling each capacitor in the sampling capacitor module 100 to be connected with the common-mode voltage end when the sampling capacitor module 100 performs sampling; when the comparator 500 performs signal comparison, each capacitor in the sampling capacitor module 100 is controlled to be disconnected with the common-mode voltage end; at the end of the signal comparison, each capacitor in the control sampling capacitance module 100 is connected to the common mode voltage terminal. Based on the method, the capacitor sampling polar plates at the PN end of the capacitor array are short-circuited, so that the point positions of the sampling polar plates can be combined to the common-mode voltage of an input signal by controlling the connection relation between the capacitors and the common-mode voltage end in different stages and utilizing charge redistribution, the problem that the resetting can not be realized under the condition that no additional power consumption is generated is solved, the resetting to the common-mode level under the condition that no additional power consumption is generated is realized, meanwhile, no additional circuit or power supply is required to be arranged, and hardware resources are saved.
In some embodiments, the control module 200 is configured to control the connection state of each capacitor in the sampling capacitor module 100 and the common-mode voltage terminal according to different signal processing stages of the circuit;
the signal processing stage comprises a sampling stage, a comparison stage and a reset stage.
Specifically, in the sampling stage of the sampling reset circuit, the control module 200 connects the first capacitor array and the second capacitor array in the sampling capacitor module 100 with the common-mode voltage terminal. When the sampling reset circuit compares signals, each capacitor in the first capacitor array and the second capacitor array is controlled to be disconnected with the common-mode voltage end, so that the charge quantity on the capacitor is frozen,
Further, when the signal comparison is finished, the circuit enters a reset stage, the first capacitor array is controlled to be connected with the second capacitor array, and each capacitor in each capacitor array is controlled to be connected with the common-mode voltage end in a recovery mode. At this time, if the total charge amount of each capacitor is not changed, according to the law of conservation of charge, it can be known that, when the first capacitor array and the second capacitor array are connected through the reset voltage terminal 600 and each capacitor in the capacitor array is connected to the common mode voltage terminal, the point location of the capacitor sampling electrode is combined to the common mode voltage of the input signal, so as to realize the reset.
According to the embodiment, the control module 200 controls the connection state of each capacitor in the sampling capacitor module 100 and the common-mode voltage end according to different signal processing stages of the circuit, so that after signal comparison, the point positions of the capacitor sampling polar plates are combined into the common-mode voltage of the input signal by charge redistribution, and the reset is realized without generating additional power consumption.
In some of these embodiments, the voltage value of the reset voltage terminal 600 is the same as the voltage value of the common mode voltage terminal.
Specifically, the capacitance in the signal comparison stage is unchanged from the capacitance after the comparison, and V reset＝Vip+Vin-Vcm can be obtained according to the expression corresponding to the law of conservation of charge and the same capacitance at the P-terminal and the N-terminal. Based on this, the voltage value of the reset voltage terminal 600 is set to be the same as the voltage value of the common-mode voltage terminal, so that after the signal comparison is finished, the sampling electrode plate of each capacitor in the sampling capacitor module 100 can be controlled to be connected with the common-mode voltage terminal, and the function of resetting to the common-mode voltage is realized, namely, the point positions of the sampling electrode plates are combined to the common-mode voltage of the input signal through charge redistribution.
It should be noted that, the common-mode voltage is the most advantageous voltage level for front-end establishment, and can be quickly established with each channel of the front-end, and the establishment accuracy is improved while the establishment speed is improved.
By this embodiment, the voltage value of the reset voltage terminal 600 is set to be the same as the voltage value of the common mode voltage terminal, and the reset is realized without additional power consumption and hardware resources by utilizing the same properties of the charge conservation law and the capacitance of the PN terminal.
In some embodiments, the reset rate of the capacitor is determined according to the capacitance value of each capacitor in the sampling capacitor module 100 and the switch on-resistance corresponding to the reset voltage terminal 600.
Specifically, since the reset voltage terminal 600 in the first signal module 300 is connected with the reset voltage terminal 600 in the second signal module 400, that is, the capacitor array PN terminal capacitor sampling electrode plate is short-circuited, after the signal comparison is finished, the point location of the sampling electrode plate can be combined to the common mode voltage of the input signal through the charge redistribution, no extra hardware resource is required to be laid to realize the reset, and the speed of the charge redistribution is limited by the capacitance in the sampling capacitance module 100 and the switch on-resistance corresponding to the reset voltage terminal 600, so that the reset rate can be determined according to the capacitance value of each capacitance in the sampling capacitance module 100 and the switch on-resistance corresponding to the reset voltage terminal 600.
It should be noted that, compared with the reset performed by using the Buffer or the power supply, the reset rate in the embodiment is not limited by the Buffer output impedance or the internal resistance of the power supply, and is only related to the capacitance value of each capacitor and the on-resistance of the switch, and the reset rate is far beyond the reset scheme based on the Buffer or the power supply.
According to the embodiment, the reset rate of the capacitor is determined according to the capacitance value of each capacitor in the sampling capacitor module 100 and the on-resistance of the switch corresponding to the reset voltage terminal 600, so that the reset rate is significantly improved.
Referring to fig. 2, the following describes the structure of each part of the sampling reset circuit.
In some of these embodiments, the sampling capacitance module 100 includes a first capacitance array and a second capacitance array;
the first capacitor array is respectively connected with the first signal module 300 and the control module 200;
the second capacitor array is connected to the second signal module 400 and the control module 200, respectively.
Specifically, the sampling capacitor module 100 includes a first capacitor array and a second capacitor array, the first capacitor array is connected to the first signal module 300 and the control module 200, respectively, and the first capacitor array and the second capacitor array include a corresponding number of capacitors, that is, each capacitor array includes a capacitor C 0,C1,……,Cmsb-1,Cmsb.
Wherein, each capacitor in the first capacitor array is connected with the first signal module 300 through the first selection switch, and each capacitor in the second capacitor array is connected with the second signal module 400 through the second selection switch. In the sampling stage, a selection switch corresponding to each capacitor is connected with an input signal end in a signal module; in the comparison stage, a selection switch corresponding to each capacitor is connected with a reference voltage end in the signal module; in the reset phase, the corresponding selection switch of each capacitor is connected to the reset voltage terminal 600 in the signal module.
Through the present embodiment, the sampling capacitor module 100 includes a first capacitor array and a second capacitor array, and each capacitor array is respectively connected with the corresponding signal module and the control module 200, so as to implement a sampling process.
In some of these embodiments, the control module 200 includes a first control switch and a second control switch;
The first control switch is respectively connected with the first capacitor array and the positive input end of the comparator 500 and is used for controlling the connection state of each capacitor in the first capacitor array and a preset common-mode voltage end;
And the second control switch is respectively connected with the second capacitor array and the negative input end of the comparator 500 and is used for controlling the connection state of each capacitor in the second capacitor array and the common-mode voltage end.
Specifically, the control module 200 includes a first control switch and a second control switch. The first control switch is connected with a sampling polar plate of each capacitor in the first capacitor array and connected with a positive input end of the comparator 500; the second control switch is connected to the sampling plate of each capacitor in the second capacitor array and to the negative input of the comparator 500.
When the capacitor array is sampled, the first control switch and the second control switch are both closed, the sampling polar plates of the capacitors in the first capacitor array and the second capacitor array are connected with the common-mode voltage end, and when the sampling is finished, the first control switch and the second control switch are opened, so that the electric charge quantity stored in the capacitors is frozen.
Further, the comparator 500 is used to perform signal comparison, the comparison process only affects the voltage value of the sampling electrode plate of the capacitor, and does not affect the amount of charge stored on the capacitor, when the signal comparison is finished, the reset phase is entered, the bottom electrode plate of each capacitor in the sampling capacitor module 100 is connected to the reset voltage end 600 in the signal module, and meanwhile, the first control switch and the second control switch are closed, so that the reset is realized.
According to the embodiment, the first control switch and the second control switch are respectively connected with the first capacitor array and the second capacitor array, so that the connection states of the sampling polar plates and the common-mode voltage end of each capacitor can be controlled based on different stages.
In some of these embodiments, the first signal module 300 further includes a first differential input signal terminal; the second signal module 400 further includes a second differential input signal terminal;
when the sampling capacitor module 100 performs sampling, each capacitor in the first capacitor array is connected with a first differential input signal end through a corresponding first selection switch;
Each capacitor in the second capacitor array is connected with a second differential input signal end through a corresponding second selection switch.
Specifically, the first signal module 300 further includes a first differential input signal terminal in addition to the reset voltage terminal 600, and the second signal module 400 further includes a second differential input signal terminal. In the sampling stage, the sampling electrode plate of each capacitor in the first capacitor array is connected with the first differential input signal terminal V ip through the first selection switch S 3, and the sampling electrode plate of each capacitor in the second capacitor array is connected with the second differential input signal terminal V in through the second selection switch S 4.
Through this embodiment, when the sampling capacitor module 100 performs sampling, the sampling electrode plate of each capacitor in the first capacitor array, that is, the bottom electrode plate or the top electrode plate of the capacitor, is connected to the first differential input signal end through the corresponding first selection switch, and each capacitor in the second capacitor array is connected to the second differential input signal end through the corresponding second selection switch, so as to implement the sampling process.
Referring to fig. 3, in some embodiments, the capacitor array is a bridge capacitor array.
Specifically, each capacitor array in the sampling capacitor module 100 employs a bridge capacitor array, which is connected to the signal module and the comparator 500, respectively, and includes a capacitor C u,…,kCu,Ca,Cu,…,mCu.
Based on this, when the sampling capacitor module 100 performs sampling, the sampling plate of the capacitor C u,…,kCu,Cu,…,mCu is connected to the differential input signal end, the input signal and two ends of the comparator 500 achieve capacitor establishment, and the top plate of the capacitor C u,…,mCu and the capacitor C a are controlled to be connected to the common-mode voltage end through the control module 200, where the sampling plate of the capacitor C u,…,kCu,Cu,…,mCu is preferably a bottom plate.
After sampling, the top plate of the capacitor C u,…,mCu and the connection between the capacitor C a and the common-mode voltage terminal are disconnected by the control module 200, so that the capacitance on the capacitor is frozen. Further, in the signal comparison stage, the sampling electrode plates of the capacitor C u,…,kCu,Cu,…,mCu are correspondingly connected to different reference voltage terminals according to the comparison result, and the process does not affect the charge quantity stored in the capacitor.
After that, when the signal comparison is finished, a reset phase is entered, the sampling electrode plate of the capacitor C u,…,kCu,Cu,…,mCu is connected to the reset voltage end 600 in the signal module, and meanwhile, the sampling electrode plate of the capacitor C u,…,mCu and the capacitor C a are controlled to be connected to realize reset.
It should be noted that, besides the bridge capacitor array, a common capacitor array such as a non-binary capacitor array may be used as the sampling capacitor module 100, and the reset principle is to combine the point positions of the sampling electrode plate into the common mode voltage of the input signal by using charge redistribution.
By adopting the bridge capacitor array and other common capacitor arrays as the sampling capacitor module 100 in this embodiment, the practicality of the sampling reset circuit is improved.
In some of these embodiments, the first signal module 300 further includes a first reference voltage terminal and a second reference voltage terminal; the second signal module 400 further includes a first reference voltage terminal and a second reference voltage terminal;
When the comparator 500 performs signal comparison, each capacitor in the sampling capacitor module 100 is controlled to be connected to the first reference voltage terminal or the second reference voltage terminal according to the comparison result.
Specifically, the first signal module 300 and the second signal module 400 each include a first reference voltage terminal V refp and a second reference voltage terminal V refn. When the comparator 500 performs signal comparison, each capacitor in the sampling capacitor module 100 is disconnected from the common-mode voltage terminal, and each capacitor in the sampling capacitor module 100 is controlled to be connected to the first reference voltage terminal V refp or the second reference voltage terminal V refn according to the comparison result.
It should be noted that, the above comparison process only affects the voltage value of each capacitor sampling plate in the sampling capacitor module 100, and does not affect the capacitance stored on the capacitor, so that after the comparison is finished, the reset is realized by using the conservation of charge and the same property of the capacitor at the PN end.
With this embodiment, when the comparator 500 performs signal comparison, each capacitor in the sampling capacitor module 100 is controlled to be connected to the first reference voltage terminal or the second reference voltage terminal according to the comparison result, so as to implement signal comparison, and keep the capacitance stored in the capacitor unchanged.
The present embodiment is described and illustrated below by way of preferred embodiments.
In the present embodiment, there is provided a sampling reset circuit including: the sampling capacitor module 100, the control module 200, the first signal module 300, the second signal module 400 and the comparator 500, the sampling capacitor module 100 comprises a first capacitor array and a second capacitor array, the control module 200 comprises a first control switch S 1 and a second control switch S 2, the first signal module 300 comprises a first input signal terminal V ip, a first reference voltage terminal V refp, a second reference voltage terminal V refn and a reset voltage terminal V reset, and the second signal module 400 comprises a second input signal terminal V in, a first reference voltage terminal V refp, a second reference voltage terminal V refn and a reset voltage terminal V reset. Wherein, each capacitor in the first capacitor array is connected with the first signal module 300 through the first selection switch; each capacitor in the second capacitor array is connected with the first signal module 300 through a second selection switch; the reset voltage terminal in the first signal module 300 is connected to the reset voltage terminal in the second signal module 400.
Specifically, in the sampling stage, the selection switch corresponding to each capacitor is connected with the input signal end in the signal module, and meanwhile, the switches S 1 and S 2 are kept closed; at the end of sampling, switches S 1 and S 2 are turned off, freezing the amount of charge on each capacitor. And entering a comparison stage, wherein the sampling polar plates of the capacitors are respectively connected to a first reference voltage end V refp and a second reference voltage end V refn according to the comparison result. This process only affects the voltage value of the capacitor sampling plate and does not affect the amount of charge stored on the capacitor.
After the comparison is completed, the sampling polar plates of the capacitors are connected to the reset voltage end in the signal module, namely, the reset stage is entered, and meanwhile, the connection between the sampling polar plates of the capacitors and the common-mode voltage end is realized through a control switch. (Vcm-Vip)Cpdac+(Vcm-Vin)Cndac＝(Vcm-Vreset)(Cpdac+Cndac), is available according to the law of conservation of charge, where V cm represents a common mode voltage corresponding to an input signal, V ip represents an input level corresponding to a capacitance at a P end of the comparator 500 in the sampling capacitor module 100, V in represents an input level corresponding to a capacitance at an N end of the comparator 500 in the sampling capacitor module 100, C pdac represents a capacitance corresponding to a capacitance at a P end of the sampling capacitor module 100, and C ndac represents a capacitance corresponding to a capacitance at an N end of the sampling capacitor module 100. Further, since the capacitances of the P terminal and the N terminal are the same, simplifying the above formula can be achievedAfter the comparison is completed, the sampling polar plate of each capacitor is controlled to be connected with the common-mode voltage end, and the point position of the sampling polar plate is combined to the common-mode voltage of the input signal by utilizing charge redistribution in the resetting process, so that additional power consumption is not needed.
According to the embodiment, the capacitor array PN end capacitor sampling polar plate is short-circuited, and then the connection relation between the capacitor and the common-mode voltage end in different stages is controlled, the point positions of the sampling polar plate are combined to the common-mode voltage of an input signal by utilizing charge redistribution, so that the problem that reset cannot be realized under the condition that no additional power consumption is generated is solved, the reset to the common-mode level under the condition that no additional power consumption is generated is realized, meanwhile, no additional circuit or power supply is required to be arranged, and hardware resources are saved.
The embodiment also provides a sampling reset method, which is adapted to the above embodiment and the preferred implementation manner, and is not described in detail. Fig. 4 is a flowchart of the sample reset method of the present embodiment, as shown in fig. 4, the flowchart includes the following steps:
Step S410, when the sampling reset circuit performs sampling, controlling the first capacitor array and the second capacitor array in the sampling capacitor module 100 to be connected with the common-mode voltage terminal;
Step S420, when the sampling reset circuit compares signals, the first capacitor array and the second capacitor array are controlled to be disconnected with the common-mode voltage end;
in step S430, when the signal comparison is finished, the first capacitor array and the second capacitor array are controlled to be connected through the reset voltage terminal 600, and each capacitor in the capacitor array is controlled to be connected with the common mode voltage terminal.
Specifically, when the sampling reset circuit performs sampling, in the sampling capacitor module 100, the sampling plate of each capacitor in the first capacitor array and the second capacitor array, that is, the bottom plate or the top plate of the capacitor is connected with the differential input signal end in the first signal module, so as to realize capacitor establishment, and the sampling plate of each capacitor in the sampling capacitor array is connected with the common mode voltage end through the control module 200.
After the sampling is finished, the control module 200 controls the sampling polar plate of each capacitor in the first capacitor array and the second capacitor array to be disconnected with the common-mode voltage end, so that the charge quantity on the capacitor is frozen. And then, the sampling reset circuit enters a signal comparison stage, sampling polar plates of all the capacitors are correspondingly connected to different reference voltage ends according to comparison results, and the process does not influence the charge quantity stored on the capacitors.
When the signal comparison is finished, the sampling electrode plates of the capacitors in the sampling capacitor module 100 are connected to the reset voltage terminal 600 in the signal module, so that the first capacitor array and the second capacitor array are connected through the reset voltage terminal 600, and meanwhile, the sampling electrode plates of each capacitor are restored to be connected with the common-mode voltage terminal through the control module 200.
It should be noted that, since the total charge amount of each capacitor will not change, (Vcm-Vip)Cpdac+(Vcm-Vin)Cndac＝(Vcm-Vreset)(Cpdac+Cndac), can be obtained according to the law of conservation of charge, where V reset represents the voltage of the reset voltage terminal, V cm represents the common mode voltage corresponding to the input signal, V ip represents the input level corresponding to each capacitor at the positive input terminal (P terminal) of the comparator 500 in the sampling capacitor module 100, V in represents the input level corresponding to each capacitor at the negative input terminal (N terminal) of the comparator 500 in the sampling capacitor module 100, C pdac represents the capacitance corresponding to the P terminal capacitor in the sampling capacitor module 100, and C ndac represents the capacitance corresponding to the N terminal capacitor in the sampling capacitor module 100. Based on the same capacitance of the P end and the N end, the capacitance can be obtained by simplifying the formulaAfter comparison, the sampling polar plate of each capacitor is controlled to be connected with the common-mode voltage end, and the first capacitor array is connected with the second capacitor array, so that the function of resetting to the common-mode voltage is realized, and extra power consumption is not needed in the resetting process.
According to the embodiment, when the sampling capacitor module 100 performs sampling, each capacitor in the sampling capacitor module 100 is controlled to be connected with a common-mode voltage end; when the comparator 500 performs signal comparison, each capacitor in the sampling capacitor module 100 is controlled to be disconnected with the common-mode voltage end; at the end of signal comparison, the first capacitor array and the second capacitor array in the sampling capacitor module 100 are controlled to be connected through the reset voltage end, and each capacitor in the capacitor array is connected with the common mode voltage end, so that the problem that reset cannot be realized under the condition that no additional power consumption is generated is solved, and the reset to the common mode level under the condition that no additional power consumption is generated is realized.
The embodiment also provides an analog-to-digital converter, which comprises the sampling reset circuit.
Optionally, the analog-to-digital converter may further include a logic control circuit and a clock circuit, wherein the logic control circuit and the sampling reset circuit are connected to the logic control circuit and the sampling reset circuit, respectively.
In this embodiment, an analog-to-digital conversion system is also provided, and as shown in fig. 5, the analog-to-digital conversion system includes a multi-channel analog front end and the analog-to-digital converter described above.
It should be noted that, when the Analog-to-digital converter (ADC) processes each channel signal in the multi-channel Analog Front End (AFE), in order to avoid the memory effect of the previous channel affecting the next channel, the charge on the ADC sampling capacitor is emptied or set to a fixed value, so that each channel can see the same amount of charge, so as to maintain consistent linearity. By the sampling reset circuit, the capacitor sampling polar plates at the PN end of the capacitor array are short-circuited, so that the point positions of the sampling polar plates are combined into the common-mode voltage of an input signal by load redistribution, and the common-mode voltage is the most favorable voltage level for front-end establishment, so that the quick establishment of each channel with the front end is realized, and the establishment speed is improved, and meanwhile, the establishment precision is obviously improved.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the present application.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims (10)

1.一种采样复位电路，其特征在于，所述电路包括：采样电容模块(100)、控制模块(200)、第一信号模块(300)、第二信号模块(400)和比较器(500)；其中，1. A sampling reset circuit, characterized in that the circuit comprises: a sampling capacitor module (100), a control module (200), a first signal module (300), a second signal module (400) and a comparator (500); wherein, 所述控制模块(200)，分别与所述采样电容模块(100)和所述比较器(500)连接；The control module (200) is connected to the sampling capacitor module (100) and the comparator (500) respectively; 所述第一信号模块(300)和所述第二信号模块(400)均与所述采样电容模块(100)连接；The first signal module (300) and the second signal module (400) are both connected to the sampling capacitor module (100); 所述第一信号模块(300)中的复位电压端(600)与所述第二信号模块(400)中的复位电压端(600)连接，且所述第一信号模块(300)和所述第二信号模块(400)均未连接外部复位器件。The reset voltage terminal (600) in the first signal module (300) is connected to the reset voltage terminal (600) in the second signal module (400), and neither the first signal module (300) nor the second signal module (400) is connected to an external reset device. 2.根据权利要求1所述的采样复位电路，其特征在于，2. The sampling reset circuit according to claim 1, characterized in that: 所述控制模块(200)，用于根据所述电路的不同信号处理阶段，控制所述采样电容模块(100)中每个电容与共模电压端的连接状态；The control module (200) is used to control the connection state between each capacitor in the sampling capacitor module (100) and the common mode voltage terminal according to different signal processing stages of the circuit; 其中，所述信号处理阶段包括采样阶段、比较阶段和复位阶段。The signal processing stage includes a sampling stage, a comparison stage and a reset stage. 3.根据权利要求1所述的采样复位电路，其特征在于，根据所述采样电容模块(100)中各个电容的电容值和所述复位电压端对应的开关导通阻抗，确定所述电容的复位速率。3. The sampling reset circuit according to claim 1, characterized in that the reset rate of the capacitor is determined according to the capacitance value of each capacitor in the sampling capacitor module (100) and the switch on-resistance corresponding to the reset voltage terminal. 4.根据权利要求1所述的采样复位电路，其特征在于，所述采样电容模块(100)包括第一电容阵列和第二电容阵列；4. The sampling reset circuit according to claim 1, characterized in that the sampling capacitor module (100) comprises a first capacitor array and a second capacitor array; 所述第一电容阵列，分别与所述第一信号模块(300)和所述控制模块(200)连接；The first capacitor array is connected to the first signal module (300) and the control module (200) respectively; 所述第二电容阵列，分别与所述第二信号模块(400)和所述控制模块(200)连接。The second capacitor array is connected to the second signal module (400) and the control module (200) respectively. 5.根据权利要求4所述的采样复位电路，其特征在于，所述控制模块(200)包括第一控制开关和第二控制开关；5. The sampling reset circuit according to claim 4, characterized in that the control module (200) comprises a first control switch and a second control switch; 所述第一控制开关，分别与所述第一电容阵列和所述比较器(500)的正输入端连接，用于控制所述第一电容阵列中各个电容与预设的共模电压端的连接状态；The first control switch is connected to the first capacitor array and the positive input terminal of the comparator (500) respectively, and is used to control the connection state between each capacitor in the first capacitor array and a preset common mode voltage terminal; 所述第二控制开关，分别与所述第二电容阵列和所述比较器(500)的负输入端连接，用于控制所述第二电容阵列中各个电容与所述共模电压端的连接状态。The second control switch is connected to the second capacitor array and the negative input terminal of the comparator (500) respectively, and is used to control the connection state between each capacitor in the second capacitor array and the common mode voltage terminal. 6.根据权利要求4所述的采样复位电路，其特征在于，所述第一信号模块(300)还包括第一差分输入信号端；所述第二信号模块(400)还包括第二差分输入信号端；6. The sampling reset circuit according to claim 4, characterized in that the first signal module (300) further comprises a first differential input signal terminal; the second signal module (400) further comprises a second differential input signal terminal; 在所述采样电容模块(100)进行采样时，所述第一电容阵列中的每个电容，通过对应的第一选择开关与所述第一差分输入信号端连接；When the sampling capacitor module (100) performs sampling, each capacitor in the first capacitor array is connected to the first differential input signal terminal through a corresponding first selection switch; 所述第二电容阵列中的每个电容，通过对应的第二选择开关与所述第二差分输入信号端连接。Each capacitor in the second capacitor array is connected to the second differential input signal terminal through a corresponding second selection switch. 7.根据权利要求4所述的采样复位电路，其特征在于，所述电容阵列为桥接电容阵列。7 . The sampling and resetting circuit according to claim 4 , wherein the capacitor array is a bridge capacitor array. 8.一种采样复位方法，其特征在于，所述方法适用于如权利要求1至7中任一项所述的采样复位电路；所述方法包括：8. A sampling reset method, characterized in that the method is applicable to the sampling reset circuit according to any one of claims 1 to 7; the method comprises: 在所述采样复位电路进行采样时，控制采样电容模块(100)中的第一电容阵列和第二电容阵列与共模电压端连接；When the sampling reset circuit performs sampling, the first capacitor array and the second capacitor array in the sampling capacitor module (100) are controlled to be connected to the common mode voltage terminal; 在所述采样复位电路进行信号比较时，控制所述第一电容阵列和所述第二电容阵列与共模电压端断开连接；When the sampling reset circuit performs signal comparison, controlling the first capacitor array and the second capacitor array to be disconnected from the common mode voltage terminal; 在信号比较结束时，控制所述第一电容阵列和所述第二电容阵列通过复位电压端(600)连接，并控制电容阵列中每个电容与共模电压端连接。When the signal comparison is finished, the first capacitor array and the second capacitor array are controlled to be connected via a reset voltage terminal (600), and each capacitor in the capacitor array is controlled to be connected to a common mode voltage terminal. 9.一种模数转换器，其特征在于，所述模数转换器包括如权利要求1至7中任一项所述的采样复位电路。9 . An analog-to-digital converter, characterized in that the analog-to-digital converter comprises the sampling reset circuit according to any one of claims 1 to 7. 10.一种模数转换系统，其特征在于，所述模数转换系统包括多通道模拟前端以及如权利要求9所述的模数转换器。10 . An analog-to-digital conversion system, characterized in that the analog-to-digital conversion system comprises a multi-channel analog front end and the analog-to-digital converter according to claim 9 .
CN202410882553.8A 2024-07-02 2024-07-02 Sampling reset circuit, method, analog-to-digital converter and analog-to-digital conversion system Pending CN118868942A (en)

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