CN121237006A

CN121237006A - Display substrate and its driving method, display device

Info

Publication number: CN121237006A
Application number: CN202410834046.7A
Authority: CN
Inventors: 谷晓芳; 郑敏栋; 马小叶; 熊雄; 王永灿; 郭晖; 张然
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2024-06-25
Filing date: 2024-06-25
Publication date: 2025-12-30
Also published as: WO2026001369A1

Abstract

This disclosure provides a display substrate and its driving method, as well as a display device, relating to the field of display technology, for reducing the problem of display residue on the display substrate. The display substrate includes multiple input signal lines, multiple columns of pixel circuits, multiple first signal line groups, multiple first multiplexed circuits, and multiple second multiplexed circuits. Each first signal line group includes at least two first signal lines, one of which is electrically connected to a column of pixel circuits. Each first multiplexed circuit is electrically connected to one input signal line and the first signal lines of the first signal line groups. Each second multiplexed circuit is electrically connected to one input signal line and the first signal lines of a first signal line group. Each input signal line is electrically connected to one first multiplexed circuit and one second multiplexed circuit, and each first signal line of a first signal line group is electrically connected to one first multiplexed circuit and one second multiplexed circuit. The aforementioned display substrate is used to display images.

Description

Display substrate, driving method thereof and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display substrate, a driving method thereof and a display device.

Background

Touch AND DISPLAY DRIVER Integration (TDDI) display products are one of the currently mainstream screen display technologies, and TDDI products are widely used in various display products by virtue of more sensitive Touch technology, lighter and thinner appearance and lower cost.

Disclosure of Invention

An embodiment of the disclosure is directed to a display substrate, a driving method thereof, and a display device, which are used for reducing the risk of right-hand floating of transistors of a multiplexing circuit and reducing or completely eliminating the problem of display residues of the display substrate.

In order to achieve the above object, the embodiments of the present disclosure provide the following technical solutions:

In one aspect, a display substrate is provided. The display substrate includes a plurality of input signal lines, a plurality of columns of pixel circuits, and a plurality of first signal line groups. One of the first signal line groups includes at least two first signal lines, one of which is electrically connected to one column of the pixel circuits. The display substrate further includes a plurality of first multiplexing circuits and a plurality of second multiplexing circuits. The first multiplexing circuit is electrically connected with one input signal line and at least two first signal lines of one first signal line group, and the first multiplexing circuit controls the electrical connection of the input signal line and one first signal line in the same period. The second multiplexing circuit is electrically connected with one input signal line and at least two first signal lines of one first signal line group, and the second multiplexing circuit controls the electric connection of the input signal line and at least one first signal line in the same period. Wherein one of the input signal lines is electrically connected to one of the first multiplexing circuits and one of the second multiplexing circuits, respectively, and the at least two first signal lines of one of the first signal line groups are electrically connected to one of the first multiplexing circuits and one of the second multiplexing circuits, respectively.

The display substrate provided by the embodiment of the disclosure, wherein one input signal line is electrically connected with one first multiplexing circuit and one second multiplexing circuit respectively, and at least two first signal lines of one first signal line group are electrically connected with one first multiplexing circuit and one second multiplexing circuit respectively. The input signal lines may transmit control signals to the first signal lines of the same first signal line group through the first multiplexing circuit and the second multiplexing circuit, respectively. In this way, a plurality of different driving methods can be employed to drive the display substrate to operate at different times by selecting one of the first multiplexing circuit and the second multiplexing circuit. On the one hand, the working time of the first multiplexing circuit and the second multiplexing circuit is shortened, the risk of right drift of transistors of the first multiplexing circuit and the second multiplexing circuit is reduced, and the problem that display residues appear on a display substrate is reduced or completely eliminated.

In some embodiments, the first signal line group includes M first signal lines, and the first multiplexing circuit and the second multiplexing circuit are electrically connected to M first signal lines, where M is greater than or equal to 2. The display substrate further comprises N second signal line groups. The second signal line group comprises M second signal lines, the M second signal lines of the second signal line group are electrically connected with one first multiplexing circuit, one second signal line controls the electrical connection of one first signal line and the input signal line, and N is more than or equal to 2. Wherein the plurality of first multiplexing circuits are alternately connected to the N second signal line groups.

In some embodiments, the display substrate further includes P third signal line groups. The third signal line group comprises M third signal lines, the M third signal lines of the third signal line group are electrically connected with one second multiplexing circuit, one third signal line controls the electric connection of the input signal line and one first signal line, and P is more than or equal to 1.

In some embodiments, the number of the second signal line groups is the same as the number of the third signal line groups, and the plurality of second multiplexing circuits are alternately electrically connected to the P third signal line groups.

In some embodiments, the display substrate includes one of the third signal line groups, and the plurality of second multiplexing circuits are electrically connected to the third signal line group.

In some embodiments, the display substrate further includes a third signal line. The third signal line is electrically connected with the second multiplexing circuit, and the third signal line controls the electrical connection of the input signal line and the M first signal lines electrically connected with the same second multiplexing circuit in the same period.

In some embodiments, the first multiplexing circuit and the second multiplexing circuit each comprise a plurality of first thin film transistors. One of the source electrode and the drain electrode of the first thin film transistor is electrically connected with the input signal line, the other is electrically connected with the first signal line, and the width-to-length ratio of at least one of the first thin film transistors is larger than or equal to 200 mu m/3.5 mu m.

In some embodiments, the first multiplexing circuit and the second multiplexing circuit each comprise a plurality of first thin film transistors. One of the source electrode and the drain electrode of the first thin film transistor is electrically connected with the input signal line, the other is electrically connected with the first signal line, and the width and the length of at least one first thin film transistor are 320 mu m/3.5 mu m.

In some embodiments, the plurality of first thin film transistors are arranged in a plurality of rows along a first direction, at least two adjacent rows of the first thin film transistors partially overlap in the first direction, and two adjacent first thin film transistors respectively belonging to two adjacent rows are staggered in a second direction. The first direction is the arrangement direction of one row of the pixel circuits, and the second direction is the arrangement direction of a plurality of rows of the pixel circuits.

In some embodiments, the display substrate includes a plurality of gate lines. The grid line comprises main body parts and grid parts which are alternately connected along the second direction, the grid parts are flush with one end of the main body part along the first direction, and the other end of the grid part protrudes out of the edge of the main body part. One of the gate lines is connected to one of the first thin film transistors, and one of the gate portions forms a gate of the first thin film transistor. The grid parts of two adjacent grid lines are protruded towards two opposite sides of the first direction compared with the main body part, the grid lines are divided into a plurality of pairs, one pair comprises two grid lines which are adjacently arranged, and the grid parts of the two grid lines of the one pair are protruded towards the direction approaching to each other. The two rows of the first thin film transistors connected with one pair of the gate lines are partially overlapped in the first direction, and the two rows of the first thin film transistors connected with two adjacent gate lines of two adjacent pairs are respectively not overlapped in the first direction.

In some embodiments, the first multiplexing circuit comprises two of the first thin film transistors, and/or the second multiplexing circuit comprises two of the first thin film transistors.

In some embodiments, the input signal line is configured to be electrically connected with a driver chip. And/or at least one of the pixel circuit, the first multiplexing circuit, and the second multiplexing circuit includes an oxide thin film transistor.

In another aspect, a driving method of a display substrate is provided for driving the display substrate described in any of the above embodiments. The driving method includes that in the bright screen display mode, a first multiplexing circuit controls electrical connection of an input signal line and a first signal line in the same period. In the off-screen wake-up mode, the second multiplexing circuit controls the electrical connection of the input signal line and at least one first signal line in the same period.

In some embodiments, the first signal line group includes M first signal lines, and the second multiplexing circuit is electrically connected to M of the first signal lines, M≥2. The display substrate further comprises P third signal line groups, and the third signal line groups comprise M third signal lines. The second multiplexing circuit is electrically connected with M third signal lines of the third signal line group, and P is more than or equal to 1. The driving method comprises the step that in the off-screen wake-up mode, a second multiplexing circuit controls the electric connection between the input signal line and one first signal line in the same period.

In some embodiments, the driving method further includes the first multiplexing circuit and the second multiplexing circuit alternately controlling the electrical connection of the input signal line and one of the first signal lines at different display frames in the bright screen display mode.

In some embodiments, the driving method further includes, in the off-screen wake-up mode, controlling, by the first multiplexing circuit and the second multiplexing circuit, electrical connection of the same input signal line and the same first signal line in the same period, and controlling, by the first multiplexing circuit and the second multiplexing circuit, electrical connection of the same input signal line and different first signal lines in different periods of one frame period.

In some embodiments, the first signal line group comprises M first signal lines, the second multiplexing circuit is electrically connected with M first signal lines, M is larger than or equal to 2, and the display substrate comprises a third signal line, and the third signal line is electrically connected with the second multiplexing circuit. The driving method further comprises the step that in the bright screen display mode, the second multiplexing circuit controls the circuit between the input signal line and the at least two first signal lines of one signal line group to be cut off, and in the off-screen wake-up mode, the second multiplexing circuit controls the electric connection of the input signal line and the at least two first signal lines of one signal line group in the same time period.

In yet another aspect, a display device is provided. The display device comprises a driving chip and the display substrate in any embodiment. The driving chip is electrically connected with the input signal line of the display substrate and is configured to transmit a data signal to the data signal terminal.

The display device has the same structure and beneficial technical effects as those of the display panel provided in some embodiments described above, and will not be described in detail herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a block diagram of a display device according to some embodiments;

fig. 2 is a component block diagram of a display device according to some embodiments;

FIG. 3 is a display residual image of a display substrate according to the related art;

FIG. 4 is a schematic diagram of a residual display screen of a display substrate according to the related art;

FIG. 5 is a block diagram of a display substrate according to some embodiments;

FIG. 6 is an equivalent circuit diagram of a display substrate according to some embodiments;

FIG. 7 is another equivalent circuit diagram of a display substrate according to some embodiments;

FIG. 8 is yet another equivalent circuit diagram of a display substrate according to some embodiments;

FIG. 9 is a block diagram of a display substrate according to some embodiments;

FIG. 10 is an enlarged view of a portion of area A of FIG. 9;

fig. 11 shows mobility, positive shift of threshold voltage, and negative shift of a transistor using a high mobility oxide material for a semiconductor layer at different thicknesses.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments (some embodiments)", "exemplary embodiment (exemplary embodiments)", "example (example)", "specific example (some examples)", etc. are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. The term "coupled" is used in a broad sense, and may be either permanently coupled, detachably coupled, or integrally formed, or indirectly coupled via an intervening medium, for example. The term "coupled" for example, indicates that two or more elements are in direct physical or electrical contact. The term "coupled" or "communicatively coupled (communicatively coupled)" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and each includes a combination of A, B and C of a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes three combinations of A only, B only, and a combination of A and B.

As used herein, the term "if" is optionally interpreted to mean "when..once..once..or" in response to a determination "or" in response to detection "depending on the context. Similarly, the phrase "if determined" or "if detected [ stated condition or event ]" is optionally interpreted to mean "upon determination" or "in response to determination" or "upon detection of [ stated condition or event ]" or "in response to detection of [ stated condition or event ]" depending on the context.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

As used herein, "parallel", "perpendicular", "equal" includes the stated case as well as the case that approximates the stated case, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the range of acceptable deviation of approximately parallel may be, for example, within 5 ° of deviation, and "perpendicular" includes absolute perpendicular and approximately perpendicular, where the range of acceptable deviation of approximately perpendicular may also be, for example, within 5 ° of deviation. "equal" includes absolute equal and approximately equal, where the difference between the two, which may be equal, for example, is less than or equal to 5% of either of them within an acceptable deviation of approximately equal.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Referring to fig. 1, an embodiment of the present disclosure provides a display device 1000, where the display device 1000 is a product with an image display function. By way of example, the display device 1000 may be any device that displays both motion (e.g., video) and stationary (e.g., still image) and text or images.

In some embodiments, the display device may be an augmented Reality (Augmented Reality, abbreviated as AR) device, a Virtual Reality (VR) device, a Mixed Reality (MR) device. Or in other embodiments, the display device may be any product or component having a display function, such as a television, a notebook, a tablet, a Personal Digital Assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver/navigator, a camera, a display of a camera view (e.g., a display of a rear view camera in a vehicle), a wearable device, an in-vehicle display, an in-flight display, etc.

In some embodiments, from the Light Emitting type of the display device 1000, the display device 1000 may be a Liquid crystal display device (LCD) or the display device 1000 may be an Organic Light-Emitting Diode (OLED) or a Quantum Dot LIGHT EMITTING Diodes (QLED) or the like. In terms of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or the like. The display device 1000 may be rectangular, circular, or the like in shape as viewed from the display device 1000. Some examples of the present disclosure will be schematically described below taking a liquid crystal display device in which the display device is rectangular and planar as an example, but the embodiments of the present disclosure are not limited thereto, and any other display device may also be considered as long as the same technical ideas are applied.

In some embodiments, referring to fig. 2, the display device 1000 may include a display substrate 1100 and a driving chip 1200. Of course, the structure of the display device 1000 is not limited thereto, and it is not necessary to list the structure of the display device 1000, for example, the display device 1000 may further include a camera, a fingerprint recognition sensor, etc., so that the display device 1000 can perform a plurality of different functions such as photographing, video recording, fingerprint recognition, etc.

The display substrate 1100 includes a display area AA and a peripheral area BB disposed around the display area AA. The display area AA is an area of the display substrate 1100 for displaying an image, and the display area AA includes a plurality of sub-pixels P, where the sub-pixels P are minimum light emitting units of the display substrate 1100. The peripheral region BB may be used for providing signal wirings (such as power signal lines, clock signal lines, etc.), driving circuits (such as gate driving circuits), binding portions, etc., and of course, the structure and function of the peripheral region BB are not limited thereto and are not listed here. The driving chip 1200 may be disposed in a peripheral region of the display substrate 1100 and is bonded to the display substrate 1100.

The plurality of sub-pixels P may include at least two sub-pixels emitting different colors of light, which is advantageous for the display substrate to realize color display. In one example, the plurality of subpixels P may include a red subpixel emitting red light, a green subpixel emitting green light, and a blue subpixel emitting blue light. The sub-pixel P may include a pixel circuit 100, and the display substrate 1100 includes a plurality of pixel circuits 100, and one pixel circuit 100 is configured to drive one sub-pixel P to emit light.

With continued reference to fig. 2, the plurality of pixel circuits 100 are arranged in columns along the first direction Y, and the display substrate 1100 includes a plurality of columns of pixel circuits 100, and the plurality of columns of pixel circuits 100 are arranged at intervals along the second direction X. That is, the first direction Y refers to an arrangement direction of a row of pixel circuits, and the second direction X refers to an arrangement direction of a plurality of rows of pixel circuits, wherein the first direction Y intersects with the second direction X, for example, the first direction Y is perpendicular to the second direction X.

As shown in fig. 2, the display substrate 1100 further includes a plurality of first signal line groups 10, where one first signal line group 10 includes at least two first signal lines 11 (two are illustrated in fig. 2 as an example), and one first signal line 11 is electrically connected to one column of pixel circuits 100.

The at least two first signal lines 11 of the first signal line group 10 may be disposed adjacent to each other (as shown in fig. 6), i.e., the at least two first signal lines 11 of one signal line group 10 may be electrically connected to at least two adjacent columns of pixel circuits, or the at least two first signal lines 11 of the first signal line group 10 may be disposed at intervals (as shown in fig. 7), i.e., the at least two first signal lines 11 of one signal line group 10 may be electrically connected to at least two columns of pixel circuits disposed at intervals.

In some embodiments, at least a portion of the plurality of first signal lines 10 is disposed in the display area AA, and the first signal lines 11 may be, for example, data signal lines, and the first signal lines 11 are used to transmit data signals to a column of pixel circuits 100. Next, an embodiment of the present disclosure will be exemplarily described taking the first signal line 11 as a data signal line as an example.

In some embodiments, as shown in fig. 2, the pixel circuit 100 may include a second thin film transistor T20, a control electrode of the second thin film transistor T20 is electrically connected to the scan signal line 12, one of a source electrode and a drain electrode is electrically connected to the first signal line 11, and the other is electrically connected to the pixel electrode.

In some embodiments, in the case where the display substrate is a liquid crystal display substrate, the pixel circuit 100 may further include a common electrode, a capacitor may be formed between the pixel electrode and the common electrode, and in the process of displaying an image on the display substrate, a capacitance may be generated between the pixel electrode and the common electrode, and the electric field may drive liquid crystal molecules of the liquid crystal layer to deflect, so as to adjust the light transmittance of each sub-pixel, thereby performing image display.

The pixel circuit 100 may include an Oxide Thin-film transistor (OTFT), for example, the second Thin-film transistor T20 may be an Oxide Thin-film transistor. The oxide thin film transistor has the characteristic of low leakage current, so that the leakage current of the pixel circuit 100 is reduced, the circuit structure of the pixel circuit 100 is simplified, the aperture ratio of the array substrate is improved, and the light transmittance of the display substrate is improved.

In some embodiments, the driving chip 1200 may be a Source Driver IC (Source Driver IC), where the Source Driver IC is used to transmit data signals to the plurality of first signal lines 11 of the plurality of first signal line groups 10. In order to reduce the cost of the driving chip 1200, a multiplexing circuit (MUX) may be disposed between the driving chip 1200 and the display area AA in the peripheral area BB to reduce the number of signals (such as data signals) output by the driving chip 1200 (at the same time), thereby reducing the cost of the driving chip 1200 and the manufacturing cost of the display substrate 1100.

In some embodiments, the driving chip 1200 may also be a touch and display driver integrated chip (TDDI chip), where the display substrate 1100 may be a display substrate with a touch function, and the display substrate may also be referred to as TDDI display substrate. For example, in the case where the display substrate 1100 is a liquid crystal display substrate, the display substrate 1100 may include an array substrate and a color film substrate (may also be referred to as a counter substrate) disposed opposite to each other, and a liquid crystal layer and a touch structure (In cell) disposed between the array substrate and the color film substrate. For example, the touch structure may be disposed on the array substrate, that is, the touch structure is located between the array substrate and the liquid crystal layer.

In the case that the driving chip 1200 is TDDI chips, the driving chip 1200 may be used to transmit data signals to the plurality of first signal lines 11 included in the plurality of first signal line groups 10, and may also be used to transmit touch signals to a touch structure. In order to reduce the cost of the driving chip 1200, a multiplexing circuit (MUX) may be further disposed between the driving chip 1200 and the display area AA in the peripheral area BB to reduce the number of signals (such as data signals) output by the driving chip 1200 (at the same time), thereby reducing the cost of the driving chip 1200 and the manufacturing cost of the display substrate 1100.

In some embodiments, where the display substrate 1100 includes a touch function, the display substrate 1100 may have a wake-up-off function (Low Power wake up Gesture; abbreviated as LPWG). The off-screen wake-up function is a characteristic function of TDDI display substrates, which can support a sliding operation of a screen in a case that the display substrates are in standby (Sleep in), for example, a user can directly wake up certain functions of the display substrates or corresponding software through preset gestures. However, under the condition that the display substrate is not used (under the condition of standby black screen), the off-screen wake-up function still consumes a certain amount of electricity, in order to not only keep the off-screen wake-up function, but also achieve the purpose of saving power consumption, in the off-screen wake-up mode, a touch signal is continuously provided to a touch electrode in the TDDI display substrate, meanwhile, both the display function and a Charge pump (Charge pump) module of the driving chip 1200 are turned off, so that the power consumption of the TDDI display substrate is reduced, in addition, the touch structure is driven by depending on the voltage of an external power supply in the off-screen wake-up mode, the highest voltage of the driving chip 1200 is the VSP voltage (for example +6v) input at the front end, and the lowest voltage is the VSN voltage (for example-6V) input at the front end.

The related display product (TDDI display substrate) has large area display residues (as shown in fig. 3) after reliability test and in the off-screen wake-up mode, and the longer the stay time in the off-screen wake-up mode, the more serious the residue phenomenon. The inventors have found that an important reason for the above-mentioned residual problem is that, as shown in fig. 4, after the display substrate is subjected to the reliability test, since the transistor of the multiplexing circuit MUX is operated for a long time to cause the transistor to shift to the right (the on-state voltage of the transistor becomes large, the on-state current is reduced), and therefore, in the case that the subsequent display substrate is in the off-screen wake-up mode, the transistor of the multiplexing circuit MUX cannot be sufficiently turned on, and therefore, when the driving chip 1200 transmits the data signal to the first signal line 11, the data signal on the input signal line 41 cannot be completely loaded (transmitted) to the first signal line 11, which results in a significant distortion of the data signal received on the first signal line 11, and thus a distortion of the data signal transmitted to the pixel circuit, and thus a voltage difference is generated between the pixel electrode and the common electrode, which results in a deflection of the liquid crystal layer, and thus a light leakage phenomenon occurs in the black screen mode, which results in the occurrence of the above-mentioned residual problem.

Referring to fig. 5, in order to solve the above technical problems, the display substrate 1100 provided by the embodiments of the present disclosure further includes a plurality of input signal lines 41, a plurality of first multiplexing circuits MUX 1, and a plurality of second multiplexing circuits MUX 2.

A first multiplexing circuit MUX 1 is electrically connected to one input signal line 41 and at least two (all) first signal lines 11 of one first signal line group 10. The first multiplexing circuit MUX 1 controls the electrical connection of the input signal line 41 and one of the first signal lines 11 in the same period, in other words, the first multiplexing circuit MUX 1 can only turn on one of the input signal line 41 and the first signal line 11 in the first signal line group 10 in the same period (same timing) so that the input signal line 41 transmits the data signal individually to each of the first signal lines 11.

Illustratively, the number of first multiplexing circuits MUX 1, the number of input signal lines 41, and the number of first signal line groups 10 are equal. One input signal line 41 is electrically connected to one first multiplexing circuit MUX 1, and a different input signal line 41 is electrically connected to a different first multiplexing circuit MUX 1. One first multiplexing circuit MUX 1 is electrically connected to one first signal line group 10, and a different first multiplexing circuit MUX 1 is electrically connected to a different first signal line group 10.

A second multiplexing circuit MUX 2 is electrically connected to one input signal line 41 and at least two (all) first signal lines 11 of one first signal line group 10, and the second multiplexing circuit MUX 2 controls the electrical connection of the input signal line 41 and at least one first signal line 11 at the same period. In other words, the first multiplexing circuit MUX 1 may turn on at least one first signal line 11 of the input signal line 41 and the first signal line group 10 in the same period so that the input signal line 41 transmits the data signal individually to each first signal line 11 or simultaneously transmits the data signal to the plurality of first signal lines 11.

Illustratively, the number of second multiplexing circuits MUX 2, the number of input signal lines 41, and the number of first signal line groups 10 are equal. One input signal line 41 is electrically connected to one second multiplexing circuit MUX 2, and a different input signal line 41 is electrically connected to a different second multiplexing circuit MUX 2. A second multiplexing circuit MUX 2 is electrically connected to a first signal line group 10, and a different second multiplexing circuit MUX 2 is electrically connected to a different first signal line group 10.

With continued reference to fig. 5, one input signal line 41 is electrically connected to one first multiplexing circuit MUX 1 and one second multiplexing circuit MUX 2, respectively, and at least two first signal lines 11 of one first signal line group 10 are electrically connected to one first multiplexing circuit MUX 1 and one second multiplexing circuit MUX 2, respectively. The input signal lines 41 may transmit control signals to the first signal lines 11 of the same first signal line group 10 through the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2, respectively. In this way, a plurality of different driving methods may be employed to drive the display substrate 1100 to operate at different times by selecting one of the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2. On the one hand, the working time length of the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 is reduced, the risk of right-hand drift of the transistors of the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 is reduced, and the problem of display residues of the display substrate 1100 is reduced or completely eliminated.

In some embodiments of the present disclosure, for simplicity of description, the first multiplexing circuit MUX 1 and/or the second multiplexing circuit MUX 2 control the electrical connection between the input signal line 41 and the first signal line 11, are described as the first multiplexing circuit MUX 1 and/or the second multiplexing circuit MUX 2 operating.

Illustratively, the display substrate 1100 may include a bright screen display mode and a off screen wake-up mode.

In the case where the second multiplexing circuit MUX 2 controls the electrical connection of the input signal line 41 and one of the first signal lines 11 at the same period. One of the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 may be used for operation in a bright screen display mode and a off screen wake-up mode, respectively. For example, in the bright screen display mode, the electrical connection of the input signal line 41 with one first signal line 11 at the same period is controlled by the first multiplexing circuit MUX 1, and in the off-screen wake-up mode, the electrical connection of the input signal line 41 with one first signal line 11 at the same period is controlled by the second multiplexing circuit MUX 2.

Since all the sub-pixels display the same gray scale (the off-screen state displays 0 gray scale) in the off-screen wake-up mode, the same size data signal can be transmitted to all the pixel circuits 100. Based on this, the second multiplexing circuit MUX 2 can control the electrical connection of the input signal line 41 and at least two first signal lines 11 at the same period, in this case. The electrical connection of the input signal line 41 with one first signal line 11 at the same period can be controlled by the first multiplexing circuit MUX 1 in the bright screen display mode, and the electrical connection of the input signal line 41 with one first signal line 11 at the same period can be controlled by the second multiplexing circuit MUX 2 in the off-screen wake-up mode.

It should be noted that, the driving method of the display substrate 1100 is not limited to the above two specific embodiments, and the same technical idea is adopted, and the embodiments of the present disclosure are not limited to this.

In some embodiments, referring to fig. 5 to 8, the first signal line group 10 includes M first signal lines 11, and the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 are electrically connected to the M first signal lines 11 included in the first signal line group 10, that is, the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 are 1:M, where M is equal to or greater than 2. Illustratively, the value of M may be 2, 3, 4, or 6, etc., which are not explicitly recited in the embodiments of the present disclosure. Thus, the number of data signals output by the driving chip 1200 (at the same time) can be reduced, thereby reducing the cost of the driving chip 1200 and the manufacturing cost of the display substrate. Further, as the value of M increases, the number of data signals output by the driving chip 1200 (at the same time) decreases.

Referring to fig. 5 to 8, in the drawings provided by the embodiments of the present disclosure, the value of M is described as 2 by way of example, but the embodiments of the present disclosure are not limited thereto, and the value of M may be set arbitrarily as required. Embodiments of the present disclosure are described below with the value of M being 2 as an example.

In some embodiments, referring to fig. 6, the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 each include M (2) first thin film transistors T10. One of the source and the drain of the first thin film transistor T10 is electrically connected to the input signal line 41, and the other is electrically connected to one of the first signal lines 11. The first thin film transistor T10 may control the electrical connection of the input signal line 41 and the first signal line 11.

In some embodiments, the first multiplexing circuit MUX 1 comprises two first thin film transistors T10. And/or the second multiplexing circuit MUX 2 comprises two first thin film transistors T10.

In some embodiments, at least one of the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 comprises an oxide thin film transistor. Illustratively, the first thin film transistors T10 included in the first and second multiplexing circuits MUX 1 and MUX 2 are oxide thin film transistors. The oxide thin film transistor has the characteristic of low leakage current, and thus, the leakage current of the first thin film transistor T10 is advantageously reduced.

Referring to fig. 6, the display substrate 1100 further includes N second signal line groups 20. The second signal line group 20 includes M second signal lines 21, the M second signal lines 21 of the second signal line group 20 are electrically connected to one first multiplexing circuit MUX 1, and one second signal line 21 controls the electrical connection of one first signal line 11 to the input signal line 41. Wherein N is greater than or equal to 2, and the value of N can be 2,3 or 4, etc. for example, the embodiment of the disclosure is not listed here. The plurality of first multiplexing circuits MUX 1 are alternately electrically connected to the N second signal line groups 20. In this way, it is advantageous to reduce the load on each second signal line group 20, and to reduce the voltage drop on the second signal line 21.

Illustratively, the second signal line 21 may be a gate line, the second signal line 21 being configured to control an electrical connection between the input signal line 41 and the first signal line 11. For example, the second signal line 21 is configured to form a gate (control electrode) of the first thin film transistor T10, thereby controlling on and off of the first thin film transistor T10.

The M second signal lines 21 of the second signal line group 20 correspond to the M first thin film transistors T10 of the first multiplexing circuit MUX 1, respectively, and one second signal line 21 is used to form a gate of one first thin film transistor T10. As shown in fig. 6, when M has a value of 2, one second signal line group 20 includes two second signal lines 21, and the two second signal lines 21 are respectively connected to the gates of the two first thin film transistors T10 of the first multiplexing circuit MUX 1.

Illustratively, N may be 2, that is, the display substrate 1100 includes two second signal line groups 20, and the plurality of first multiplexing circuits MUX 1 are alternately electrically connected to the N second signal line groups 20, and each first multiplexing circuit MUX 1 may be alternately once, for example, from left to right, an odd number (or an even number) of first multiplexing circuits MUX 1 are electrically connected to one second signal line group 20 near the display area, and an even number (or an odd number) of first multiplexing circuits MUX 1 are electrically connected to one second signal line group 20 far from the display area. It is also possible that the first multiplexing circuits MUX 1 alternate once every plurality, such as every 2,3,4 or other number.

In some embodiments, in the bright screen display mode, the first multiplexing circuit MUX 1 may be used to transmit the data signal to the first signal line 11, and the N second signal line groups 20 are used to control the first multiplexing circuit MUX 1, so that the load on the second signal line groups 20 may be reduced, and the voltage drop on the second signal line 21 may be reduced, so that the first thin film transistor T10 included in the first multiplexing circuit MUX 1 is fully turned on, which is beneficial for the data signal transmitted on the input signal line 41 to be fully written on the first signal line 11.

In some embodiments, referring to fig. 6 and 7, the display substrate 1100 further includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, the M third signal lines 31 of the third signal line group 30 are electrically connected to one second multiplexing circuit MUX 2, and one third signal line 31 controls the electrical connection of the input signal line 41 to one first signal line 11. Wherein P is more than or equal to 1. Illustratively, the value of P may be 1, 2,3, etc., which are not explicitly recited in the embodiments of the present disclosure.

Illustratively, the third signal line 31 may be a gate line, the third signal line 31 being configured to control the electrical connection between the input signal line 41 and the first signal line 11. For example, the third signal line 31 is configured to form a gate (control electrode) of the first thin film transistor T10 of the second multiplexing circuit MUX 2, thereby controlling on and off of the first thin film transistor T10.

The M third signal lines 31 of the third signal line group 30 correspond to the M first thin film transistors T10 of the second multiplexing circuit MUX 2, respectively, and one third signal line 31 is used to form a gate of one first thin film transistor T10. As shown in fig. 6 and 7, in the case where the value of M is 2, one third signal line group 30 includes two third signal lines 31, and the two third signal lines 31 are respectively connected to the gates of the two first thin film transistors T10 of the second multiplexing circuit MUX 2.

As shown in fig. 7, when P has a value of 1, that is, the display substrate 1100 includes 1 third signal line group 30, and the plurality of second multiplexing circuits MUX 2 are electrically connected to M third signal lines 31 of the third signal line group 30. In this way, the number of the third signal line groups 30 can be reduced, and the control difficulty of the driving chip can be reduced, which is also advantageous in simplifying the structure of the display substrate 1100, and in reducing the width of the peripheral region.

In the case where the value of P is greater than 1, the value of P may be 2 or 3, or the like, that is, the display substrate 1100 includes a plurality of third signal line groups 30, for example. The plurality of second multiplexing circuits MUX 2 are alternately electrically connected to the P third signal line groups 30. In this way, it is advantageous to reduce the load on each second signal line group 20, and to reduce the voltage drop on the second signal line 21.

In one example, as shown in fig. 6, the value of P may be 2, that is, the display substrate 1100 includes two third signal line groups 30. The plurality of second multiplexing circuits MUX 2 are alternately electrically connected to the two third signal line groups 30, and it may be that each of the first multiplexing circuits MUX 1 is alternately connected to the first (one near the display area AA) third signal line group 30 and the even (or odd) second multiplexing circuits MUX 2 are connected to the second (one far from the display area AA) third signal line group 30, for example, in the second direction X. In this way, it is advantageous to reduce the load on each second signal line group 20, and to reduce the voltage drop on the second signal line 21. It is also possible that the second multiplexing circuits MUX 2 alternate once every plurality, such as every 2, 3, 4 or other number.

In some embodiments, in the case where the value of P is greater than 1, that is, the display substrate 1100 includes a plurality of third signal line groups 30. At this time, the number of the third signal line groups 30 may be equal to the number of the second signal line groups 20 (as shown in fig. 6), and the plurality of second multiplexing circuits MUX 2 are alternately electrically connected to the P third signal line groups 30, so that the plurality of first multiplexing circuits MUX 1 and the plurality of second multiplexing circuits MUX 2 are connected in exactly the same manner, and the plurality of first multiplexing circuits MUX 1 and the plurality of second multiplexing circuits MUX 2 are arranged redundantly with each other.

In some embodiments, in the case where the value of P is greater than 1, that is, the display substrate 1100 includes a plurality of third signal line groups 30, the number of the third signal line groups 30 may be different from the number of the second signal line groups 20 (not shown in the figure), for example, the number of the third signal line groups 30 may be greater than the number of the second signal line groups 20, or the number of the third signal line groups 30 may be less than the number of the second signal line groups 20.

In the case where the value of P is greater than 1, that is, the display substrate 1100 includes the plurality of third signal line groups 30, the plurality of first multiplexing circuits MUX 1 and the plurality of second multiplexing circuits MUX 2 may operate in an alternative manner in any display mode, or the plurality of first multiplexing circuits MUX 1 and the plurality of second multiplexing circuits MUX 2 may alternately operate in any display mode.

Illustratively, in the bright screen display mode, one of the plurality of first multiplexing circuits MUX 1 and the plurality of second multiplexing circuits MUX 2 operates, and in the off-screen wake-up mode, the other of the plurality of first multiplexing circuits MUX 1 and the plurality of second multiplexing circuits MUX 2 operates. That is, in the same display mode, the plurality of first multiplexing circuits MUX 1 and the plurality of second multiplexing circuits MUX 2 operate alternatively, and in different display modes, the plurality of first multiplexing circuits MUX 1 and the plurality of second multiplexing circuits MUX 2 operate alternately. In this way, it is possible to avoid occurrence of picture sticking at the time of mode switching.

Illustratively, the first multiplexing circuits MUX 1 and the second multiplexing circuits MUX 2 may be operated alternately in any mode, for example, in a bright screen display mode, the first multiplexing circuits MUX 1 and the second multiplexing circuits MUX 2 alternately transmit data signals required for at least one frame of a picture, for example, the first multiplexing circuits MUX 1 and the second multiplexing circuits MUX 2 are operated alternately every 1 frame (or 2 frames, 3 frames, 4 frames, 60 frames, etc. are set as required). In this way, the working time of the first multiplexing circuits MUX 1 and the second multiplexing circuits MUX 2 can be shortened, the starting time of the first thin film transistor T10 is reduced, and the risk of drift of the first thin film transistor T10 can be effectively reduced.

It is understood that the driving method of the display substrate provided by the embodiments of the present disclosure is not limited thereto, and the same technical idea is adopted.

In some embodiments, referring to fig. 8, the display substrate 1100 includes a third signal line 31, where the third signal line 31 is electrically connected to all of the second multiplexing circuits MUX 2, the third signal line 31 is controlled in the same period, and the input signal line 41 electrically connected to the same second multiplexing circuits MUX 2 is electrically connected to the M first signal lines 11 included in the first signal line group 10, that is, the third signal line 31 simultaneously connects or disconnects the input signal line 41 to the M first signal lines 11.

Illustratively, as shown in fig. 8, the third signal line 31 may be a gate line, the third signal line 31 being configured to control electrical connection between the input signal line 41 and all the first signal lines 11 of one first signal line group 10. Illustratively, the third signal line 31 is configured to form the gates (control poles) of all the first thin film transistors T10 of the second multiplexing circuit MUX 2, thereby controlling the turning on and off of all the first thin film transistors T10. For example, one third signal line 31 is used to form the gates of M first thin film transistors T10. In this way, the number of the third signal line groups 30 can be greatly reduced, and the control difficulty of the driving chip can be reduced, and the structure of the display substrate 1100 can be simplified, and the width of the peripheral region can be advantageously reduced.

For example, in the case where the display substrate 1100 includes one third signal line 31, the plurality of second multiplexing circuits MUX 2 may operate in the off-screen wake-up mode, and all the pixel circuits 100 in the display area AA may display the same gray scale (0 gray scale), and may simultaneously transmit the data signals of the same size to the pixel circuits 100, and thus all the first thin film transistors T10 of the second multiplexing circuits MUX 2 may be simultaneously turned on, based on which the plurality of second multiplexing circuits MUX 2 may be controlled by one third signal line 31.

In some embodiments, referring to fig. 9 and 10, in the case where the plurality of first multiplexing circuits MUX 1 and the plurality of second multiplexing circuits MUX 2 each include the plurality of first thin film transistors T10, the width-to-length ratio (W/L) of the first thin film transistors T10 is greater than or equal to 200 μm/3.5 μm, that is, the channel structure width-to-length ratio of the first thin film transistors T10 is greater than or equal to 200 μm/3.5 μm. In this way, it is advantageous to improve the charging capability of the first thin film transistor T10, that is, to improve the current gain of the first thin film transistor T10, and to reduce the delay of the transmission signals of the first multiplexing circuit MUX 1 and the plurality of second multiplexing circuits MUX 2. Illustratively, the aspect ratio of the first thin film transistor T10 may be 200 μm/3.5 μm, 250 μm/3.5 μm, 300 μm/3.5 μm, 320 μm/3.5 μm, or 350 μm/3.5 μm, etc., which are not further exemplified by embodiments of the present disclosure.

In some embodiments, the width to length ratio of the first thin film transistor T10 may be 320 μm/3.5 μm. At this time, the charging capability of the first thin film transistor T10 can be greatly improved, and the risk of drift of the first thin film transistor T10 is reduced.

As illustrated in fig. 9 and 10, the display substrate 1100 may include a plurality of gate lines GL, wherein the plurality of gate lines GL may include the second and third signal lines 21 and 31, in other words, the second and third signal lines 21 and 31 may each be a gate line GL. Further, each gate line GL includes a main body portion 42 and a gate portion 43 alternately connected in the second direction X. One gate portion 43 is configured to form a gate of one first thin film transistor T10.

The display substrate 1100 further includes a substrate, referring to fig. 10, the first thin film transistor T10 further includes a semiconductor pattern 44 disposed on a side of the gate portion 43 near the substrate, a front projection of the gate portion 43 on the substrate coincides with a front projection of the semiconductor pattern 44 on the substrate, and in the semiconductor pattern 44, a channel structure 441 is formed at a portion of the substrate overlapping with the front projection of the gate portion 43 on the substrate, a dimension of the channel structure 441 in the first direction Y is a width W of the first thin film transistor T10, a dimension of the channel structure 441 in the second direction X is a length L of the first thin film transistor T10, and a width-to-length ratio W/L of the first thin film transistor T10 refers to a ratio between the width W and the length L of the channel structure 441.

Wherein the semiconductor pattern 44 may be continuous in the first direction Y, or the semiconductor pattern 44 may include a plurality of sub-patterns 442 (two sub-patterns 442 as shown in fig. 10) spaced apart along the first direction Y, and in case the semiconductor pattern 44 includes the plurality of sub-patterns 442, a size of the semiconductor pattern 44 along the first direction Y may be a sum of sizes W' of the plurality of sub-patterns 442 along the first direction Y.

As an example, referring to fig. 10, the gate portion 43 may include a plurality of sub-portions 431 spaced apart along the second direction X, the plurality of sub-portions 431 each extend along the first direction Y, a front projection of one sub-portion 431 on the substrate and a front projection of the semiconductor pattern 44 on the substrate form one channel structure 441, and a length L of the channel structure 441 refers to a dimension of a portion of each semiconductor pattern 44 overlapping with the front projection of one sub-portion 431 along the second direction X, that is, a separate dimension of each channel structure 441.

As shown in fig. 10, the sub-portions 431 are connected end to form an S-shaped structure, and a slit 433 having an opening 432 may be formed between two adjacent sub-portions 431, where the openings 432 of two adjacent slits 433 are opposite. The first thin film transistor T10 further includes a source electrode and a drain electrode located in the middle of the slit 433, the source electrode and the drain electrode being connected to the semiconductor pattern 44 through the slit 433.

In some embodiments, referring to fig. 9 and 10, the dimension D1 of the body portion 42 is smaller than the dimension D2 of the gate portion 43 along the first direction Y, which is advantageous to increase the dimension of the gate portion 43 along the first direction Y, thereby increasing the width-to-length ratio of the first thin film transistor T10, increasing the charging capability of the first thin film transistor T10, i.e. increasing the on-state current of the first thin film transistor T10, and reducing the risk of drift of the first thin film transistor T10.

As shown in fig. 9, the plurality of first thin film transistors T10 are arranged in a plurality of rows along the first direction Y, and one gate line GL is electrically connected to one row of the first thin film transistors T10, or, the plurality of first thin film transistors T10 electrically connected to the same gate line GL form one row of the first thin film transistors T10. At least two adjacent rows of the first thin film transistors T10 partially overlap in the first direction Y, that is, at least two adjacent rows of the first thin film transistors T10 in the plurality of rows of the first thin film transistors T10 partially overlap in the first direction Y. In this way, the space of the rows of the first thin film transistors T10 in the first direction Y can be greatly reduced, which is beneficial to reducing the size of the frame region and realizing the narrow frame of the display substrate 1100.

In the present application, the adjacent two rows of first thin film transistors T10 partially overlap in the first direction Y means that the adjacent two rows of first thin film transistors T10 commonly occupy the same partial space of the display substrate 1100 along the first direction Y, or the projection portions of the adjacent two rows of first thin film transistors T10 overlap in the second direction X. For example, in fig. 9, the first thin film transistors T10 of the first and second rows, and the third and fourth rows from the top down are considered to partially overlap in the first direction Y, and the first thin film transistors T10 of the second and third rows are considered to be misaligned in the first direction Y.

With continued reference to fig. 9, two adjacent first thin film transistors T10 respectively belonging to two adjacent rows are staggered in the second direction X, which is favorable for optimizing the arrangement space of the first thin film transistors T10, improving the arrangement density of the first thin film transistors T10, greatly reducing the space occupied by the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 in the peripheral area, further reducing the width of the peripheral area, and being favorable for realizing a narrow frame of the display substrate 1100.

In some embodiments, as shown in fig. 9, one ends of the body portion 42 and the gate portion 43 in the first direction Y are flush, and the other end of the gate portion 43 protrudes (protrudes) from the edge of the body portion 42. The gate portions 43 of the adjacent two gate lines GL protrude toward opposite sides of the first direction Y than the main body portion 42. The plurality of gate lines GL are divided into a plurality of pairs, and a pair includes two gate lines GL adjacently disposed, and gate portions 43 of the two gate lines GL of the pair protrude toward a direction approaching each other. The two rows of first thin film transistors T10 connected to the pair of gate lines GL are partially overlapped in the first direction Y, and the two rows of first thin film transistors T10 connected to the two adjacent pairs of gate lines GL are not overlapped in the first direction Y, so that the arrangement space of the first thin film transistors T10 is optimized, the arrangement density of the first thin film transistors T10 is improved, the space occupied by the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 in the peripheral area is greatly reduced, the width of the peripheral area is reduced, and the display substrate is facilitated to realize a narrow frame.

Illustratively, as shown in fig. 9, the four gate lines GL are divided into a first gate line, a second gate line, a third gate line, and a fourth gate line in this order from top to bottom. The four gate lines GL are divided into two groups, the first and second gate lines are divided into one group, and the third and fourth gate lines are divided into one group. The gate portion 43 of the first gate line protrudes downward in the first direction Y compared to the main body portion 42, and the gate portion 43 of the second gate line protrudes upward in the first direction Y compared to the main body portion 42. The two rows of first thin film transistors T10 connected to the first gate line and the second gate line partially overlap in the first direction Y. The two rows of first thin film transistors T10 connected to the second gate line and the third gate line do not overlap in the first direction Y.

In some embodiments, the semiconductor pattern 44 may employ a high mobility oxide semiconductor material (High Mobility Metal Oxide Semiconductor; abbreviated as HMOS), which is advantageous in improving the electron mobility of the semiconductor pattern 44 and increasing the on-state current of the first thin film transistor T10. In addition, the high mobility metal oxide semiconductor material also has better illumination stability, which is beneficial to improving the illumination stability of the first thin film transistor T10. The high mobility metal oxide semiconductor material includes, but is not limited to, rare earth doped IZO and IGZO, and the rare earth doping concentration may be between 0.1% -2%. However, since the optical bandgap Eg of the high mobility oxide semiconductor material is small, electrons in the high mobility oxide semiconductor material can absorb part of light in the visible light band to generate electron transition, so that the transistor irradiated by the backlight is turned on in advance, and the newly added defects increase under illumination. As shown in fig. 11, applying a positive voltage (PBTS as shown in fig. 11) to a transistor for a long time causes a positive shift in threshold voltage, applying a negative voltage (NBTS as shown in fig. 11) to a transistor for a long time causes a negative shift in threshold voltage, and the higher the mobility, the more serious the negative shift, resulting in many limitations in the application of oxide semiconductor materials with high mobility. The technical scheme provided by the embodiment of the disclosure can improve and even completely eliminate the residual problem, so that the wide application of high mobility is facilitated.

Some embodiments of the present disclosure also provide a driving method of the display substrate 1100 for driving the display substrate described in any one of the above embodiments. The display substrate comprises a bright screen display mode and a screen-off awakening mode. Of course, the display substrate may also include other display modes, which are not listed here.

The driving method of the display substrate 1100 includes:

in the bright screen display mode, the first multiplexing circuit MUX 1 controls the electrical connection of the input signal line 41 and one first signal line at the same period.

In the off-screen wake-up mode, the second multiplexing circuit MUX 2 controls the electrical connection of the input signal line with at least one first signal line during the same period.

Based on the above driving method, the display substrate 1100 may control the electrical connection of the input signal line 41 and the first signal line 11 at the same period using the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2, respectively, in different display modes. Thus, even if the display substrate undergoes long-time bright screen display (such as a reliability test), the first thin film transistor T10 of the first multiplexing circuit MUX 1 drifts (such as right drift), after the display substrate is switched to the off-screen wake-up mode, the drift of the first thin film transistor T10 of the first multiplexing circuit MUX 1 does not affect the electrical connection between the input signal line 41 and the first signal line 11, that is, the problem that the data signal is distorted in the process of passing through the second multiplexing circuit MUX 2 is solved, so that the risk that the display substrate remains is reduced.

In some embodiments, referring to FIGS. 6 and 7, the first signal line group 10 includes M first signal lines 11, and the second multiplexing circuit MUX 2 is electrically connected to the M first signal lines, M≥2. The display substrate 1100 further includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, and a second multiplexing circuit MUX 2 is electrically connected to the M third signal lines 31 of the third signal line group 30, where P is greater than or equal to 1.

At this time, the driving method of the display substrate further includes:

In the off-screen wake-up mode, the second multiplexing circuit MUX 2 controls the electrical connection of the input signal line 41 to one of the first signal lines 11 during the same period. That is, the second multiplexing circuit MUX 2 is used to conduct only the input signal line 41 with one of the first signal lines 11 in one of the first signal line groups 10 in the same period.

At this time, the driving method of the display substrate further includes:

In the bright screen display mode, the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 alternately electrically connect the input signal line 41 with one first signal line 11 at different display frames. In this way, the total times and total duration of the turning-on of the first thin film transistor T10 of the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 in the bright screen display mode can be reduced, so that the risk of drift of the first thin film transistor T10 is reduced, the accuracy of data signal transmission in the bright screen display mode is improved, and the display of the display substrate in the long-time bright screen display mode is ensured not to be distorted.

In other embodiments, referring to FIGS. 6 and 7, the first signal line group 10 includes M first signal lines 11, and the second multiplexing circuit MUX 2 is electrically connected to the M first signal lines, M≥2. The display substrate 1100 further includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, and a second multiplexing circuit MUX 2 is electrically connected to the M third signal lines 31 of the third signal line group 30, where P is greater than or equal to 1.

At this time, the driving method of the display substrate further includes:

In the off-screen wake-up mode, the first multiplexing circuit MUX1 and the second multiplexing circuit MUX 2 both control the electrical connection of the same input signal line 41 and the same first signal line 11 in the same period. And the first multiplexing circuit MUX1 and the second multiplexing circuit MUX 2 control the electrical connection of the same input signal line with different first signal lines at different periods of one frame period.

That is, the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 operate simultaneously, and the two first thin film transistors T10 respectively belonging to the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 are connected in parallel, which is favorable for raising the on-state current of the two first thin film transistors T10, reducing the risk of distortion of the data signal during the process of passing through the two first thin film transistors T10, and reducing the risk of residual occurrence of the display substrate.

In some embodiments, referring to FIG. 8, the first signal line group 10 includes M first signal lines 11, and the second multiplexing circuit MUX 2 is electrically connected to the M first signal lines 11, M≥2. The display substrate 1100 includes a third signal line 31, and the third signal line 31 is electrically connected to the second multiplexing circuit MUX 2.

At this time, the driving method of the display substrate further includes:

in the bright screen display mode, the second multiplexing circuit MUX 2 controls the input signal line 41 and all the first signal lines 11 of the first signal line group 10 to be disconnected.

In the off-screen wake-up mode, the second multiplexing circuit MUX 2 controls the electrical connection between the input signal line 41 and at least two first signal lines at the same time period.

That is, in the case where the display substrate 1100 includes only one third signal line 31, and in the bright screen display mode, the second multiplexing circuit MUX 2 does not operate, the electrical connection between the input signal line 41 and the first signal line 11 is controlled via the first multiplexing circuit MUX 1. And in the off-screen wake-up mode, the second multiplexing circuit MUX 2 electrically connects the input signal line 41 and all the first signal lines 11 of one signal line group 10 at the same time. At this time, it is possible to greatly reduce the number of the third signal line groups 30 and the control difficulty of the driving chip, and to simplify the structure of the display substrate 1100 and to advantageously reduce the width of the peripheral region.

While the invention has been described with reference to specific embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising:

a plurality of input signal lines, a plurality of columns of pixel circuits, and a plurality of first signal line groups, one of the first signal line groups including at least two first signal lines, one of the first signal lines being electrically connected to one column of the pixel circuits, and

A plurality of first multiplexing circuits electrically connected to one of the input signal lines and the at least two first signal lines of one of the first signal line groups, the first multiplexing circuits controlling electrical connection of the input signal lines and one of the first signal lines at the same period;

A plurality of second multiplexing circuits electrically connected to one of the input signal lines and the at least two first signal lines of one of the first signal line groups, the second multiplexing circuits controlling the electrical connection of the input signal lines and at least one of the first signal lines at the same time period;

Wherein one of the input signal lines is electrically connected to one of the first multiplexing circuits and one of the second multiplexing circuits, respectively, and the at least two first signal lines of one of the first signal line groups are electrically connected to one of the first multiplexing circuits and one of the second multiplexing circuits, respectively.

2. The display substrate of claim 1, wherein the display substrate comprises a transparent substrate,

The first signal line group comprises M first signal lines, the first multiplexing circuit and the second multiplexing circuit are electrically connected with the M first signal lines, and M is more than or equal to 2;

The display substrate further comprises N second signal line groups, wherein each second signal line group comprises M second signal lines, the M second signal lines of each second signal line group are electrically connected with one first multiplexing circuit, and one second signal line controls the electrical connection of one first signal line and the input signal line, wherein N is more than or equal to 2;

wherein the plurality of first multiplexing circuits are alternately connected to the N second signal line groups.

3. The display substrate of claim 2, wherein the display substrate further comprises:

The P third signal line groups comprise M third signal lines, the M third signal lines of the third signal line groups are electrically connected with one second multiplexing circuit, one third signal line controls the electric connection of the input signal line and one first signal line, and P is more than or equal to 1.

4. The display substrate according to claim 3, wherein,

The number of the second signal line groups is the same as that of the third signal line groups, and the plurality of second multiplexing circuits are alternately electrically connected with the P third signal line groups.

5. The display substrate according to claim 3, wherein,

The display substrate comprises a third signal line group, and the second multiplexing circuits are electrically connected with the third signal line group.

6. The display substrate of claim 2, wherein the display substrate further comprises:

And the third signal line is electrically connected with the second multiplexing circuit and controls the electric connection between the input signal line and the M first signal lines which are electrically connected with the same second multiplexing circuit in the same period.

7. The display substrate according to any one of claims 1 to 6, wherein,

The first multiplexing circuit and the second multiplexing circuit each comprise a plurality of first thin film transistors, one of the source electrode and the drain electrode of each first thin film transistor is electrically connected with the input signal line, the other is electrically connected with the first signal line, and the width-to-length ratio of at least one first thin film transistor is larger than or equal to 200 mu m/3.5 mu m.

8. The display substrate according to any one of claims 1 to 6, wherein,

The first multiplexing circuit and the second multiplexing circuit each comprise a plurality of first thin film transistors, one of the source electrode and the drain electrode of each first thin film transistor is electrically connected with the input signal line, the other is electrically connected with the first signal line, and the width and the length of at least one first thin film transistor are 320 mu m/3.5 mu m.

9. The display substrate of claim 7, wherein the display substrate comprises a transparent substrate,

The plurality of first thin film transistors are arranged in a plurality of rows along a first direction, at least two adjacent rows of the first thin film transistors are partially overlapped in the first direction, the two adjacent first thin film transistors respectively belonging to the two adjacent rows are staggered in a second direction, the first direction is the arrangement direction of one row of pixel circuits, and the second direction is the arrangement direction of a plurality of rows of pixel circuits.

10. The display substrate of claim 9, wherein the display substrate comprises a transparent substrate,

The display substrate comprises a plurality of grid lines, wherein the grid lines comprise main body parts and grid parts which are alternately connected along the second direction, and the grid parts are flush with one end of the main body part and the other end of the grid part protrudes out of the edge of the main body part along the first direction;

The grid parts of two adjacent grid lines are protruded towards two opposite sides of the first direction compared with the main body part, the grid lines are divided into a plurality of pairs, one pair comprises two adjacent grid lines, and the grid parts of the two grid lines of the one pair are protruded towards the direction approaching to each other;

The two rows of the first thin film transistors connected with one pair of the gate lines are partially overlapped in the first direction, and the two rows of the first thin film transistors connected with two adjacent gate lines of two adjacent pairs are respectively not overlapped in the first direction.

11. The display substrate according to claim 7, wherein the first multiplexing circuit comprises two of the first thin film transistors, and/or the second multiplexing circuit comprises two of the first thin film transistors.

12. The display substrate of claim 1, wherein the display substrate comprises a transparent substrate,

The input signal lines are configured to be electrically connected to the driver chip and/or,

At least one of the pixel circuit, the first multiplexing circuit, and the second multiplexing circuit includes an oxide thin film transistor.

13. The method for driving a display substrate according to any one of claims 1 to 12, wherein the display substrate includes a bright screen display mode and a off-screen wake-up mode, the method comprising:

In the bright screen display mode, the first multiplexing circuit controls the electric connection of the input signal line and one first signal line in the same period;

in the off-screen wake-up mode, the second multiplexing circuit controls the electrical connection of the input signal line and at least one first signal line in the same period.

14. The driving method according to claim 13, wherein,

The display substrate further comprises P third signal line groups, wherein each third signal line group comprises M third signal lines, the second multiplexing circuit is electrically connected with the M third signal lines of the third signal line groups, and P is more than or equal to 1;

the driving method includes:

In the off-screen wake-up mode, the second multiplexing circuit controls the electrical connection of the input signal line and one of the first signal lines in the same period.

15. The driving method according to claim 14, characterized in that the driving method further comprises:

In the bright screen display mode, the first multiplexing circuit and the second multiplexing circuit alternately control the electrical connection of the input signal line and one of the first signal lines in different display frames.

16. The driving method according to claim 14 or 15, characterized in that the driving method further comprises:

In the off-screen wake-up mode, the first multiplexing circuit and the second multiplexing circuit are both controlled to be electrically connected with the same input signal line and the same first signal line in the same period, and the first multiplexing circuit and the second multiplexing circuit are controlled to be electrically connected with the same input signal line and different first signal lines in different periods of one frame period.

17. The driving method according to claim 13, wherein,

The first signal line group comprises M first signal lines, the second multiplexing circuit is electrically connected with the M first signal lines, and M is more than or equal to 2; the display substrate comprises a third signal line, and the third signal line is electrically connected with the second multiplexing circuit;

the driving method further includes:

in the bright screen display mode, the second multiplexing circuit controls circuit cut-off between the input signal line and the at least two first signal lines of one signal line group;

In the off-screen wake-up mode, the second multiplexing circuit controls the electrical connection of the input signal line and the at least two first signal lines of one signal line group at the same period.

18. A display device, comprising:

The display substrate according to any one of claims 1 to 12;

and the driving chip is electrically connected with the input signal line of the display substrate and is configured to transmit a data signal to the data signal terminal.