CN121237162A - An eFuse unit circuit with integrated dynamic current compensation module - Google Patents

Abstract

The invention provides an eFuse fuse unit circuit integrating a dynamic current compensation module, which belongs to the technical field of semiconductor memories and comprises a digital control module, a bias circuit fuse unit output module, voltage dividing resistors R1, R3 and R4 connected with the bias circuit, and a fuse programming module, wherein when a low-level control signal is input into an EN1 end of the fuse programming module, an NMOS tube N13 of the fuse programming module is opened, a resistor R0 of the fuse programming module starts fuse programming through high current, a silicide layer on the resistor R0 is fused after completion, so that the resistor R0 is converted into a high-resistance state from low resistance, the resistance value of the resistor R0 is larger than that of the voltage dividing resistors R1, R3 and R4, when programming is completed, the output Y is turned over to 0 from 1, and the fuse unit output module outputs an output signal to other circuits for control. The invention has low power consumption, high stability and wide current regulation capability.

Description

EFuse fuse unit circuit integrated with dynamic current compensation module

Technical Field

The invention belongs to the technical field of semiconductor memories, and particularly relates to an eFuse fuse unit circuit integrated with a dynamic current compensation module.

Background

EFuses are one-time programmable memories that enable data storage by melting metal fuses, the data of which cannot be modified or erased once written. The technology is widely applied to sensitive information such as unique Identification (ID) codes, encryption keys and the like of storage equipment so as to ensure the safety and the integrity of data. In modern SoC designs, eFuses are used to prevent hacking and unauthorized access, and their built-in sophisticated control and multiple protection features can quickly cut off abnormal currents, response speed and reliability superior to traditional schemes.

As shown in fig. 3, the conventional fuse circuit is designed to have different parameters, such as clock frequency pin function of the chip, etc., configured by engineers according to the purpose and function of the chip during the production process. These parameters are typically set by fuses. In the use process, if the configuration of the chip needs to be changed, the fuse needs to be reset, and the traditional fuse belongs to an independent device in the chip, so that the occupied space is large.

Compared with the traditional fuse circuit, the eFuse fuse unit structure of the invention is a one-time programmable memory which can realize data storage by melting the silicide layer on the polycrystalline resistor to convert the silicide layer from a low-resistance state to a high-resistance state and changing the on-off state of the circuit, and the data cannot be modified or erased once written. eFuses in the present invention may be used in a number of application scenarios, such as chip protection, power management, circuit calibration, and the like. In terms of chip protection, eFuses of the invention may be used to protect circuitry from over-voltage or over-current, as well as tamper-proof, and the like. In terms of power management, eFuses may be used to control current and voltage, ensuring that the circuit is functioning properly. In terms of circuit calibration, eFuses in the invention may be used to calibrate circuit parameters such as clock frequency and current bias. The eFuses generally have the advantages of small volume, low power consumption, strong programmability, high reliability, difficult erasure and the like, and can be widely applied to sensitive information such as unique Identification (ID) codes, encryption keys and the like of storage equipment so as to ensure the safety and the integrity of data. In modern SoC designs, eFuses are used to prevent hacking and unauthorized access, and their built-in sophisticated control and multiple protection features can quickly cut off abnormal currents, response speed and reliability superior to traditional fuse structures.

The protection device using the traditional fuse as the basic circuit has the advantages that the fusing value is greatly influenced by the ambient temperature in practical application, because the alloy material characteristics of the traditional fuse can drift along with the temperature change, the traditional fuse can be fused by mistake at high temperature, the response is delayed at low temperature, the protection threshold is uncontrollable, the fusing precision is low, the fixed fusing curve cannot adapt to dynamic load (such as motor starting surge), the error range is often up to +/-20%, and the requirements of precision electronic equipment are difficult to meet.

In view of the above problems, although the low cost and tamper resistant characteristics of conventional fuses are still valuable in a simple scenario in the prior art, the need for intelligence and maintenance-free in order to save chip area is pushing electronic fuses such as eFuses to accelerate replacement.

Disclosure of Invention

Aiming at the problems existing in the prior art, the eFuse fuse unit circuit integrated with the dynamic current compensation module is higher in integration level, saves more chip area, reduces impact of transient current on a system, adapts to complex working conditions, is higher in safety, is programmable in current and voltage threshold value, dynamically matches load change, and adapts to application scenes such as battery aging and temperature fluctuation.

The eFuse fuse unit circuit integrating the dynamic current compensation module is characterized by comprising a digital control module, a bias circuit and a fuse unit output module, wherein the bias circuit and the fuse unit output module are respectively connected with the digital control module, the bias circuit is connected with the fuse unit output module, the eFuse fuse unit circuit also comprises voltage dividing resistors R1, R3 and R4 and a fuse programming module, the voltage dividing resistors R1, R3 and R4 are connected with the bias circuit, and the fuse programming module is connected with the fuse unit output module;

The bias circuit structure provides stable bias current, the digital control module is used for controlling the bias circuit to generate bias current,

When a low-level control signal is input to the EN1 end, an NMOS tube N13 of the fuse programming module is opened, a resistor R0 of the fuse programming module starts fuse programming through high current, a silicide layer on the resistor R0 is blown after programming is finished, so that the resistor R0 is converted into a high-resistance state from low resistance, the resistance value of the resistor R0 is larger than that of the voltage dividing resistors R1, R3 and R4, programming is finished, the output Y is turned over from 1 to 0 at the moment,

The fuse unit output module outputs an output signal of the entire fuse unit circuit to other circuit control.

Further, the digital control module comprises a PMOS tube P1, a PMOS tube P2, an NMOS tube N1 and an NMOS tube N2, wherein the grid electrode of the NMOS tube N1 is connected with the grid electrode of the PMOS tube P1, the grid electrode of the NMOS tube N2 and the EN end to receive a bias circuit switch digital signal, the source electrodes of the NMOS tube N1 and the NMOS tube N2 are grounded, the drain electrode of the PMOS tube P1 is connected with the source electrode of the NMOS tube N2 and the grid electrode of the PMOS tube P2, and the source electrode of the PMOS tube P1 is connected with a power supply;

The PMOS tube P1 and the NMOS tube N2 form an inverter, the inverter is output to the grid electrode of the PMOS tube P2 and is connected with a power supply, namely the PMOS tube P2 is used as a pull-up tube of the bias circuit.

Further, the bias circuit comprises PMOS transistors P3, P4, P5, P6, NMOS transistors N3, N4, N5, N6, N7, N8, N9,

The grid electrode of the PMOS tube P3 is connected with the grid electrode of the PMOS tube P2 in parallel with a power supply,

The source electrode of the PMOS tube P3 is connected with the drain electrode of the PMOS tube P5, the grid electrode of the PMOS tube P3, the grid electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P4, and is connected with the drain electrode of the PMOS tube P2 of the digital control module;

The source electrode of the PMOS tube P5 is connected with the source electrode of the NMOS tube N3, and the source electrode of the PMOS tube P4 is connected with the drain electrode of the NMOS tube N5, the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N6;

The source electrode of the PMOS tube P6 is connected with the drain electrode of the NMOS tube N6 and the grid electrode of the NMOS tube N8, the source electrode of the NMOS tube N6 is connected with the drain electrode of the NMOS tube N8 and is connected with the fuse unit output module, the source electrode of the NMOS tube N8 is grounded, the grid electrode of the PMOS tube P6 is connected with the grid electrode of the PMOS tube P3;

The source electrode of the NMOS tube N7 is connected with the drain electrode of the NMOS tube N9, the grid electrode of the NMOS tube N7 is connected with the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N6, and is connected with the fuse unit output module;

The MINUS ends of the resistors R1, R3 and R4 are respectively connected with the drain electrode of the PMOS tube P3, the drain electrode of the PMOS tube P6 and the drain electrode of the PMOS tube P4.

Further, the fuse programming module comprises a PMOS tube P8, an NMOS tube N10, an NMOS tube N11, an NMOS tube N12 and an NMOS tube N13;

The grid electrode of the PMOS tube P8 is connected with the grid electrode of the NMOS tube N10, the EN1 end is connected with a fuse programming digital signal, the source electrode of the PMOS tube P8 is grounded, and the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N10, the drain electrode of the NMOS tube N11 and the grid electrode of the NMOS tube N13;

The grid electrode of the NMOS tube N11 is connected with a grid electrode of the NMOS tube N12 to form a power supply, the source electrode of the NMOS tube N11 is connected with the drain electrode of the NMOS tube N12, and the source electrodes of the NMOS tube N12 and the NMOS tube N13 are grounded;

The drain electrode of the NMOS tube N13 is connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the fuse unit output module.

Further, the fuse unit output module comprises a resistor R2, a PMOS tube P9, a PMOS tube P10, a PMOS tube P11, a PMOS tube P12, a PMOS tube P13, an NMOS tube N14, an NMOS tube N15, an NMOS tube N16, an NMOS tube N17 and an NMOS tube N18;

the source electrode of the PMOS tube P9 is connected with a power supply, the grid electrode of the PMOS tube P9 is connected with the MINUS end of the resistor R2, the PLUS end of the resistor R2 is grounded, and the drain electrode of the PMOS tube P9 is connected with the other end of the resistor R0;

The grid electrode of the PMOS tube P10 is connected with the grid electrode of the PMOS tube P3, the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P6 of the bias circuit, the drain electrode of the PMOS tube P10 is connected with one end of a resistor R0 and the drain electrode of an NMOS tube N13, the source electrode of the PMOS tube P10 and the drain electrode of an NMOS tube N14, the grid electrode of a PMOS tube P11, the grid electrode of an NMOS tube N16, the drain electrode of the PMOS tube P10 and the drain electrode of the NMOS tube N13,

The drain electrode of the PMOS tube P13 is connected with the drain electrode of the NMOS tube N17;

The grid electrode of the NMOS tube N14 is used as a first connecting end of the fuse unit output module and the paranoid circuit, is connected with the grid electrode of the NMOS tube N7, the source electrode of the NMOS tube N14 is connected with the drain electrode of the NMOS tube N15,

The grid electrode of the NMOS tube N15 is used as a second connecting end of the fuse unit output module and the paranoid circuit, is connected with the source electrode of the PMOS tube P6, and the source electrode of the NMOS tube N15 is grounded;

the source electrode of the PMOS tube P11 is connected with a power supply, and the drain electrode of the PMOS tube P11 is connected with the drain electrode of the NMOS tube N16, the grid electrode of the PMOS tube P12 and the grid electrode of the NMOS tube N18;

The source electrode of the PMOS tube P12 is connected with a power supply, the drain electrode of the PMOS tube P12 is connected with the source electrode of the PMOS tube P13, the source electrode of the NMOS tube N17 is connected with the drain electrode of the NMOS tube N18, and the source electrode of the NMOS tube N18 is grounded;

the gate of the PMOS transistor P13 is connected to the FDLP clock signal, and the gate of the NMOS transistor N17 is connected to FDLN (clock signal).

Further, the resistances of the resistors R1, R3, and R4 are 5K ohms.

Further, the resistor R0 is a poly resistor.

Compared with the prior art, the beneficial technical effects of the invention adopting the technical scheme are as follows:

1. The eFuse fuse unit structure in the invention has higher integration level, saves more chip area and can save about 90 percent of chip area compared with the traditional fuse scheme.

2. The eFuse fuse cell structure in the invention has visual and controllable programming process.

3. In the invention, the fuse resistor R0 adopts a poly resistor structure, the impedance is stable in an unprogrammed state, and the resistance value after programming and programming can be regulated and controlled

4. The eFuse fuse unit structure can still perform fuse programming after CP test (Chip Probing Test), optimize product performance and reduce production cost.

5. Biasing circuitry is present in the present invention and may control whether or not it is on so the static power consumption of the present invention is substantially 0 compared to conventional eFuses.

In summary, the present invention improves upon the deficiencies of conventional fuse structures to save chip area and optimize static power consumption relative to conventional eFuses.

Drawings

FIG. 1 is a diagram of a digital control module and biasing circuit according to the present invention;

fig. 2 is a circuit diagram of a fuse unit output module and a fuse unit output module according to the present invention.

Fig. 3 is a conventional eFuse cell structure.

Detailed Description

For a better understanding of the technical content of the present invention, specific examples are set forth below, along with the accompanying drawings.

Aspects of the invention are described herein with reference to the drawings, in which there are shown many illustrative embodiments. The embodiments of the present invention are not limited to the embodiments described in the drawings. It is to be understood that this invention is capable of being carried out by any of the various concepts and embodiments described above and as such described in detail below, since the disclosed concepts and embodiments are not limited to any implementation. Additionally, some aspects of the disclosure may be used alone or in any suitable combination with other aspects of the disclosure.

As shown in FIGS. 1 and 2, the eFuse fuse unit circuit integrated with the dynamic current compensation module in this embodiment includes a digital control module, a bias circuit and a fuse unit output module respectively connected with the digital control module, wherein the bias circuit is connected with the fuse unit output module, and further includes voltage dividing resistors R1, R3, R4 and a fuse programming module, the voltage dividing resistors R1, R3, R4 are connected with the bias circuit, and the fuse programming module is connected with the fuse unit output module, and in the embodiment, the resistance of R1, R3, R4 is 5KΩ or 1KΩ.

The bias circuit structure provides stable bias current, the digital control module is used for controlling the bias circuit to generate bias current,

When a low-level control signal is input to the EN1 end, an NMOS tube N13 of the fuse programming module is opened, the resistor R0 of the fuse programming module starts fuse programming through high current, a silicide layer on the resistor R0 is blown after programming is finished, so that the resistor R0 is converted into a high-resistance state from low resistance, the resistance value of the resistor R0 is larger than that of the voltage dividing resistors R1, R3 and R4, programming is finished, the output Y is turned over from 1 to 0 at the moment, and the fuse unit output module outputs the output signal of the whole fuse unit circuit to other circuits for control, wherein the resistor R0 uses poly as the fuse resistor.

The digital control module comprises a PMOS tube P1, a PMOS tube P2, an NMOS tube N1 and an NMOS tube N2, wherein the grid electrode of the NMOS tube N1 is connected with the grid electrode of the PMOS tube P1, the grid electrode of the NMOS tube N2 and the EN end to receive a bias circuit switch digital signal, the source electrodes of the NMOS tube N1 and the NMOS tube N2 are grounded, the drain electrode of the PMOS tube P1 is connected with the source electrode of the NMOS tube N2 and the grid electrode of the PMOS tube P2, and the source electrode of the PMOS tube P1 is connected with a power supply;

The PMOS tube P1 and the NMOS tube N2 form an inverter, the inverter is output to the grid electrode of the PMOS tube P2 and is connected with a power supply, namely the PMOS tube P2 is used as a pull-up tube of the bias circuit.

The bias circuit comprises PMOS tubes P3, P4, P5 and P6, NMOS tubes N3, N4, N5, N6, N7, N8 and N9,

The grid electrode of the PMOS tube P3 is connected with the grid electrode of the PMOS tube P2 in parallel with a power supply,

The source electrode of the PMOS tube P3 is connected with the drain electrode of the PMOS tube P5, the grid electrode of the PMOS tube P3, the grid electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P4, and is connected with the drain electrode of the PMOS tube P2 of the digital control module;

The source electrode of the PMOS tube P5 is connected with the source electrode of the NMOS tube N3, N3 is an inverted ratio tube, and the source electrode of the PMOS tube P4 is connected with the drain electrode of the NMOS tube N5, the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N6;

The source electrode of the PMOS tube P6 is connected with the drain electrode of the NMOS tube N6 and the grid electrode of the NMOS tube N8, the source electrode of the NMOS tube N6 is connected with the drain electrode of the NMOS tube N8 and is connected with the fuse unit output module, the source electrode of the NMOS tube N8 is grounded, the grid electrode of the PMOS tube P6 is connected with the grid electrode of the PMOS tube P3;

The source electrode of the NMOS tube N7 is connected with the drain electrode of the NMOS tube N9, the grid electrode of the NMOS tube N7 is connected with the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N6, and is connected with the fuse unit output module;

The MINUS ends of the resistors R1, R3 and R4 are respectively connected with the drain electrode of the PMOS tube P3, the drain electrode of the PMOS tube P6 and the drain electrode of the PMOS tube P4.

The fuse programming module comprises a PMOS tube P8, an NMOS tube N10, an NMOS tube N11, an NMOS tube N12 and an NMOS tube N13;

The grid electrode of the PMOS tube P8 is connected with the grid electrode of the NMOS tube N10, the EN1 end is connected with a fuse programming digital signal, the source electrode of the PMOS tube P8 is grounded, and the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N10, the drain electrode of the NMOS tube N11 and the grid electrode of the NMOS tube N13;

The grid electrode of the NMOS tube N11 is connected with a grid electrode of the NMOS tube N12 to form a power supply, the source electrode of the NMOS tube N11 is connected with the drain electrode of the NMOS tube N12, and the source electrodes of the NMOS tube N12 and the NMOS tube N13 are grounded;

The drain electrode of the NMOS tube N13 is connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the fuse unit output module.

The fuse unit output module comprises a resistor R2, a PMOS tube P9, a PMOS tube P10, a PMOS tube P11, a PMOS tube P12, a PMOS tube P13, an NMOS tube N14, an NMOS tube N15, an NMOS tube N16, an NMOS tube N17 and an NMOS tube N18;

the source electrode of the PMOS tube P9 is connected with a power supply, the grid electrode of the PMOS tube P9 is connected with the MINUS end of the resistor R2, the PLUS end of the resistor R2 is grounded, and the drain electrode of the PMOS tube P9 is connected with the other end of the resistor R0;

The grid electrode of the PMOS tube P10 is connected with the grid electrode of the PMOS tube P3, the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P6 of the bias circuit, the drain electrode of the PMOS tube P10 is connected with one end of a resistor R0 and the drain electrode of an NMOS tube N13, the source electrode of the PMOS tube P10 and the drain electrode of an NMOS tube N14, the grid electrode of a PMOS tube P11, the grid electrode of an NMOS tube N16, the drain electrode of the PMOS tube P10 and the drain electrode of the NMOS tube N13,

The drain electrode of the PMOS tube P13 is connected with the drain electrode of the NMOS tube N17;

The grid electrode of the NMOS tube N14 is used as a first connecting end of the fuse unit output module and the paranoid circuit, is connected with the grid electrode of the NMOS tube N7, the source electrode of the NMOS tube N14 is connected with the drain electrode of the NMOS tube N15,

The grid electrode of the NMOS tube N15 is used as a second connecting end of the fuse unit output module and the paranoid circuit, is connected with the source electrode of the PMOS tube P6, and the source electrode of the NMOS tube N15 is grounded;

the source electrode of the PMOS tube P11 is connected with a power supply, and the drain electrode of the PMOS tube P11 is connected with the drain electrode of the NMOS tube N16, the grid electrode of the PMOS tube P12 and the grid electrode of the NMOS tube N18;

The source electrode of the PMOS tube P12 is connected with a power supply, the drain electrode of the PMOS tube P12 is connected with the source electrode of the PMOS tube P13, the source electrode of the NMOS tube N17 is connected with the drain electrode of the NMOS tube N18, and the source electrode of the NMOS tube N18 is grounded;

the gate of the PMOS transistor P13 is connected to the FDLP clock signal, and the gate of the NMOS transistor N17 is connected to FDLN (clock signal).

In this embodiment, specifically, substrates of the PMOS transistors P2, P3, P4, P5, P6, P7, and P10 are all connected to a power supply, and substrates of the NMOS transistors N3, N4, N5, N6, N7, N8, N9, N14, and N15 are all grounded;

The R0 adopts a poly resistor as a fuse wire, so that defects of a thin gate oxide layer and a silicide substrate thereof are prevented from being introduced in the forming process of metal silicide, therefore, the invention adopts a polysilicon interconnection structure, when programming is carried out, under the action of higher current density between two electrodes, metal atoms can migrate along the movement direction of electrons, electromigration can also increase along with continuous increase of current density, if electromigration is severe, atoms are accumulated on an anode of a polysilicon fuse chain to form a hillock, a cavity is formed due to shortage of atoms on a cathode at the moment, and finally, disconnection is caused, so that programming is completed, and the phenomenon is the Electromigration (EM) phenomenon. Electromigration is the nature of fusing. Is the flow relationship for the electromigration case:

The resistance of the fuse after programming can be said to increase exponentially relative to its initial resistance of approximately 20 to 150 ohms.

Because the resistances of the resistors R1, R3 and R4 are equal and correspond to three paths of bias current respectively, and in order to make the bias current more stable, the NMOS tube N3 at the main bias circuit is made into an inverse ratio tube, when the resistance of R0 is smaller than that of R1, R3 and R4, the current flowing through the PMOS tube P10 is larger than that of N14 and N15 because of the constant current of N14 and N15, the output end of the PMOS tube P10 can not be overturned at the moment, when the resistance of R0 is larger than that of R1, R3 and R4, the current flowing through the PMOS tube P10 is smaller than that of N14 and N15 because of the constant current of N14 and N15, the output end can be overturned at the moment because the resistance of R0 is smaller than that of R1, R3 and R4 = 5KΩ are adopted in the bias circuit, and the Casode structure has stronger stability and faster response speed, and when the resistance of R0 is larger than 5KΩ, (R1 = R4 = 5KΩ), the output end can be overturned at the moment

In summary, the present example provides an eFuse fuse unit circuit integrated with a dynamic current compensation module, which has low power consumption, high stability, adaptation to complex working conditions, higher safety, programmable current and voltage thresholds, dynamic matching of load variation, adaptation to battery aging, temperature fluctuation and other application scenarios.

While the invention has been described in terms of preferred embodiments, it is not intended to be limiting. Those skilled in the art will appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the present invention. Accordingly, the scope of the invention is defined by the appended claims.

Claims (7)

1. The eFuse fuse unit circuit integrated with the dynamic current compensation module is characterized by comprising a digital control module, a bias circuit and a fuse unit output module, wherein the bias circuit and the fuse unit output module are respectively connected with the digital control module, the bias circuit is connected with the fuse unit output module, the eFuse fuse unit circuit also comprises voltage dividing resistors R1, R3 and R4 and a fuse programming module, the voltage dividing resistors R1, R3 and R4 are connected with the bias circuit, and the fuse programming module is connected with the fuse unit output module;

The bias circuit structure provides stable bias current, the digital control module is used for controlling the bias circuit to generate bias current,

When a low-level control signal is input to the EN1 end, an NMOS tube N13 of the fuse programming module is opened, a resistor R0 of the fuse programming module starts fuse programming through high current, a silicide layer on the resistor R0 is blown after programming is finished, so that the resistor R0 is converted into a high-resistance state from low resistance, the resistance value of the resistor R0 is larger than that of the voltage dividing resistors R1, R3 and R4, programming is finished, the output Y is turned over from 1 to 0 at the moment,

The fuse unit output module outputs an output signal of the entire fuse unit circuit to other circuit control.

2. The eFuse fuse unit circuit integrated with the dynamic current compensation module of claim 1, wherein the digital control module comprises a PMOS tube P1, a PMOS tube P2, an NMOS tube N1, an NMOS tube N2, wherein the grid electrode of the NMOS tube N1 is connected with the grid electrode of the PMOS tube P1, the grid electrode of the NMOS tube N2 and the EN end, and receives a bias circuit switch digital signal;

The PMOS tube P1 and the NMOS tube N2 form an inverter, the inverter is output to the grid electrode of the PMOS tube P2 and is connected with a power supply, namely the PMOS tube P2 is used as a pull-up tube of the bias circuit.

3. The eFuse fuse cell circuit integrated with dynamic current compensation module of claim 2 wherein the bias circuit comprises PMOS transistors P3, P4, P5, P6, NMOS transistors N3, N4, N5, N6, N7, N8, N9, the gate of PMOS transistor P3 is connected with the gate of PMOS transistor P2 in parallel,

The source electrode of the PMOS tube P3 is connected with the drain electrode of the PMOS tube P5, the grid electrode of the PMOS tube P3, the grid electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P4, and is connected with the drain electrode of the PMOS tube P2 of the digital control module;

The source electrode of the PMOS tube P5 is connected with the source electrode of the NMOS tube N3, and the source electrode of the PMOS tube P4 is connected with the drain electrode of the NMOS tube N5, the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N6;

The source electrode of the PMOS tube P6 is connected with the drain electrode of the NMOS tube N6 and the grid electrode of the NMOS tube N8, the source electrode of the NMOS tube N6 is connected with the drain electrode of the NMOS tube N8 and is connected with the fuse unit output module, the source electrode of the NMOS tube N8 is grounded, the grid electrode of the PMOS tube P6 is connected with the grid electrode of the PMOS tube P3;

The source electrode of the NMOS tube N7 is connected with the drain electrode of the NMOS tube N9, the grid electrode of the NMOS tube N7 is connected with the grid electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N6, and is connected with the fuse unit output module;

The MINUS ends of the resistors R1, R3 and R4 are respectively connected with the drain electrode of the PMOS tube P3, the drain electrode of the PMOS tube P6 and the drain electrode of the PMOS tube P4.

4. The eFuse fuse cell circuit integrated with dynamic current compensation module of claim 3 wherein the fuse programming module comprises PMOS tube P8, NMOS tube N10, NMOS tube N11, NMOS tube N12, NMOS tube N13;

The grid electrode of the PMOS tube P8 is connected with the grid electrode of the NMOS tube N10, the EN1 end is connected with a fuse programming digital signal, the source electrode of the PMOS tube P8 is grounded, and the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N10, the drain electrode of the NMOS tube N11 and the grid electrode of the NMOS tube N13;

The grid electrode of the NMOS tube N11 is connected with a grid electrode of the NMOS tube N12 to form a power supply, the source electrode of the NMOS tube N11 is connected with the drain electrode of the NMOS tube N12, and the source electrodes of the NMOS tube N12 and the NMOS tube N13 are grounded;

The drain electrode of the NMOS tube N13 is connected with one end of a resistor R0, and the other end of the resistor R0 is connected with the fuse unit output module.

5. The eFuse fuse unit circuit of the integrated dynamic current compensation module of claim 4 in which the fuse unit output module comprises a resistor R2, a PMOS tube P9, a PMOS tube P10, a PMOS tube P11, a PMOS tube P12, a PMOS tube P13, an NMOS tube N14, an NMOS tube N15, an NMOS tube N16, an NMOS tube N17, an NMOS tube N18;

the source electrode of the PMOS tube P9 is connected with a power supply, the grid electrode of the PMOS tube P9 is connected with the MINUS end of the resistor R2, the PLUS end of the resistor R2 is grounded, and the drain electrode of the PMOS tube P9 is connected with the other end of the resistor R0;

The grid electrode of the PMOS tube P10 is connected with the grid electrode of the PMOS tube P3, the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P6 of the bias circuit, and the drain electrode of the PMOS tube P10 is connected with one end of a resistor R0 and the drain electrode of the NMOS tube N13, and the source electrode of the PMOS tube P10 is connected with the drain electrode of the NMOS tube N14, the grid electrode of the PMOS tube P11, the grid electrode of the NMOS tube N16, the drain electrode of the PMOS tube P13 and the drain electrode of the NMOS tube N17;

The grid electrode of the NMOS tube N14 is used as a first connecting end of the fuse unit output module and the paranoid circuit, is connected with the grid electrode of the NMOS tube N7, the source electrode of the NMOS tube N14 is connected with the drain electrode of the NMOS tube N15,

The grid electrode of the NMOS tube N15 is used as a second connecting end of the fuse unit output module and the paranoid circuit, is connected with the source electrode of the PMOS tube P6, and the source electrode of the NMOS tube N15 is grounded;

the source electrode of the PMOS tube P11 is connected with a power supply, and the drain electrode of the PMOS tube P11 is connected with the drain electrode of the NMOS tube N16, the grid electrode of the PMOS tube P12 and the grid electrode of the NMOS tube N18;

The source electrode of the PMOS tube P12 is connected with a power supply, the drain electrode of the PMOS tube P12 is connected with the source electrode of the PMOS tube P13, the source electrode of the NMOS tube N17 is connected with the drain electrode of the NMOS tube N18, and the source electrode of the NMOS tube N18 is grounded;

the gate of the PMOS transistor P13 is connected to the FDLP clock signal, and the gate of the NMOS transistor N17 is connected to FDLN (clock signal).

6. The eFuse fuse cell circuit of the integrated dynamic current compensation module of claim 1 in which,

The resistances of the resistors R1, R3 and R4 are 5 Kohm.

7. The eFuse fuse cell circuit of the integrated dynamic current compensation module of claim 1 in which,

Resistor R0 is a poly resistor.