CN122002995A - Micro light emitting diode array, manufacturing method thereof, display device and electronic equipment - Google Patents

Abstract

The application discloses a micro light emitting diode array, a preparation method thereof, a display device and electronic equipment, and belongs to the technical field of display. The substrate of the micro light emitting diode array comprises at least two element areas, wherein a micro light emitting diode and at least one electrode unit are formed in each element area, and the electrode units and the micro light emitting diodes are manufactured by the same process. The micro light emitting diode comprises a first doped semiconductor layer, an active layer, a second doped semiconductor layer and a first electrode, wherein the electrode unit is electrically connected with the first doped semiconductor layer in the micro light emitting diode, so that independent control of the micro light emitting diode is realized. In the micro light emitting diode array, the first electrode and the electrode unit of each micro light emitting diode form a group of electrodes, each group of electrodes can be controlled independently, and the electrode units manufactured by the same process are equal to the micro light emitting diodes in height, so that the subsequent electric connection with a driving circuit is facilitated.

Description

Micro light emitting diode array, manufacturing method thereof, display device and electronic equipment

Technical Field

The application belongs to the technical field of display, and particularly relates to a micro light emitting diode array, a preparation method thereof, a display device and electronic equipment.

Background

The micro light emitting diode array is considered as an optimal augmented reality (Augmented Reality, AR) display lighting scheme in the industry because of the performance advantages of high brightness, low energy consumption, rapid reaction time, high contrast, high resolution, color saturation and the like, and the micro light emitting diode array at present usually adopts a common N electrode form by a plurality of micro light emitting diode elements or needs to realize independent connection of the N electrode and the CMOS driving circuit by means of complicated processes such as secondary bonding of a temporary substrate, removal of an epitaxial growth substrate and the like. Under the connection mode of the common N electrode and the CMOS driving circuit, the N-type current mirror is not allowed, or the driving circuit based on the N-type MOS tube is adopted in the design of the CMOS driving circuit. In addition, as all pixel point units in the Micro-LED array adopt a common N electrode, single pixel points can be independently controlled only through the voltage of a P electrode end, and a certain limitation is caused on a cross-voltage range.

Disclosure of Invention

The application provides a micro light emitting diode array, a preparation method thereof, a display device and electronic equipment, and aims to realize that electrodes at two ends of each micro light emitting diode element in the micro light emitting diode array can be independently controlled.

In a first aspect, the present application provides a micro light emitting diode array, including a substrate, where the substrate includes at least two element regions, and a micro light emitting diode and at least one electrode unit are formed in each element region, where the electrode unit and the micro light emitting diode are manufactured by the same process. The micro light emitting diode comprises a first doped semiconductor layer, an active layer, a second doped semiconductor layer and a first electrode, wherein the electrode unit is electrically connected with the first doped semiconductor layer in the micro light emitting diode, so that independent control of the micro light emitting diode is realized.

In some embodiments, the electrode unit includes an auxiliary active layer, an auxiliary second doped semiconductor layer, and a second electrode sequentially formed over the first doped semiconductor layer, an auxiliary metal layer is further included in each element region, a first end of the auxiliary metal layer is electrically connected to the second electrode, and a second end of the auxiliary metal layer is electrically connected to the first doped semiconductor layer.

In some embodiments, the second electrode is formed in the same process step as the first electrode, the second electrode being equal in height and equal in thickness to the first electrode.

In some embodiments, the micro light emitting diode further comprises a conductive layer located between the second doped semiconductor layer and the first electrode. The electrode unit further includes an auxiliary conductive layer between the auxiliary second doped semiconductor layer and the second electrode. The first end of the auxiliary metal layer covers part of the auxiliary conductive layer and is electrically connected with the second electrode through the auxiliary conductive layer. Wherein the conductive layer and the auxiliary conductive layer are formed in the same process step.

In some embodiments, the conductive layer and the auxiliary conductive layer are both indium tin oxide layers.

In some embodiments, a spacer is disposed between the first doped semiconductor layers of adjacent element regions, the spacer being at least one of a trench region, an ion implantation region, and a passivation layer.

In the embodiment of the application, in each element area, the first electrode and the electrode unit of each micro light emitting diode are respectively used as two ends of a group of electrodes of the micro light emitting diode, and each group of electrodes can be respectively and independently controlled, so that the micro light emitting diode in each element area can be independently controlled, the application scene of the micro light emitting diode array is expanded, the cross-voltage range of a single micro light emitting diode element is expanded, and the display brightness is favorably improved. The electrode unit and the micro light emitting diode are manufactured by adopting the same process, so that the electrode unit and the micro light emitting diode have the same height, namely, the height of the upper surface of the first electrode of the micro light emitting diode relative to the substrate is equal to the height of the upper surface of the electrode unit relative to the substrate, and the subsequent connection with a driving circuit is facilitated.

On the other hand, the embodiment of the application also provides a preparation method of the micro light emitting diode array, which comprises the following steps S10-S20:

Step S10, providing a substrate, wherein the substrate comprises at least two element areas.

Step S20, forming a micro light emitting diode and at least one electrode unit in each element area.

The method for forming the micro light emitting diode comprises the steps of sequentially forming a first doped semiconductor layer, an active layer, a second doped semiconductor layer and a first electrode on a substrate.

The at least one electrode unit is synchronously formed in the step of forming the micro light emitting diode, and the electrode unit is electrically connected with the first doped semiconductor layer in the micro light emitting diode to realize independent control of the micro light emitting diode.

In some embodiments, the electrode unit includes an auxiliary active layer, an auxiliary second doped semiconductor layer, and a second electrode sequentially formed over the first doped semiconductor layer.

The step of forming the at least one electrode unit in synchronization with the step of forming the micro light emitting diode includes the following steps S21 to S24:

And S21, sequentially forming a first doped semiconductor layer, a basic active layer and a basic second doped semiconductor layer on the substrate.

And S22, removing part of the basic second doped semiconductor layer to form a separated second doped semiconductor layer and an auxiliary second doped semiconductor layer, wherein the thicknesses of the second doped semiconductor layer and the auxiliary second doped semiconductor layer are equal.

And S23, removing part of the basic active layer to form a separated active layer and an auxiliary active layer, and exposing part of the first doped semiconductor layer.

And step S24, forming a first electrode and a second electrode in the same process, wherein the first electrode is positioned on the second doped semiconductor layer, the second electrode is positioned on the auxiliary second doped semiconductor layer, and the thicknesses of the first electrode and the second electrode are equal.

In some embodiments, the above-described method of preparing further comprises forming an auxiliary metal layer, a first end of the auxiliary metal layer being electrically connected to the second electrode, and a second end of the auxiliary metal layer being electrically connected to the first doped semiconductor layer.

In some embodiments, the step of forming the micro light emitting diode by simultaneously forming the at least one electrode unit before removing a portion of the underlying second doped semiconductor layer further includes the following steps S211-S212:

and S211, forming a basic conductive layer on the basic second doped semiconductor layer.

And S212, removing part of the basic conductive layer to form a separated conductive layer and an auxiliary conductive layer, wherein the thicknesses of the conductive layer and the auxiliary conductive layer are the same. The formed conductive layer is positioned above the second doped semiconductor layer, the auxiliary conductive layer is positioned above the auxiliary second doped semiconductor layer, the first electrode is positioned above the conductive layer, and the second electrode is positioned above the auxiliary conductive layer.

Or in some embodiments, after forming the separated second doped semiconductor layer and the auxiliary second doped semiconductor layer, forming a conductive layer and an auxiliary conductive layer by using the same photolithography process, wherein the conductive layer is located above the second doped semiconductor layer, and the auxiliary conductive layer is located above the auxiliary second doped semiconductor layer. The first electrode is located above the conductive layer, and the second electrode is located above the auxiliary conductive layer.

In some embodiments, forming the auxiliary metal layer includes forming a first end cap portion of the auxiliary metal layer to cover the auxiliary conductive layer, and forming the second electrode includes forming a second electrode to electrically connect with the auxiliary metal layer through the auxiliary conductive layer.

In some embodiments, a spacer is formed between the first doped semiconductor layers of adjacent element regions, the spacer being at least one of a trench region, an ion implantation region, and a passivation layer.

In some embodiments, the spacer is formed after the first electrode and the second electrode are formed. Or after forming the auxiliary metal layer and before forming the first electrode and the second electrode, forming a spacer. Or forming a spacer before forming the auxiliary metal layer.

In the preparation method provided by the embodiment of the application, at least one electrode unit in each element area is synchronously formed in the step of forming the micro light emitting diode, the process is simpler, and the electrode units and the micro light emitting diode can have the same height, so that the subsequent connection with a driving circuit is facilitated. In addition, in each element area, the electrode unit is electrically connected with the first doped semiconductor layer in the micro light emitting diode, so that independent control of the micro light emitting diode is realized, the application scene of the micro light emitting diode array is expanded, the cross-voltage range of a single micro light emitting diode element is expanded, and the display brightness is improved.

In still another aspect, the present application further provides a display device, including the micro light emitting diode array mentioned in any one of the embodiments of the first aspect, and a micro lens, where the micro lens at least covers the micro light emitting diode, and the micro lens is used to adjust the converging light emitting direction, so that the display device displays related content. The display device has the same technical effects as the micro light emitting diode array, and the description thereof is omitted herein.

In still another aspect, the present application further provides an electronic device, including the display apparatus described above. The electronic device has the same technical effects as the display device, and will not be described herein.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a micro light emitting diode array according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another micro LED array according to an embodiment of the present application;

FIG. 3 is a flowchart of a method for manufacturing a micro light emitting diode array according to an embodiment of the present application;

Fig. 4 to 14 are step diagrams of a preparation method of a micro light emitting diode array according to an embodiment of the present application;

FIG. 15 is a schematic plan view of a micro light emitting diode array pixel according to an embodiment of the present application;

FIG. 16 is a schematic plan view of a micro LED array according to an embodiment of the present application;

FIG. 17 is a schematic plan view of a micro LED array according to another embodiment of the present application;

FIGS. 18-22 are step diagrams of a method for forming spacers according to an embodiment of the present application;

FIG. 23 is a schematic diagram of a display device according to an embodiment of the present application;

fig. 24 is a schematic diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

In the description of the present application, "plurality" means two or more.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In describing some embodiments, the expression "connected" and its derivatives may be used. The term "coupled" is used in a broad sense, and may be either permanently coupled, detachably coupled, or integrally formed, or indirectly coupled via an intervening medium, for example. The term "electrically connected" for example means that two or more elements are in direct physical or electrical contact, and may also mean that two or more elements are not in direct contact with each other but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are idealized exemplary figures. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Examples of the embodiments are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements throughout or elements having like or similar functionality. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.

Currently, micro light emitting diode arrays generally employ a plurality of Micro LIGHT EMITTING Diodes (Micro-LEDs) in the form of a common N-electrode. For example, according to the existing epitaxial growth technique, the P-type semiconductor layer constituting the Micro-LED element is grown later than the N-type semiconductor layer so as to be on the surface layer of the epitaxial wafer. Therefore, attaching the P-type Semiconductor layer surface of the Micro-LED to the surface of the driver chip, which may be a Complementary Metal Oxide Semiconductor (CMOS) driver chip, is a common bonding method.

This is because, if the surface of the N-type semiconductor layer of the Micro-LED is attached to the surface of the CMOS driving chip, the surface of the P-type semiconductor layer of the Micro-LED needs to be attached to the temporary substrate by adding a temporary bonding method, the epitaxial growth substrate is removed to expose the surface of the N-type semiconductor layer of the Micro-LED, and then the surface of the N-type semiconductor layer of the Micro-LED is attached to the surface of the CMOS driving chip by bonding for the second time, so that the process is relatively complex and cumbersome and less adopted.

The surface of the P-type semiconductor layer of the Micro-LED is attached to the surface of the CMOS driving chip through one-time bonding, and P electrodes respectively arranged on the P-type semiconductor layer of the Micro-LED are connected with a CMOS driving circuit below the P-type semiconductor layer, so that independent control of a single Micro-LED is a common mode. In this manner, a common N electrode is formed on the N-type semiconductor layer on the side away from the bonding interface by utilizing the current spreading capability of the N-type semiconductor layer itself or by adding a conductive layer to the surface of the N-type semiconductor layer, and is connected to the underlying CMOS driving circuit.

In the above connection mode of the common N electrode and the CMOS driving circuit, the heights of the P electrode and the N electrode on the substrate are different, the process is complex in the connection process with the driving circuit, and the common N electrode will not allow the N-type current mirror or the driving circuit based on the N-type MOS transistor or the pixel circuit sharing the low voltage (ELVDD) to be applied in the CMOS driving circuit design. In addition, because all pixel points in the Micro-LED array (namely all Micro-LEDs) adopt a common N electrode, single pixel points can be independently controlled only by adjusting the voltage on the P electrode side, and limitation is generated in a cross-voltage range.

In view of the foregoing, the present application provides a micro light emitting diode array, as shown in fig. 1, and fig. 1 is a schematic structural diagram of a micro light emitting diode array according to an embodiment of the present application.

The micro light emitting diode array 100 includes a substrate 10, and the substrate 10 includes at least two element regions, for example, a region a corresponds to one element region and a region B corresponds to another element region in fig. 1. A micro light emitting diode M1 and at least one electrode unit M2 are formed in each element area, and the electrode unit M2 and the micro light emitting diode M1 are manufactured by the same process. The micro light emitting diode M1 includes a first doped semiconductor layer 11 formed on the substrate 10, an active layer 13 and a second doped semiconductor layer 14 formed over the first doped semiconductor layer 11, and a first electrode 15, and the electrode unit M2 is electrically connected to the first doped semiconductor layer 11 in the micro light emitting diode M1, to achieve independent control of the micro light emitting diode M1.

In the embodiment of the present application, the first doped semiconductor layer 11, the active layer 13 and the second doped semiconductor layer 14 form a PN junction structure of the micro light emitting diode, the first electrode 15 and the electrode unit M2 of each micro light emitting diode M1 are respectively used as two ends of a group of electrodes, the first electrode 15 is electrically connected to the second doped semiconductor layer 14, and the electrode unit M2 is electrically connected to the first doped semiconductor layer 11, thereby forming a micro light emitting diode element in each element region as shown in fig. 1. The electrode unit M2 and the micro light emitting diode M1 are manufactured by the same process, so that the electrode unit M2 and the micro light emitting diode M1 have the same height, that is, the height of the upper surface of the first electrode 15 of the micro light emitting diode M1 relative to the substrate 10 is equal to the height of the upper surface of the electrode unit M2 relative to the substrate 10, which is beneficial for subsequent connection with a driving circuit.

Fig. 1 illustrates a case where only one electrode unit M2 is disposed in each micro led element, and exemplary cases where a plurality of electrode units M2 are disposed in each micro led element, where the plurality of electrode units M2 and the micro led M1 are all manufactured by the same process and disposed at the same height, which is not described herein. When a plurality of electrode units M2 are employed in a group of electrodes of one micro light emitting diode element, more driving functions of the CMOS pixel circuit are facilitated.

In the micro light emitting diode array, the micro light emitting diode in each element area is a light emitting pixel. The area corresponding to the micro light emitting diode M1 is an actual light emitting area of each light emitting pixel point, the electrode unit M2 may be set according to a gap position between the pixel points, which is only schematic in the figure, and the actual size and shape may be adjusted according to application requirements.

For each micro light emitting diode element in the micro light emitting diode array, each group of electrodes can be controlled independently, that is, a mode that a plurality of micro light emitting diodes adopt a certain common electrode is not adopted any more, the first electrode 15 and the electrode unit M2 of each micro light emitting diode element can be controlled independently, the application scene of the micro light emitting diode array is expanded, the cross-voltage range of a single micro light emitting diode element is expanded, and the display brightness is improved.

Illustratively, the first doped semiconductor layer 11 may be an N-type semiconductor layer, such as N-type gallium nitride, and the corresponding second doped semiconductor layer 14 is a P-type semiconductor layer, such as P-type gallium nitride. At this time, the electrode unit M2 is an N electrode, and the first electrode 15 is a P electrode. Alternatively, the first doped semiconductor layer 11 may be a P-type semiconductor layer and the second doped semiconductor layer 14 may be an N-type semiconductor layer.

In the above embodiment, the first electrode 15 and the electrode unit M2 of each micro led element in the array can be controlled independently. For example, when the electrode unit M2 is an N electrode and the first electrode 15 is a P electrode, the N electrode of each micro light emitting diode element can be independently controlled by the CMOS driving circuit, so that the pixel circuit of the N-type current mirror is allowed to be adopted, and the driving circuit based on the N-type MOS transistor or the pixel circuit sharing ELVDD is also allowed to be applied in the CMOS driving circuit design, thereby expanding the application scenario of the micro light emitting diode array 100.

In addition, since the first electrode 15 and the electrode unit M2 of each micro light emitting diode element can be controlled respectively, the voltage of each micro light emitting diode element is allowed to be turned off and reset rapidly, and by adjusting the voltage signals on the electrodes at the two ends, a larger dynamic voltage-crossing range can be realized, which is beneficial to improving the display effect.

In some embodiments, as shown in fig. 2, fig. 2 is a schematic view of another micro light emitting diode array structure provided in the embodiment of the present application, the electrode unit M2 includes an auxiliary active layer 131, an auxiliary second doped semiconductor layer 141 and a second electrode 16 sequentially formed above the first doped semiconductor layer 11, each element region further includes an auxiliary metal layer 18, a first end of the auxiliary metal layer 18 is electrically connected to the second electrode 16, and a second end of the auxiliary metal layer 18 is electrically connected to the first doped semiconductor layer 11.

In the embodiment of the present application, the electrode unit M2 has a similar stacked structure to the micro light emitting diode M1, and the auxiliary metal layer 18 realizes the electrical connection of the second electrode 16 with the first doped semiconductor layer 11 based on the stacked structure of the electrode unit M2. In the case where a voltage is applied between the first electrode 15 and the second electrode 16 and is conducted, the resistance of the auxiliary metal layer 18 is smaller, and a current between the second electrode 16 and the first doped semiconductor layer 11 is conducted through the auxiliary metal layer 18 without passing through a stacked structure of the second electrode 16, which is formed by the "auxiliary second doped semiconductor layer 141, the auxiliary active layer 131, and the first doped semiconductor layer 11", for ensuring that the height of the second electrode 16 with respect to the substrate 10 is equal to the height of the first electrode 15 with respect to the substrate 10, facilitating subsequent connection with a driving circuit.

In some of the embodiments, based on the above-mentioned stacked structure of the electrode unit M2, the second electrode 16 and the first electrode 15 are formed in the same process step, and the second electrode 16 and the first electrode 15 are equal in height and thickness, which facilitates subsequent connection with the driving circuit.

In some embodiments, as shown in fig. 2, in each micro light emitting diode element of the micro light emitting diode array 100, the micro light emitting diode M1 further includes a conductive layer 17, and the conductive layer 17 is located between the second doped semiconductor layer 14 and the first electrode 15. The electrode unit M2 further includes an auxiliary conductive layer 171, the auxiliary conductive layer 171 being located between the auxiliary second doped semiconductor layer 141 and the second electrode 16. The first end of the auxiliary metal layer 18 covers a portion of the auxiliary conductive layer 171 and is electrically connected to the second electrode 16 through the auxiliary conductive layer 171. Wherein the conductive layer 17 and the auxiliary conductive layer 171 are formed in the same process step.

In some embodiments, the conductive layer 17 and the auxiliary conductive layer 171 are both Indium Tin Oxide (ITO), where the ITO has a high visible light transmittance and a low resistivity, and after being treated by an annealing process, the conductive layer 17 may form an ohmic contact with the second doped semiconductor layer 14, so as to ensure the luminous transmittance and the conductivity of the micro light emitting diode.

Meanwhile, the auxiliary conductive layer 171 is utilized to realize the electric connection between the auxiliary metal layer 18 and the second electrode 16, so as to realize the electric connection between the second electrode 16 and the first doped semiconductor layer 11, which is beneficial to improving the connection reliability between the metal electrode and the semiconductor device, and the conductive layer 17 and the auxiliary conductive layer 171 are combined with the characteristic that the conductive layer 17 and the auxiliary conductive layer 171 are formed in the same process step, so that the conductive layer 17 and the auxiliary conductive layer 171 have the same height, and good conditions are provided for realizing the equal height setting of the first electrode 15 and the second electrode 16.

In some embodiments, as shown in fig. 1 to 2, a spacer 12 is disposed between the first doped semiconductor layers 11 of adjacent element regions, and the spacer 12 is at least one of a trench region, an ion implantation region, and a passivation layer.

In the embodiment of the present application, the first doped semiconductor layer 11 of different element regions is separated by the spacer 12, so that the division of a plurality of element regions is clarified. Since the electrode unit M2 of each micro light emitting diode is electrically connected to the first doped semiconductor layer 11, the spacer 12 is used to realize electrical isolation between the first doped semiconductor layers 11 of different element regions, so that electrical connection between the electrode units M2 of different micro light emitting diodes is avoided, that is, electrical isolation between the electrode units M2 of different element regions in the array is realized, and no common electrode is used, so that the electrode units M2 (or the second electrodes 16) of different micro light emitting diodes can be controlled independently.

Illustratively, the spacer region 12 may be a trench region, with electrical isolation of the first doped semiconductor layer 11 of the different micro light emitting diodes being achieved by physical isolation. Alternatively, the spacer 12 may be an ion implantation region or a passivation layer to achieve electrical isolation by blocking the conductive properties inside the first doped semiconductor layer 11. The depth of the spacer 12 depends on the conductivity properties of the first doped semiconductor layer 11 at different depths and the process of forming the spacer 12, and electrical isolation can be achieved within a desired depth range as desired, so that the depth of the spacer 12 can be smaller than the thickness of the first doped semiconductor layer 11, or the depth of the spacer 12 can be equal to the thickness of the first doped semiconductor layer 11, or the depth of the spacer 12 can be greater than the thickness of the first doped semiconductor layer 11, e.g. trench etching into the substrate.

On the other hand, the embodiment of the application also provides a preparation method of the micro light emitting diode array, as shown in fig. 3, fig. 3 is a flowchart of the preparation method of the micro light emitting diode array provided by the embodiment of the application, and fig. 4 to 14 are step diagrams of the preparation method of the micro light emitting diode array provided by the embodiment of the application.

The preparation method comprises the following steps S10-S20:

Step S10 as shown in fig. 4, a substrate 10 is provided. The substrate 10 includes at least two element regions thereon. Wherein the substrate 10 may be a sapphire substrate.

In step S20, as shown in FIG. 5-FIG. 14, a micro light emitting diode M1 and at least one electrode unit M2 are formed in each device region.

The step of forming a micro light emitting diode M1 includes sequentially forming a first doped semiconductor layer 11, an active layer 13, a second doped semiconductor layer 14, and a first electrode 15 on a substrate 10.

The at least one electrode unit M2 is formed synchronously in the step of forming the micro light emitting diode M1, and the electrode unit M2 is electrically connected to the first doped semiconductor layer 11 in the micro light emitting diode M1, so as to realize independent control of the micro light emitting diode M1.

Illustratively, in some embodiments, the electrode unit M2 includes an auxiliary active layer 131, an auxiliary second doped semiconductor layer 141, and a second electrode 16 sequentially formed over the first doped semiconductor layer 11.

The above-mentioned "at least one electrode unit M2 is formed simultaneously in the step of forming the micro light emitting diode M1" includes the following steps S21 to S24:

In step S21, as shown in FIGS. 5 to 6, a first doped semiconductor layer 11, a base active layer 130 and a base second doped semiconductor layer 140 are sequentially formed on a substrate 10.

The first doped semiconductor layer 11 is illustratively N-type gallium nitride. The basic active layer 130 is a multiple quantum well (Multiple Quantum Well, MQW), and the MQW multiple quantum well structure has the advantage that the light-emitting wavelength can be regulated and controlled by adjusting the thickness and the material composition of the quantum well, so that micro light-emitting diodes with different colors can be formed. When the first doped semiconductor layer 11 is N-type gallium nitride, the base second doped semiconductor layer 140 is P-type gallium nitride, thereby forming a light emitting diode structure.

In some embodiments, as shown in fig. 5, after the first doped semiconductor layer 11 is formed, a spacer 12 is formed between the first doped semiconductor layers 11 of adjacent element regions, and the spacer 12 is used to divide different element regions. The formation of the spacer 12 may include various forms, and the step of forming the spacer 12 is not limited to being formed immediately after the formation of the first doped semiconductor layer 11 as shown in fig. 5. For example, in some embodiments, the spacer 12 is at least one of a trench region, an ion implantation region, and a passivation layer, the formation stages of which may be appropriately arranged during a related process of a subsequent process (e.g., etching, depositing a passivation layer, etc.) to finally form the spacer 12.

In some embodiments, after forming the basic second doped semiconductor layer 140, the method further includes the following steps S211 to S212:

in step S211, as shown in fig. 7, a base conductive layer 170 is formed on the base second doped semiconductor layer 140.

Illustratively, the base conductive layer 170 is an Indium Tin Oxide (ITO) semiconductor transparent conductive film, which has high visible light transmittance and low resistivity, and is beneficial to improving the connection reliability of the metal electrode and the semiconductor device while ensuring the luminous transmittance and the conductive performance of the micro light emitting diode. After the base conductive layer 170 is formed, an annealing process is performed to form an ohmic contact.

In step S212, as shown in fig. 8, a part of the base conductive layer 170 is removed to form a separated conductive layer 17 and an auxiliary conductive layer 171, and the conductive layer 17 and the auxiliary conductive layer 171 have the same thickness.

In step S22, as shown in fig. 8, a part of the basic second doped semiconductor layer 140 is removed to form a separated second doped semiconductor layer 14 and an auxiliary second doped semiconductor layer 141, and the thicknesses of the second doped semiconductor layer 14 and the auxiliary second doped semiconductor layer 141 are equal.

In step S23, as shown in fig. 8, a portion of the base active layer 130 is removed to form a separated active layer 13 and auxiliary active layer 131, and a portion of the first doped semiconductor layer 11 is exposed. The active layer 13 and the auxiliary active layer 131 have the same thickness.

In the steps S211 to S23, a MESA (MESA) pattern is designed according to a patterned mask, for example, the ITO transparent conductive film of the indium tin oxide semiconductor of the partial basic conductive layer 170, the P-type gan of the partial basic second doped semiconductor layer 140, and the MQW multiple quantum well of the partial basic active layer 130 are removed by etching, so that after the etching is completed, the N-type gan of the first doped semiconductor layer 11 is exposed and a relatively flat contact surface is formed. Finally, a functionalized step structure, namely, a MESA is formed, which corresponds to the first stack structure 150 of the micro light emitting diode M1 and the second stack structure 160 of the electrode unit M2, respectively.

The first stacked electrode structure 150 includes an active layer 13, a second doped semiconductor layer 14, and a conductive layer 17. The second stack structure 160 includes an auxiliary active layer 131, an auxiliary second doped semiconductor layer 141, and an auxiliary conductive layer 171.

The first stacked electrode structure 150 and the second stacked structure 160 formed by the steps have symmetry, and the preparation processes of the film structures are the same and the thicknesses are equal, so that the first stacked electrode structure 150 and the second stacked structure 160 have the same height, which provides good conditions for forming the first electrode 15 and the second electrode 16 with the same height subsequently.

Thereafter, as shown in fig. 9, a mask 01 is formed. Illustratively, the mask 01 is a photoresist, and the patterned mask 01 is formed by photolithography in a conventional semiconductor process, the mask 01 completely covers the MESA of the first stacked electrode structure 150, and the mask 01 covers a portion of the MESA of the second stacked structure 160, exposing the first doped semiconductor layer 11 of the intermediate region of the MESA of the first stacked electrode structure 150 and the MESA of the second stacked structure 160, and exposing a portion of the sidewall of the MESA of the second stacked structure 160.

In step S24, as shown in FIG. 10-FIG. 14, the first electrode 15 and the second electrode 16 are formed in the same process, the first electrode 15 is located on the conductive layer 17, the second electrode 16 is located on the auxiliary conductive layer 171, and the thicknesses of the first electrode 15 and the second electrode 16 are equal.

In some embodiments, the above-described fabrication method further includes forming an auxiliary metal layer 18, a first end of the auxiliary metal layer 18 being electrically connected to the second electrode 16, and a second end of the auxiliary metal layer 18 being electrically connected to the first doped semiconductor layer 11.

Illustratively, in some embodiments, forming the auxiliary metal layer 18 includes forming a first end cap portion of the auxiliary metal layer 18 to cover the auxiliary conductive layer 171. Forming the second electrode 16 includes forming the second electrode 16 to be electrically connected to the auxiliary metal layer 18 through the auxiliary conductive layer 171.

For example, as shown in fig. 10, using the mask 01, an auxiliary metal layer 18 is formed on the exposed portion of the mask 01, a first end of the auxiliary metal layer 18 covers a portion of the auxiliary conductive layer 171, and a second end extends above the first doped semiconductor layer 11 exposed by the mask 01 and is electrically connected to the first doped semiconductor layer 11.

During the formation of the auxiliary metal layer 18, the metal material of the auxiliary metal layer 18 is also deposited on the upper surface of the mask 01. When the mask 01 is stripped, the metal material of the auxiliary metal layer 18 deposited on the mask 01 is also removed, and this part is not shown.

Thereafter, as shown in fig. 11, an annealing process is performed after removing the mask 01, so that the metal material of the auxiliary metal layer 18 located on the surface of the first doped semiconductor layer 11 forms an ohmic contact therewith. In some embodiments, the material of the ohmic contact may be Ti/Al or Ti/Au, or the like.

Next, as shown in fig. 12, a passivation layer 02 is formed.

Illustratively, the material of the passivation layer 02 includes a silicon nitride material, or the passivation layer 02 may also include silicon oxide or silicon oxynitride, or the like. The passivation layer 02 covers the substrate 10, the first doped semiconductor layer 11, the first stack structure 150, the second stack structure 160, and the auxiliary metal layer 18.

Thereafter, as shown in fig. 13, the passivation layer 02 on the MESA of the first stack structure 150 and the passivation layer 02 on the MESA of the second stack structure 160 are patterned, and a portion of the passivation layer 02 is etched away, exposing a portion of the surface of the conductive layer 17 away from the substrate 10, and exposing a portion of the surface of the auxiliary conductive layer 171 away from the substrate 10.

Finally, as shown in fig. 14, similar to the process shown in fig. 8 to 10, after forming a photoresist mask on the passivation layer 02, the first electrode 15 and the second electrode 16 are formed in the same process. For example, a metal material is deposited, and then the photoresist is removed and the metal material deposited on the photoresist is removed simultaneously, thereby forming a first electrode 15 on the conductive layer 17 and a second electrode 16 on the auxiliary conductive layer 171, the second electrode 16 being electrically connected to the first end of the auxiliary metal layer 18 through the auxiliary conductive layer 171, thereby electrically connecting the second electrode 16 to the first doped semiconductor layer 11.

Illustratively, the metallic material of the first electrode 15 and the metallic material of the second electrode 16 are both gold.

To this end, the micro light emitting diode M1 and the electrode unit M2 are formed in the same process.

In some embodiments, the aforementioned process of forming the first and second stacked structures 150 and 160 may also take a similar manner of forming the first and second electrodes 15 and 16. Illustratively, after the basic second doped semiconductor layer 140 is formed in step S21, the operations of steps S211 to S212 are not performed, but after the separated second doped semiconductor layer 14 and the auxiliary second doped semiconductor layer 141 are formed, the conductive layer 17 and the auxiliary conductive layer 171 are formed in the same photolithography process, and the conductive layer 17 and the auxiliary conductive layer 171 have the same thickness, wherein the conductive layer 17 is located above the second doped semiconductor layer 14 and the auxiliary conductive layer 171 is located above the auxiliary second doped semiconductor layer 141.

The above step of forming the first and second stacked structures 150 and 160, and the step of forming the first and second electrodes 15 and 16, make the first and second electrodes 15 and 16 have the identical height. The first electrode 15 and the second electrode 16 are used for being electrically connected with a driving circuit, so that the micro light emitting diode element emits light, and the first electrode 15 and the second electrode 16 are arranged at equal heights, so that subsequent electrical connection with a CMOS driving circuit is facilitated.

On the micro light emitting diode array 100 prepared in the above steps, as shown in fig. 15 to 17, fig. 15 is a schematic plan view of a light emitting pixel point of the micro light emitting diode array provided in the embodiment of the present application, fig. 16 is a schematic plan view of the micro light emitting diode array provided in the embodiment of the present application, and fig. 17 is a schematic plan view of another micro light emitting diode array provided in the embodiment of the present application.

In each micro led device area, the MESA area (or micro led M1) corresponding to the first stack structure 150 is an actual light emitting pixel, and its arrangement on the substrate 10 is shown in fig. 15. In designing the MESA pattern according to the patterned mask, the MESA region (or, the electrode unit M2) corresponding to the second stack structure 160 may be set according to the gap position between the pixel points. As shown in fig. 16, in the case where one second stack structure 160 is provided for each element region (i.e., one electrode unit M2 is provided), fig. 17 shows the case where a plurality of second stack structures 160 are provided for each element region (i.e., a plurality of electrode units M2 are provided).

In some embodiments, as shown in fig. 16 to 17, in the manufacturing process, a spacer 12 is formed between the first doped semiconductor layers 11 of adjacent element regions, and the spacer 12 is at least one of a trench region, an ion implantation region, and a passivation layer. The step of forming the spacers 12 may be varied and the types of spacers 12 formed at different process stages may be different.

As shown in fig. 18 to 22, fig. 18 to 22 are step diagrams of a preparation method for forming a spacer according to an embodiment of the present application.

Illustratively, in some embodiments, as shown in fig. 18, the spacers 12 are formed after the first electrode 15 and the second electrode 16 are formed at step S25, i.e., after the step shown in fig. 14.

For example, the passivation layer 02 and the first doped semiconductor layer 11 are subjected to patterning treatment, and a portion of the passivation layer 02 and a portion of the first doped semiconductor layer 11 are removed by etching to form a trench region, which exposes the substrate 10, thereby forming the spacer 12, that is, the spacer 12 is a trench region. By forming the trench region by etching, the continuity of the first doped semiconductor layer 11 is broken, the first doped semiconductor layers 11 of different element regions are not connected, and electrical isolation is achieved by physical isolation. That is, the current injected from the second electrode 16 can flow only through the first electrode 15 in the same element region, but cannot flow into the first doped semiconductor layer 11 in the adjacent element region. At this time, the depth of the spacer 12 may be equal to the thickness of the first doped semiconductor layer 11, or the trench region may be extended into the substrate 10 such that the depth of the spacer 12 is greater than the thickness of the first doped semiconductor layer 11.

Or, in some embodiments, as shown in fig. 19-20, the spacer 12 is formed after the formation of the auxiliary metal layer 18 and before the formation of the first electrode 15 and the second electrode 16. More specifically, the spacer 12 is formed after the formation of the auxiliary metal layer 18 as shown in fig. 11 and before the formation of the passivation layer 02 as shown in fig. 12.

For example, after the auxiliary metal layer 18 is formed as shown in fig. 11, the first doped semiconductor layer 11 is subjected to patterning treatment as shown in fig. 19, and a part of the first doped semiconductor layer 11 is removed by etching to form a trench V1. Thereafter, as shown in fig. 20, the passivation layer 02 is formed while simultaneously depositing the passivation layer 02 in the trench V1, and finally the spacer 12 is formed. That is, the spacer 12 is a passivation layer.

Still or exemplary, in some embodiments, the spacer 12 is formed prior to forming the auxiliary metal layer 18, as shown in fig. 21 or 22.

For example, as shown in fig. 21, the trench V2 is formed by etching away a portion of the first doped semiconductor layer 11 while designing the MESA pattern in accordance with the patterned mask. A subsequent process flow is then performed according to the steps shown in fig. 9-14, wherein in the process of forming the passivation layer 02 in fig. 12, the passivation layer 02 is deposited in the trench V2, i.e. the spacer 12 comprises a passivation layer.

Or as shown in fig. 22, after the first doped semiconductor layer 11 is formed on the substrate 10, ion implantation is performed on the first doped semiconductor layer 11, so that the ion implantation area is in a high-resistance state, that is, the spacer 12 is an ion implantation area, and electrical isolation between the first doped semiconductor layers is achieved.

In the above method for forming the spacer 12, besides the etching process, physical isolation of the first doped semiconductor layer 11 of different element regions can be achieved by physical cutting, laser ablation and other technical means, so as to achieve electrical isolation. Besides the ion implantation process, the high-resistance region can be formed by local oxidation and other technical means, so that the electrical isolation of the first doped semiconductor layer 11 of different element regions is realized.

In the above technical means, the depth of the formed spacer 12 may be smaller than the thickness of the first doped semiconductor layer 11, as long as the electrical isolation performance of the spacer 12 can be ensured. For example, in the etching process, the first doped semiconductor layer 11 may not be completely removed in the region of the spacer 12, that is, the substrate 10 may not be exposed during the etching of the first doped semiconductor layer 11 in the region. In practical applications, the depth of the spacer 12 depends on the conductivity of different depths determined by the epitaxial design inside the first doped semiconductor layer 11, and the first doped semiconductor layer 11 can be subjected to related process to achieve electrical isolation within a desired depth range.

In still another aspect, the present application further provides a display device, as shown in fig. 23, and fig. 23 is a schematic diagram of a display device according to an embodiment of the present application.

The display device 200 includes the micro light emitting diode array 100 according to any of the embodiments of the first aspect, and the micro lenses 201. Since the area corresponding to the micro light emitting diode M1, that is, the MESA area of the first stacked structure 150 corresponding to the above-mentioned preparation method, is the actual light emitting area of each light emitting pixel, the micro lens 201 at least covers the area corresponding to the micro light emitting diode M1, that is, the area corresponding to the electrode unit M2 does not need to be separately provided with the micro lens 201. It is also possible to cover the area of the electrode unit M2 if the size of the microlens 201 is large enough.

The micro lens 201 is used for adjusting the converging light emitting direction, so that the display device 200 realizes a display function and displays related pictures. Since the micro light emitting diodes in each element area of the micro light emitting diode array 100 can be independently controlled, the application scenario of the micro light emitting diode array is expanded, the cross-voltage range of a single micro light emitting diode element is expanded, the selectable range of the driving circuit in the display device 200 is expanded, and the display brightness of the display device 200 is improved. In addition, the electrode units and the micro light emitting diodes in the micro light emitting diode array 100 are manufactured by the same process, so that the electrode units and the micro light emitting diodes have the same height, the connection between the micro light emitting diode array 100 and the driving circuit is simpler, and the manufacturing process of the display device 200 is simpler based on the connection

In still another aspect, the present application further provides an electronic device, as shown in fig. 24, and fig. 24 is a schematic diagram of an electronic device according to an embodiment of the present application.

The electronic device 300 includes the display apparatus 200, and the electronic device 300 includes, but is not limited to, an AR near-to-eye display apparatus, etc., and the electronic device 300 has the same technical effects as the display apparatus 200, and will not be described herein.

The foregoing is merely illustrative of the embodiments of the present application, and the present application is not limited thereto, and any person skilled in the art will recognize that changes and substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (16)

1. A micro light emitting diode array comprising:

A substrate including at least two element regions thereon;

Forming a micro light emitting diode and at least one electrode unit in each element region;

The electrode unit and the micro light emitting diode are manufactured by adopting the same process;

The micro light emitting diode comprises a first doped semiconductor layer, an active layer, a second doped semiconductor layer and a first electrode;

the electrode unit is electrically connected with the first doped semiconductor layer in the micro light emitting diode to realize independent control of the micro light emitting diode.

2. The micro light emitting diode array according to claim 1, wherein the electrode unit includes an auxiliary active layer, an auxiliary second doped semiconductor layer, and a second electrode sequentially formed over the first doped semiconductor layer;

Each element region further comprises an auxiliary metal layer, wherein a first end of the auxiliary metal layer is electrically connected with the second electrode, and a second end of the auxiliary metal layer is electrically connected with the first doped semiconductor layer.

3. The array of micro light emitting diodes of claim 2, wherein the second electrode is formed in the same process step as the first electrode, the second electrode being of equal height and thickness as the first electrode.

4. The array of micro light emitting diodes of claim 3, further comprising a conductive layer between the second doped semiconductor layer and the first electrode;

the electrode unit further comprises an auxiliary conductive layer, wherein the auxiliary conductive layer is positioned between the auxiliary second doped semiconductor layer and the second electrode, and a first end of the auxiliary metal layer covers part of the auxiliary conductive layer and is electrically connected with the second electrode through the auxiliary conductive layer;

the conductive layer and the auxiliary conductive layer are formed in the same process step.

5. The array of micro light emitting diodes of claim 4, wherein the conductive layer and the auxiliary conductive layer are both indium tin oxide layers.

6. The array of claim 1, wherein a spacer is disposed between the first doped semiconductor layers of adjacent ones of the element regions, the spacer being at least one of a trench region, an ion implantation region, and a passivation layer.

7. A method for manufacturing a micro light emitting diode array, comprising:

providing a substrate, wherein the substrate comprises at least two element areas;

Forming a micro light emitting diode and at least one electrode unit in each element region, the step of forming a micro light emitting diode comprising:

Sequentially forming a first doped semiconductor layer, an active layer, a second doped semiconductor layer and a first electrode on the substrate;

The electrode unit is electrically connected with the first doped semiconductor layer in the micro light emitting diode, so that independent control of the micro light emitting diode is realized.

8. The method of manufacturing according to claim 7, wherein the electrode unit includes an auxiliary active layer, an auxiliary second doped semiconductor layer, and a second electrode sequentially formed over the first doped semiconductor layer;

The at least one electrode unit is formed synchronously in the step of forming a micro light emitting diode, and comprises the following steps:

sequentially forming the first doped semiconductor layer, the basic active layer and the basic second doped semiconductor layer on the substrate;

removing a portion of the base second doped semiconductor layer to form separate second doped semiconductor layer and auxiliary second doped semiconductor layer, the second doped semiconductor layer and the auxiliary second doped semiconductor layer having equal layer thicknesses;

removing a portion of the base active layer to form the separated active layer and auxiliary active layer, and exposing a portion of the first doped semiconductor layer;

and forming the first electrode and the second electrode in the same process, wherein the first electrode is positioned on the second doped semiconductor layer, the second electrode is positioned on the auxiliary second doped semiconductor layer, and the thicknesses of the first electrode and the second electrode are equal.

9. The method of manufacturing according to claim 8, further comprising:

an auxiliary metal layer is formed, a first end of the auxiliary metal layer is electrically connected with the second electrode, and a second end of the auxiliary metal layer is electrically connected with the first doped semiconductor layer.

10. The method of claim 9, wherein the step of simultaneously forming the at least one electrode unit in the step of forming a micro light emitting diode before removing a portion of the base second doped semiconductor layer further comprises:

forming a base conductive layer on the base second doped semiconductor layer;

And removing part of the basic conductive layer to form a separated conductive layer and an auxiliary conductive layer, wherein the thickness of the conductive layer is the same as that of the auxiliary conductive layer, the conductive layer is positioned above the second doped semiconductor layer, the auxiliary conductive layer is positioned above the auxiliary second doped semiconductor layer, the first electrode is positioned above the conductive layer, and the second electrode is positioned above the auxiliary conductive layer.

11. The method of claim 9, wherein after forming the separated second doped semiconductor layer and the auxiliary second doped semiconductor layer, forming a conductive layer and an auxiliary conductive layer using the same photolithography process, wherein the conductive layer is over the second doped semiconductor layer, the auxiliary conductive layer is over the auxiliary second doped semiconductor layer, the first electrode is over the conductive layer, and the second electrode is over the auxiliary conductive layer.

12. The method of manufacturing according to claim 10 or 11, wherein forming the auxiliary metal layer includes forming a first end of the auxiliary metal layer to cover a portion of the auxiliary conductive layer;

Forming the second electrode includes electrically connecting the second electrode with the auxiliary metal layer through the auxiliary conductive layer.

13. The method of manufacturing according to claim 12, wherein a spacer is formed between the first doped semiconductor layers of the adjacent element regions, the spacer being at least one of a trench region, an ion implantation region, and a passivation layer.

14. The method of manufacturing according to claim 13, wherein the spacer is formed after the first electrode and the second electrode are formed;

or forming the spacer after forming the auxiliary metal layer and before forming the first electrode and the second electrode;

and forming the spacing region before forming the auxiliary metal layer.

15. A display device comprising the micro light emitting diode array of any one of claims 1 to 6, and a microlens covering at least the micro light emitting diode.

16. An electronic device comprising the display device according to claim 15.