CN1222016C - Method of formation jonctions by laser annealing and rapid thermal annealing - Google Patents

Abstract

Methods are provided for thermal processing of a semiconductor wafer that contains a dopant material. The wafer is irradiated with laser energy sufficient to activate the dopant material without melting the wafer. In addition, rapid thermal annealing of the wafer is performed at relatively low temperature to repair crystalline damage. The dopant activation is achieved with no measurable diffusion. The low temperature rapid thermal anneal repairs crystalline damage, so that devices have good mobilities and low leakage currents.

Description

Method for forming ultra-shallow junction by laser annealing and rapid thermal annealing

related application

This application benefits from Provisional Patent Application Serial No. 60/190,233, filed March 17, 2000, which is hereby incorporated by reference in its entirety.

Technical Field of the Invention

This invention relates to methods of thermally treating semiconductor wafers containing doped materials, and more particularly to methods for obtaining ultra-thin semiconductor wafers by using sub-melt laser annealing and low-temperature rapid thermal annealing. Simple method.

Prior Art of the Invention

Ion implantation is a standard technique used to introduce conductivity-altering dopant materials into semiconductor wafers. In a conventional ion implantation system, desired dopant materials are ionized in an ion source, the ions are accelerated into an ion beam with a prescribed energy, and the ion beam is directed toward the surface of the wafer. The energetic ions in the ion beam penetrate into the semiconductor material and are embedded into the crystal lattice of the semiconductor material. Following ion implantation, the semiconductor wafer is annealed to activate the dopant material and to repair crystallographic damage caused by the ion implantation. Annealing involves heat-treating semiconductor wafers for a specified time and temperature.

A well-known trend in the semiconductor industry is towards smaller, higher speed devices. Specifically, both the lateral size and depth of features are reduced in semiconductor devices. The state of the art in semiconductor devices requires junction depths of less than 1,000 angstroms, and eventually may require junction depths on the order of 200 angstroms or less.

The implantation depth of the dopant material is determined by the energy of the ions implanted into the semiconductor wafer. Shallow junctions are obtained at low implantation energies. However, the annealing procedure used to activate the implanted dopant material causes outdiffusion of the dopant material from the implanted region of the semiconductor wafer. Due to this diffusion, the depth of the junction is increased by annealing. To counteract the increase in junction depth produced by annealing, the implant energy may be reduced such that the desired junction depth is achieved after annealing. This approach provides satisfactory results, except in the case of ultrashallow junctions. The limitation on the depth of the junction that can be obtained by reducing the implant energy is due to the diffusion of the dopant material that occurs during annealing.

Much work has been done to develop annealing procedures that limit the diffusion of dopant materials while activating them. Rapid thermal annealing or spike annealing is often utilized. A rapid thermal anneal typically involves heating the wafer to a temperature of 950°C to 1100°C over a period of 1 to 30 seconds, whereas a spike anneal may involve an anneal time of less than 0.1 second. As described in PCT Publication WO 99/39381, to minimize thermal diffusion, controlled low concentrations of oxygen can be added to the nitrogen atmosphere. Despite careful selection of annealing parameters, rapid ramp anneals and spike anneals still cause doped material to diffuse by means of heat, transient enhanced diffusion, oxidation enhanced diffusion, and doping enhanced diffusion (ie, boron enhanced or phosphorus enhanced diffusion). Thermal diffusion still occurs even when low concentrations of oxygen are added to the nitrogen environment and ultra-low energy implants are performed.

Another known annealing technique is laser annealing, as described in U.S. Patent Nos. 5,908,307, issued June 1, 1999 to Talwar et al. As described by example. The surface layer of the wafer is amorphized, and a dopant material is implanted in the amorphized surface layer. The amorphized surface layer is then irradiated with laser energy sufficient to melt the amorphized surface layer, thereby distributing the dopant material throughout the region of molten silicon. The integration of laser annealing with conventional device processing procedures is complex. In order to avoid melting of polysilicon gate circuits, pre-implantation of amorphous silicon or germanium is required, and deposition of anti-reflective metal films is also necessary.

The technique of forming shallow junctions by means of BF ₂ ⁺ ion implantation and excimer laser annealing with single pulse irradiation is H. Tsukamoto et al. in "Ultrashallow Junction Formed by Excimer Laser Annealing (Japanese Journal of Applied Physics, vol.31, Pt.2, No.6A, 1992, pp.659-662)]" described. If the laser fluence is too low to cause melting, the disclosed procedure will result in high sheet resistance.

US Patent No. 4,151,008, issued April 24, 1979 to Kirkpatrick, discloses thermally treating certain selected regions of a semiconductor device with short duration light pulses from a pulsed laser or flashlamp. If the energy density of the light is too low to cause melting, the disclosed process produces high sheet resistance.

All known prior art techniques for accomplishing semiconductor wafer anneals suffer from one or more disadvantages, including but not limited to: unacceptable levels of diffusion of dopant materials, high sheet resistance, and excessive complexity. Therefore, there is a need for an improved method for annealing semiconductor wafers that will achieve the desired dopant profile and sheet resistance, will repair crystallographic damage, minimize diffusion, and will not introduce undue complexity into the manufacturing process .

Summary of the invention

According to a first aspect of the invention there is provided a method for thermally treating a semiconductor wafer comprising a dopant material. Dopant materials may be implanted or deposited into the wafer by ion implantation, plasma doping, or any other suitable deposition technique. The method includes the steps of irradiating the wafer with laser energy sufficient to activate the dopant material without melting the wafer and subjecting the wafer to rapid thermal annealing at relatively low temperatures to repair crystallographic damage.

Preferably, the step of irradiating the wafer with laser energy is sufficient to heat the wafer to a temperature in the range of about 1100°C to 1410°C, and the step of rapid thermal annealing of the wafer is sufficient to heat the wafer in The wafer is heated to a temperature in the range of approximately 650°C to 850°C.

The implanted wafer is preferably irradiated with laser energy having a wavelength in the range of about 190 to 1500 nanometers. In one embodiment, the implanted wafer is irradiated with laser energy having a wavelength of 308 nanometers. Other suitable laser wavelengths include 532 nm and 1064 nm. The laser energy used to irradiate the wafer may include one or more laser pulses. The wafer can be irradiated with laser energy comprising 100 to 1,000 laser pulses, and the pulse width of the laser pulses can be in the range of 10 to 100 nanoseconds. The product of the number of laser pulses and the pulse width of the laser pulses may be in the range of 1 to 1,000 microseconds. In one embodiment, multiple laser pulses each having a pulse width of about 20 nanoseconds are used.

The laser annealing step may be performed in an atmosphere containing oxygen in nitrogen, wherein the concentration of oxygen is controlled within a range of less than 1 ppm to 1,000 ppm during laser irradiation of the wafer. The ramp annealing step may be performed in an atmosphere containing oxygen in nitrogen, wherein the concentration of oxygen is controlled within a range of less than 1 ppm to 1,000 ppm during the ramp annealing of the wafer.

According to a second aspect of the invention there is provided a method of forming doped regions in a semiconductor wafer. The method comprises the steps of implanting a dopant material into a semiconductor wafer, irradiating the implanted wafer with laser energy sufficient to activate the dopant material 5 without causing the wafer to melt, and irradiating the implanted wafer at a relatively low temperature. The wafer undergoes rapid thermal annealing to repair crystallographic damage.

The method of the present invention achieves activation of dopants without measurable diffusion. The rapid thermal anneal will repair the crystallographic damage from the implantation of the dopant material such that the device has good mobility and low leakage current. By eliminating melting of the silicon, distribution of dopant throughout the molten region is avoided.

Brief description of the drawings

For a better understanding of the present invention, reference is made to the accompanying drawings, which are hereby incorporated by reference, in which:

1 is a simplified partial cross-sectional view of a semiconductor wafer;

Figure 2 is a flow diagram illustrating an embodiment of the procedure of the present invention;

Figure 3 is a graph of boron concentration (in atoms per cubic centimeter) as a function of depth (in angstroms) for various procedures including embodiments of the procedure of the present invention.

Detailed Description of the Invention

A very simplified partial cross-sectional view of a semiconductor wafer 10 is shown in FIG. 1 . Junctions and regions of desired conductivity can be formed in semiconductor wafer 10 by ion implantation. It will be appreciated that real semiconductor devices include multiple structurally complex implanted regions, and that the semiconductor device 10 shown in FIG. 1 is shown for illustrative purposes only. Ion beam 12 of dopant material is directed at wafer 10 to create implanted region 14 . The depth of implanted region 14 is determined by a number of factors, including the energy and mass of the ions in ion beam 12 . The boundaries of implant region 14 are generally defined by implant mask 16 . The wafer is then annealed to activate the dopant material and repair crystallographic damage caused by ion implantation.

Prior art annealing procedures cause dopant material to diffuse into impurity regions 20 that are larger and deeper than implanted regions 14 . The impurity region 20 is characterized by a junction depth _Xj which is the normal depth of the impurity region 20 to the surface of the wafer 10 after annealing. One of the goals of making ultra-shallow junctions is to reduce diffusion to a sub-minimum and thereby limit the junction depth X _j .

It has been found that the junction depth Xj of the impurity region 20 after annealing can be compared to prior art procedures by utilizing a combination of low temperature rapid temperature annealing for the formation of ultra-shallow doping regions with minimal thermal diffusion and no melting. The novel heat treatment method of laser annealing in the sub-melt state is reduced. This procedure can be used to form ultra-shallow junctions with low sheet resistance and to form relatively deep impurity regions where thermal diffusion is undesirable after ion implantation.

An embodiment of the procedure according to the present invention is shown in the flowchart of FIG. 2 . A semiconductor wafer (usually a silicon wafer) may be implanted with a dopant material in step 50 . Preferred dopant materials include, but are not limited to, boron, indium, arsenic, and phosphorus. In one example, boron is implanted at ultra-low energy (ie, less than 1 keV). The dopant material can be implanted into the silicon wafer using a conventional ion implantation system, a plasma doping system, or any other system capable of depositing or implanting the dopant material to the desired depth in the semiconductor wafer.

In step 52, the wafer containing dopant material is irradiated with laser energy in a laser annealing step. The laser energy is sufficient to activate the dopant material without melting the wafer. The wafer is placed in a laser annealing chamber with a controlled environment and exposed to laser energy with predetermined parameters. The parameters of the laser annealing are selected to achieve high wafer temperatures (preferably in the range of about 1100°C to 1410°C) very rapidly without causing melting of the silicon or other wafer material. Because silicon is non-melting, the laser annealing step is referred to as "sub-melting state" laser annealing. The laser annealing step achieves activation of the dopant. Examples of suitable laser annealing parameters are described below.

Laser annealing step 52 preferably utilizes pulsed laser energy in the wavelength range of approximately 190 to 1500 nanometers. A preferred laser is an excimer laser with an output wavelength of 308 nm. Other suitable laser wavelengths include 532 nm and 1064 nm. Preferably, the laser energy should heat the silicon or other base material of the wafer to a depth of about 1 micron. Certain structures, such as polysilicon layered stacks, are thermally isolated from the bulk silicon by a dielectric. While laser energy is absorbed in deep layers of bulk silicon, thin layers of polysilicon absorb very little energy. It has been found that using longer wavelengths in the above range avoids undesired melting of the polysilicon gates.

The laser fluence used to irradiate the wafer is selected to rapidly (preferably in less than about 10 microseconds) rapidly heat the surface layer of the wafer to a temperature in the range of about 1100°C to 1410°C that does not melt the silicon . Silicon melts at 1410°C, as is known in the art. To achieve activation of the dopant material without melting the silicon, the laser fluence is preferably in the range of about 0.50 to 0.58 joules per square centimeter (J/cm ² ) at a wavelength of 308 nanometers and a pulse width of 20 nanoseconds.

The wafer is preferably irradiated with more than one laser pulse. The number of pulses can range from 1 to 10,000, and the pulse width can range from approximately 1 to 10,000 nanoseconds. The product of the number of laser pulses and the pulse width is preferably in the range of 1 to 1,000 microseconds. More preferably, the number of pulses is in the range of 100 to 1,000 and the pulse width is in the range of 10 to 100 nanoseconds. In one example of a suitable laser anneal, 100 pulses, each with a pulse width of 20 nanoseconds, are used to laser anneal a given area of a semiconductor wafer.

In one embodiment, the laser annealing step 52 can be accomplished by modifying the system used for conventional laser annealing, in which the amorphous layer of the wafer is melted. The parameters of the laser annealing system were modified to perform sub-molten laser annealing as described above. A suitable system is the model LA-100 available from Verdant Technologies, which can be modified to perform sub-molten state laser annealing as described above.

The laser beam used to irradiate the wafer may, depending on its cross-sectional area, cover the entire wafer area or a sub-area which is smaller than the entire area of the wafer. In one example, the laser beam has a cross-sectional area of 10 centimeters by 10 centimeters at the wafer surface. Where the laser beam covers a sub-area of the wafer, the wafer may be stepped or scanned relative to the laser beam in order to cover the entire area of the wafer. So, for example, a first subregion of a wafer can be irradiated with 100 pulses, each pulse having a pulse width of 20 nanoseconds, and then the wafer can be moved or stepped relative to the laser beam to a second subregion, and The second subregion can be irradiated with 100 laser pulses, each with a pulse width of 20 nanoseconds. This step-by-step procedure is repeated until the entire wafer area is irradiated. Where the laser beam is large enough to cover the entire wafer surface, a single sequence of laser pulses can be used to perform the laser annealing step. In another approach, the wafer can be stepped in small increments after one or more laser pulses, or can be scanned continuously so that the entire wafer surface receives the desired laser energy level. In yet another approach, the wafer remains stationary and the laser beam is deflected or otherwise moved relative to the stationary wafer in order to illuminate the entire wafer surface.

In step 54, the wafer is heated in a low temperature rapid thermal annealing step. The wafer is placed in a rapid thermal processing chamber with a controlled environment and heated according to predetermined parameters. The low temperature ramp annealing is preferably in the temperature range of about 650°C to 850°C for a time in the range of less than 1 second to 60 seconds. Rapid thermal annealing at low temperatures repairs crystalline damage from implantation, resulting in semiconductor devices with good mobility and low leakage current without causing significant diffusion of dopant materials. In one example, the wafer is heated to 700° C. for 20 seconds in a low temperature ramp annealing step.

Rapid thermal annealing systems for semiconductor wafers are commercially available. A suitable system is the model AST-3000 system available from STEAG-AST.

A low temperature rapid thermal anneal step 54 is shown following the laser anneal step 52 in FIG. 2 . Alternatively, the low temperature rapid thermal anneal step 54 may be performed prior to the laser anneal step 52 .

The laser annealing step 52 may be performed in an environmentally controlled closed chamber containing oxygen in nitrogen, preferably at one atmosphere pressure. Preferably, the concentration of oxygen in the laser annealing chamber is controlled during the laser annealing step 52 in the range of less than 1 ppm to 1000 ppm. The low temperature ramp annealing step 54 may be accomplished in an environmentally controlled thermal processing chamber, preferably containing oxygen in nitrogen at one atmosphere pressure. In a preferred embodiment, the oxygen concentration in the thermal processing chamber is controlled during the low temperature ramp annealing step 54 in the range of less than 1 ppm to 1000 ppm.

The advantages of the heat treatment method of the present invention are illustrated by the distribution curve of boron dopant shown in FIG. 3 . The dopant profile shown in Figure 3 was obtained using a secondary ion mass spectrometer (SIMS). In FIG. 3, the boron concentration (in atoms per cubic centimeter) is plotted as a function of depth (in Angstroms) from the wafer surface. In each case, silicon wafers were implanted with boron ions (B ⁺ ) at an energy of 1keV and a dose of 9E14/ ^cm2 (the symbol 9E14/ ^cm2 indicates that the implant dose is 9× ¹⁰¹⁴ atoms per cubic centimeter). of.

In FIG. 3, curve 70 represents a silicon wafer that has been implanted with boron as described above but has not been annealed. Curve 72 represents a silicon wafer that has been implanted with boron as described above and subjected to a peak anneal at a temperature of 1050°C for a duration of 0.2 seconds. Curve 74 represents a silicon wafer that has been implanted with boron as described above and subjected to a rapid thermal anneal at 700°C for a duration of 20 seconds. The measured sheet resistance of this wafer was 3500 ohms per square. Curve 76 represents a silicon wafer that had been implanted with boron as described above and was laser annealed below the melting threshold with 100 laser pulses at a wavelength of 308 nm followed by a rapid thermal anneal at 700°C for a duration of 20 seconds.

Curve 76 clearly shows that no measurable diffusion occurs and a sheet resistance of 360 ohms per square is still produced. The junction depth in the wafer represented by curve 76 is 372 Angstroms at a concentration of 3E18/cm ³ . In contrast, the wafer represented by curve 74 exhibited a much higher sheet resistance, indicating that the dopant material had not been activated. The peak annealed wafer, represented by curve 72, exhibited a substantial diffusion of dopant material resulting in a junction depth of 561 Angstroms. It will be appreciated that curves 70, 74 and 76 are nearly overlapping in FIG. 3 .

The heat treatment technique described here minimizes the thermal diffusion of dopant materials by exposing the wafer to very high temperatures for only a few microseconds and thereby minimizes the thermal diffusion of the dopant material. Improvements in annealing. For halo formation applications, this means that boron can be used as the dopant material instead of indium, which is currently preferred due to its relatively low diffusion effect, but due to the corrosiveness of its original material and the resulting low ion source lifetime so it is not preferred. Another application of the disclosed procedure is to form source/drain extensions that are steeper than those formed by rapid thermal annealing. The source/drain extensions formed by this procedure have the steepness of the implanted profile.

The present invention also improves upon conventional laser annealing by eliminating the melting of silicon. This makes it much easier to integrate the procedure into the device processing flow and avoids redistribution of dopants throughout the molten region. Furthermore, a pre-amorphized implant is not essential.

While there has been shown and described what are presently considered to be the preferred embodiments of the invention, various modifications can be made by those skilled in the art without departing from the scope of the invention as defined in the claims. Changes and modifications will be apparent.

Claims (18)

1. A method for thermally treating a semiconductor wafer comprising a dopant material, the method comprising the steps of: exposing the wafer to laser energy in a laser annealing chamber sufficient to activate the dopant material without melting the wafer; and The wafer is subjected to rapid thermal annealing at a low temperature in the rapid thermal processing chamber, wherein the rapid thermal annealing step of the wafer is performed non-simultaneously before or after the step of irradiating the wafer with laser energy. 2. The method of claim 1, wherein the step of irradiating the wafer with laser energy is sufficient to heat the wafer to a temperature in the range of 1100°C to 1410°C. 3. The method of claim 1, wherein the rapid thermal annealing step of the wafer is sufficient to heat the wafer to a temperature in the range of 650°C to 850°C for a time in the range of 1 second to 60 seconds. 4. The method of claim 1, wherein the wafer is irradiated with laser energy having a wavelength of 308 nanometers from an excimer laser. 5. The method of claim 1, wherein the wafer is irradiated with laser energy having a wavelength of 532 nanometers. 6. The method of claim 1, wherein the wafer is irradiated with laser energy having a wavelength of 1064 nanometers. 7. The method of claim 1, wherein the wafer is irradiated with laser energy having a wavelength in the range of 190 to 1500 nanometers. 8. The method of claim 1, wherein the wafer is irradiated with laser energy comprising more than one laser pulse. 9. The method of claim 1, wherein the wafer is irradiated with laser energy comprising 1 to 10,000 laser pulses. 10. The method of claim 1, wherein the wafer is irradiated with laser energy of laser pulses having pulse widths in the range of 1 to 10,000 seconds. 11. The method of claim 1, wherein the wafer is irradiated with laser energy consisting of 100 to 1000 laser pulses, and the pulse width of the laser pulses is in the range of 10 to 100 nanoseconds. 12. The method of claim 1, wherein the wafer is irradiated with laser energy consisting of more than one laser pulse, wherein the product of the number of laser pulses times the pulse width of the laser pulses is in the range of 1 to 1,000 microseconds. 13. The method of claim 1, wherein the wafer is irradiated with laser energy consisting of more than one laser pulse each having a pulse width of 20 nanoseconds. 14. The method according to claim 1, wherein the silicon wafer is irradiated with laser energy having a wavelength of 308 nm and a fluence in the range of 0.50 to 0.58 J/cm ^<2> . 15. The method of claim 1, wherein the rapid thermal annealing step of the wafer has a duration of 20 seconds. 16. The method of claim 15, wherein the rapid thermal annealing step of the wafer comprises heating the wafer to a temperature of 700°C. 17. The method according to claim 1, further comprising the step of controlling the concentration of oxygen in the range of 1 to 1,000 ppm during the step of irradiating the wafer with laser energy. 18. The method according to claim 1, further comprising the step of controlling the concentration of oxygen in the range of 1 to 1,000 ppm during the step of ramp annealing the wafer.

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