CN1237397C - 用于ars系统的器件隔离工艺流程 - Google Patents

用于ars系统的器件隔离工艺流程 Download PDF

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CN1237397C
CN1237397C CNB021203032A CN02120303A CN1237397C CN 1237397 C CN1237397 C CN 1237397C CN B021203032 A CNB021203032 A CN B021203032A CN 02120303 A CN02120303 A CN 02120303A CN 1237397 C CN1237397 C CN 1237397C
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C·-C·杨
P·哈特维尔
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Abstract

一种用于原子分辨存储(ARS)系统(200)的器件隔离工艺流程，该工艺流程在ARS系统(200)的工艺流程中插入器件隔离，使得二极管(370)彼此电绝缘，以改善信噪比。另外，由于在沉积存储数据位的相变层之前对其进行了最苛刻的处理，所以将存储数据位的相变层(323)的处理损伤降到最小。

Description

用于ARS系统的器件隔离工艺流程
技术领域
本技术领域涉及原子分辨存储(ARS)系统，具体说，涉及用于ARS系统的器件隔离工艺流程。
背景技术
ARS系统提供了一种带有存储密度大于每平方英寸1兆兆位(1000吉位)的小型器件。ARS技术建立在先进的原子探针显微镜基础上，其中，采用小到单个原子的探针场发射极尖顶来扫描材料表面，以产生精度在几个纳米的图象。探针存储技术可采用原子级探针场发射极尖顶的阵列，将数据读出和写入存储介质上的点。
ARS系统一般包括三个粘接的硅(Si)晶片，即尖顶晶片，也叫发射晶片，转子晶片，也叫动子晶片，和定子晶片。这些晶片采用本领域尽知的晶片粘接技术粘接在一起。
图1说明现有技术的ARS系统，其中，所有的二极管共享一个公共电极。尖顶晶片110包括多个场发射极尖顶114。可以用作存储介质以存储数据位的相变层123沉积在衬底转子晶片(120)上，也被称为动子晶片上。衬底转子晶片120是高掺杂硅衬底，它可以是n型衬底或p型衬底。将罩层160涂覆在相变层123上以保护相变层123和避免受热时材料蒸发。罩层160也改变了相变层123的表面状态。电子束聚焦电极113使得被聚焦的电子束116局部改变局部介质薄膜的相。如图1所示，转子晶片120可沿x和y的方向运动，使得可以向存储介质中写入以及从存储介质中读出数据位。
ARS存储介质使用p-n结二极管，即，用于读出数据位的器件埋入顶部有源硅层。在现有技术的ARS系统里，二极管享有公共电极(未示出)，这可能增大器件间的串音，导致较高的电噪音。
发明内容
用于ARS系统的器件隔离的方法包括：在晶片衬底与顶部有源硅层之间形成绝缘层，所述晶片衬底比如是转子晶片；在有源硅层顶部之上形成相变层；在相变层上沉积、形成图形，和有选择地蚀刻掩模层；使用掩模层作为掩模蚀刻顶部有源硅层直到绝缘层为止。其结果，二极管，即埋入顶部有源硅层的器件彼此电隔离，以提高ARS系统的信噪比。
在器件隔离工艺流程的实施方案中，通过将氧离子注入晶片衬底上的顶部有源硅层的下方以及和加热氧生成氧化物来形成绝缘层。
在另一个器件隔离工艺流程的实施方案中，绝缘层是利用反掺杂质来在转子晶片衬底上外延生长硅，以及加热反掺杂质而形成的。
器件隔离工艺流程把器件隔离插入ARS系统的工艺流程中，所以二极管可以彼此电气绝缘，以改善信噪比。另外，由于在沉积存储数据位的相变层之前进行了极苛刻的处理，这样就把相变层的处理损坏降到最小。
附图说明
参照下面附图对器件隔离工艺流程优选的实施方案进行详细说明，图中相似的编号代表相似的元件：
图1示出带有非隔离器件的现有技术的ARS系统；
图2(a)和2(b)示出典型的ARS系统；
图3示出带有隔离器件的示例性的ARS系统；
图4(a)-4(f)示出一个示例性的ARS系统的器件隔离工艺流程；
图5(a)-5(c)示出另一种用于ARS系统器件隔离的方法；
图6是说明ARS系统的示例性的器件隔离工艺流程的流程图。
具体实施方式
图2(a)和2(b)说明一个示例性的ARS系统200。该ARS系统200具有高数据存储能力，可达1000吉位/平方英寸。ARS系统200体积小、坚固、而且便于携带。另外，ARS系统200具有低功耗，因为，一般当ARS系统200不需要运行时，它不消耗功率。参见图2(a)，ARS系统200包括三个粘接的硅晶片，即尖顶晶片210，在本说明书中称之为第一晶片；转子晶片，一般也叫动子晶片，在本说明书中称之为第二晶片；和定子晶片230。转子晶片220的一般厚度为100μm，是高掺杂硅衬底，它可以是n型或p型衬底。用晶片粘接技术把晶片210，220，230粘接在一起，如图2(a)所示，晶片粘接技术在本领域是众所周知的。
每一晶片-晶片的粘接要求使用超高真空(UHV)密封件202密封的高真空内腔。其有助于保持ARS芯片的内部环境。晶片-晶片的粘接还要求低电阻的电连接。例如，如图2(a)所示，在转子晶片220的定子侧的导电极可与定子晶片230的转子侧的导电极相耦合。在转子晶片220的介质侧的导电极可与位于定子晶片230里的互补金属氧化物半导体(CMOS)线路232相连接。位于定子晶片230中的尖顶电子线路212控制场发射极尖顶214(见图2(b))，场发射极尖顶要求与ARS系统200里的存储介质222相连接。存储介质222包括介质记录单元224(见图2(b))将数据位存储在ARS系统200中。
含有CMOS线路232的读/写(R/W)电子线路也位于导电极234(b)下边的定子晶片230里。R/W电子线路可控制存储介质222中数据位的读出或写入。
通过晶片通孔226能使R/W电信号(未示出)从定子晶片230里的CMOS线路232传递到转子晶片220的介质侧的导电极，以及尖顶晶片210里的尖顶电子线路212。
图2(b)说明ARS系统200的运行。单个场发射极尖顶214产生电子束216，该电子束是从具有高电场的场发射极尖顶214的金属里引出的。通过加热微数据点和改变点的物理状态和相，聚焦电子束，并用于向存储介质中上写入数据位。电子束216还可用于确定存储介质222里数据位的状态(数值)。发射极尖顶阵列218是场发射极尖顶214的阵列，其下的存储介质222按纳米精度移动。图2(b)所示的悬置弹簧240可把转子晶片220固定在场发射极尖顶214和定子晶片230之间，使数据位相对于场发射极尖顶214移动，因此使每一个场发射极尖顶214存取多数据位。
为了ARS系统200的运行，需要对转子晶片220和定子晶片230进行处理，即：沉积导电极，用于纳米精度定位控制。ARS系统200工艺流程的实例在Lee等人的美国专利申请，名为“处理转子晶片的介质侧之后，使用硒化晶片粘接ARS动子晶片的工艺流程”和“处理转子晶片的介质侧之前，使用硒化物晶片粘接ARS动子片的工艺流程”中均有说明，它们是在同一天提交的，在这里一并列出供参考。
器件隔离工艺流程在ARS系统200的工艺流程中插入了器件隔离，以使二极管，即埋于相变层323(描述于后)里的小电子器件和顶部有源硅层330(稍后再述)和位于转子晶片220表面的电子器件可以彼此电绝缘。其结果，信噪比得以改善。另外，由于在沉积存储数据位的相变层之前，对相变层进行了最苛刻的处理，这样就把对相变层处理损坏降到最小。
图3叙述了一个带有隔离器件的典型的ARS系统。尖顶晶片210，也叫发射极晶片，可以包括多个场发射极尖顶214。尖顶发射极214可由平板发射极替代。绝缘层350，如埋入氧化物层350(a)(稍后再述)或反掺杂半绝缘硅层350(b)(稍后再述)，可以在转子晶片220上的顶部有源硅层330的下方形成。可以用作存储数据位的存储介质222的相变层323可以沉积在顶部有源硅层330的顶部。顶部有源硅层330与相变层323一道形成异质p-n结二极管370，用以在相变层323上对数据位进行电读出或写入。当具有不同电导类型的两种不同材料，在这种情况下例如有源硅和相变材料，生成结并且引起电流沿着一个方向流动时，一般就形成了异质p-n结二极管370(heterojunction p-n diode)。罩层360可以覆盖在相变层323上以保护相变层323，并防止加热时材料蒸发。罩层360也可以改善相变层323表面的状态。转子晶片220可沿x和y方向移动，以向存储介质222写入或从存储介质222中读出数据位。
器件隔离工艺能使多个异质p-n结二极管370相互电绝缘，所以每个隔离的二极管370与每个场发射极尖顶214耦合。通过沿x和y方向移动二极管370，可以将多个数据位写在单个隔离的二极管370上，因此减少了不同二极管370之间的相互串音的机会。随着电信号干扰的减少，大大地改善ARS系统200的信噪比。信噪比指的是对应于所读数据位的信号。
图4(a)-4(f)说明了ARS系统200典型的器件隔离工艺流程。图4(a)说明了在转子晶片220上顶部有源硅层330(a)下方进行氧离子注入。氧注入之后，通过热处理可以形成隔离氧化层350(a)。氧化层350(a)可以使顶部有源硅层330(a)和转子晶片220电绝缘，所以可防止二者之间的电子流动。
参见图4(b)，通过热蒸发沉积相变材料的薄膜可以形成相变层323(a)。该相变材料是可以进行从非晶转变成结晶材料。非晶材料的原子晶格一般已经为无序并且不具备长程有序。另一方面，结晶材料具有长程有序原子晶格的周期性排列，如果结晶材料是离子注入的，即往结晶材料中注入带有能量的离子，注入的离子会破坏结晶材料的晶格结构，所以，结晶材料可能失去长程有序而成为非晶材料。相变层323(a)可以用带有晶体本底的非晶体点的形式纪录数据位。保护罩层360可以任意地覆盖在相变层323(a)上，以保护相变层表面，并在加热时防止材料蒸发。
参见图4(c)，掩模层410，例如SiO2层或光学抗蚀剂材料(PR)层，可以被沉积在相变层323(a)上。掩模层410可以用例如光刻法形成图形，而且可以蚀刻掩模层410的预定部分。
参见图4(d)，与掩模层410清除部分相对应的相变层323(a)的曝露部分可以用干法或湿法工艺蚀刻。干法蚀刻是定向的、和各向异性的蚀刻，例如用等离子体，即：排出的气体和电子及中性原子的混合体完成。因此，干法蚀刻可以被广泛用于转移精细图形。湿法蚀刻用湿的化学试剂，如酸和碱来进行，所以定向性不好。湿法蚀刻的轮廓是各向同性的，所以湿法蚀刻不适合于转移亚微米级的精细图形。
图4(e)示出了下一个步骤，蚀刻顶部有源硅层330(a)直到绝缘氧化层350(a)为止。由于干法蚀刻较好的图形转移能力，干法蚀刻技术一般用于限定顶部有源硅层330(a)。因此，异质p-n结二极管370，即埋入顶部有源硅层330(a)和相变层323(a)中的器件，彼此成为电绝缘，以增加ARS系统200的信噪比。
参见图4(f)，掩模层410可以被去除。为了达到保护的目的，可以将保护罩层360可选地涂覆在相变层323(a)上。
图5(a)-5(c)示出了ARS系统200器件隔离工艺流程的另一个实施方案。取代穿过高掺杂的硅衬底的转子晶片220的氧离子注入，为了形成电气绝缘层，注入离子可以是反掺杂质，以形成半绝缘硅层350(b)。
首先，用外延工艺在硅衬底上生长结晶硅。在结晶硅生长的过程中，通过添加掺杂材料可以控制硅的类型，即n型或p型。在转子晶片220与顶部有源硅层330(b)之间，可以伴随反掺杂外延硅层形成半绝缘硅层350(b)。形成反p-n结二极管的这种工艺被称为“结隔离”。
因为外延硅可以在例如600-650℃，生成速度为0.5μm/分钟条件下生长，外延生长步骤的热堆积对定子晶片230中的热敏CMOS电路来说不是致命的。此外，可以对转子晶片220单独优化顶部有源硅层330(b)的掺杂浓度以获得最佳器件性能。
参见图5(a)，p型掺杂硅可以外延生长在反掺杂的，即n型，硅转子晶片220衬底上。用热处理激活p型硅掺杂质可以形成p型半绝缘硅层350(b)。作为替代，可以在p型硅转子晶片220衬底上外延生长n型半绝缘硅层。
其次，如图5(b)所示，在p型掺杂质的顶部可以外延生长n型掺杂硅。用热处理激活的n型硅掺杂质可以形成n型顶部有源硅层330(b)。作为替代，为了形成p型顶部有源硅层，在n型硅掺杂质上生长p型掺杂硅。
参见图5(c)，通过在n型顶部有源硅层330(b)上沉积相变材料可以形成p型相变层323(b)。作为替代，可以在p型顶部有源硅层上形成n型相变层。可选地，将保护罩层360沉积在相变层323(b)之上。
与图4(c)-4(f)相类似(图5未示出)，掩模层410，如硬掩模SiO2层或软掩模光学抗蚀剂材料(PR)层，可以沉积在相变层323(b)之上。掩模层410可以用例如光刻法形成图形，掩模层410的预定部分可以被蚀刻。然后，与掩模层410的清除部分相对应的相变层323(b)的曝露部分可以用干法或湿法工艺蚀刻。
其次，可以将顶部有源硅层330(b)蚀刻直到半绝缘硅层350(b)为止。因此，异质p-n结二极管370，即埋入顶部有源硅层330(b)和相变层323(b)中的器件彼此成为电绝缘，以提高ARS系统200的信噪比。最后，可以清除掩模层410，保护罩层360可以可选地涂覆在相变层323(b)和顶部有源硅层330(b)之上，起到保护作用。
图6是示出ARS系统100的器件隔离工艺流程的流程图。步骤610涉及在转子晶片衬底220上的有源硅层330之下进行氧离子注入或反掺杂质注入，然后，进行热处理以形成绝缘层350(步骤612)。随后，通过在顶部有源硅层330上沉积相变材料，可以形成相变层323(步骤614)。可选地，可以将保护罩层360涂覆在相变层323之上，起保护作用。
下一步，掩模层410，例如硬掩模SiO2层或软掩模光学抗蚀剂材料(PR)层，可以被沉积在相变层323之上(步骤616)。掩模层410(步骤618)通过光刻法形成图形并且掩模层410的预定部分可以被蚀刻(步骤620)。然后，与掩模层410蚀刻部分相对应的相变层323的暴露部分可以用干法或湿法工艺蚀刻(步骤626)。在步骤624中，顶部有源硅层330可以被蚀刻直到绝缘层350为止，最后，可以清除掩模层410(步骤626)，并且可选地将保护罩层360沉积在相变层323之上，起保护作用(步骤628)。
已用示例性的实施方案描述了器件隔离工艺流程，本领域的技术人员将会意识到按照这些教导，进行许多改进应是十分显而易见的，因此，本申请旨在涵盖它的任何变型。

Claims (6)

1.一种用于原子分辨存储系统(200)的器件隔离的方法，该方法包括：
在转子晶片衬底(220)和顶部有源硅层(330)之间形成(610，612)绝缘层(350)；
在顶部有源硅层(330)上部形成(614)相变层(323)；
在相变层(323)上沉积(616)掩模层(410)，其中该掩模层(410)被形成图形并且被有选择地蚀刻；以及
将掩模层(410)用作掩模蚀刻(624)所述顶部有源硅层(330)直到绝缘层(350)为止，由此，埋入顶部有源硅层(330)的器件(370)成为彼此电隔离。
2.权利要求1的方法，该方法还包括在相变层(323)上沉积(614)保护罩层。
3.权利要求1的方法，该方法还包括清除(626)掩模层(410)。
4.权利要求1的方法，其中形成绝缘层的步骤包括：
在晶片衬底(220)上的顶部有源硅层(330)下方进行氧离子注入(610)；和
加热(612)氧以形成绝缘层。
5.权利要求1的方法，其中形成绝缘层的步骤包括：
在晶片衬底上用反掺杂质外延生长(610)硅；和加热(612)反掺杂质。
6.权利要求1的方法，其中沉积步骤包括用光刻法对掩模层(410)形成(618)图形。
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