CS243095B1 - Connection of multi-input building block with capacitors switched by means of minimum number of change-over switches - Google Patents

Description

The invention relates to a multi-input building block with capacitors switched by a minimum number of switches.

The known methods of synthesizing switched capacitor circuits are of two kinds, indirect, in which elements or blocks of a non-capacity character in analog circuits are replaced by corresponding switched capacitor circuits, and direct, in which the transfer function of the corresponding analog circuit as a whole is simulated. In both cases, the design is always based on a certain p-z transformation and also the known switching capacitor building blocks correspond to the corresponding analog building blocks only for a certain type of this transformation.

The basic disadvantage of the current state is therefore that the known switching capacitor building blocks do not allow the synthesis of this kind of circuits directly in the z region, for example the direct-transfer function T (z). .

This disadvantage of the current state is overcome by the connection of the multi-input switching capacitor building block according to the invention, which is constituted by a voltage amplifier connected by its input to the first output of the integrating capacitor, to the second input switch terminal of each r-th-o switched capacitor. where r is a natural number · between 1 and R, with the first terminal of the first internal switch and with the second terminal of the second internal switch, the common terminal of the second internal switch is connected to the first terminal of the second feedback capacitor and the first terminal of each qth Inverting switched capacitor where q is a natural number ranging from 1 to Q, the second terminal of each qth inverting switched capacitor is connected to a common input terminal of the q th inverting switched capacitor, common terminal of the first internal switch is connected to the first terminal of the first feedback capacitor and the first terminal of each p-th direct-discharge switched capacitor, where p is a natural number between 1 and P, the second pin of each p-th direct-discharge switched capacitor is connected to a common input switch terminal p-th directly discharged switched capacitor, the common input switch terminal of each r-th switched capacitor is grounded through the r-th switched capacitor, the second output of the first feedback capacitor is connected to the second output of the second feedback capacitor with the common output switch terminal and the first output terminal , the first terminal of the output switch is connected to the output of the voltage amplifier and the second output terminal of the wiring, the second terminals of the input switches of each p-th directly discharged switching capacitor, of each q-th inverting the switching capacitor, the first internal switch and the output switch, the first terminal of the second internal switch, and the second terminal of the integrating capacitor are grounded, while the first input switch terminals of each p-th directly discharged switching capacitor, each q-th inverting switched capacitor and each r-th switch capacitors are formed by individual input terminals.

The advantage of connecting a multi-input building block with capacitors switched by a minimum number of switches according to the invention is that it allows direct synthesis of switched capacitor circuits in the z region and can be applied to any known structure resulting from decomposition of the transfer function into first order partial functions.

The invention will now be described in more detail with reference to the accompanying drawing, which shows a circuit diagram of an exemplary embodiment of a multi-input building block with capacitors switched by a minimum number of switches according to the invention. In the figure, the circuit consists of a voltage amplifier 1, connected by its input to the first terminal of the integrating capacitor 2, to the second terminal of the input switch 3 of each r-th switched capacitor 4r, where r is a natural number in the range 1 to R, s the first terminal of the first internal switch 5 and the second terminal of the second internal switch 6. The common terminal of the second internal switch 6 is coupled to the first terminal of the second feedback capacitor 7 and to the first terminal of each qth inverting switched capacitor 8q. 1 to Q, wherein the second terminal of each q-th inverting switched capacitor 8q is connected to a common terminal of the input switch 3 of the q-th inverting switched capacitor 8q. The common terminal of the first-internal switch 5 is connected to the first terminal of each p-th direct-discharge switched capacitor 9p, where, p is a natural number ranging from 1 to P, and to the first terminal of the first feedback capacitor 10. the discharged switched capacitor 9p is connected to the common terminal of the input switch 3p of the directly discharged switched capacitor 9p. The common terminal of the input switch 3 of each r-th switching capacitor 4r is grounded via the r-th switching capacitor 4r. The second terminal of the first feedback capacitor 10 is coupled to the second terminal of the second feedback capacitor 7, to the common terminal of the output switch 11, and to the first output terminal 12 of the wiring. The first terminal of the output switch 11 is connected to the output of the voltage amplifier and the second output terminal 13 of the wiring. The second input switches 243095 of each of the fifth directly discharged switched capacitor 9p, each qth inverted switched capacitor 8q, the first internal switch 5 and the output switch 11, the first terminal of the second internal switch 6 and the second terminal of the integrating capacitor 2 are grounded, the first terminals of the input switches 3 of each p-th directly switched switching capacitor 9p, each q-th inverting switched capacitor 8q, and each r-th switched capacitor 4r simultaneously form the individual input terminals of the wiring.

In the operation of a multi-input building block with capacitors switched by a minimum number of switches according to the invention, input voltage sources are connected to the input terminals and all input switches 3> output switch 11, first and second internal switches 5 and 6 are periodically switched in two phases. the common terminal and the first terminal are connected in the odd phase and the common terminal and the second terminal are connected in the even phase. Thus, in the odd phase, each p-th directly discharged capacitor 9p and the first feedback capacitor 10 are charged, while in the even phase they discharge directly without passing on their charge to other capacitors. Each q-th inverting switched capacitor 8q and the second feedback capacitor 7 also charge in the odd switching phase, but in the even switching phase they transmit their opposite polarity charge to the integrating capacitor 2, while each r-th switching capacitor 4r also in the switching phase, it charges this charge in the even phase to the integrating capacitor 2 with unchanged polarity. The voltage amplifier 1 amplifies the voltage · from the integration capacitor 2, so that at each output of the wiring there is an odd phase switching

where

For _9p ^(L) , the voltage is applied to the first terminal of the input switch 3p of the directly discharged switched capacitor 9p,

At _8q ^(L) , the voltage applied to the first terminal of the input switch 3 of the q th inverting switched capacitor 8q,

For _4r ^(L *, the voltage applied to the first terminal of the input switch 3 of the r-th switched capacitor 4r, while the transmission coefficients K _9p , K _8q and K _4r are given by

K = x + κ · - ²¹ -> (2) - c <3) = ± ητ ^- (4) ŘdeK · ^ χ + j- (l 1 = 1

where C _9p is the capacitance of the p-th directly switched switching capacitance 9p, C _Sq is the capacity of the q-th inverting switched capacitor 8q, C _4r is the capacitance of the rth switched capacitor 4r, C is the capacitance of the integrating capacitor 2 and A is the amplifier The relation (1j is assuming that the capacity of the second feedback capacitor 7 is equal to C / A) The sign of the individual transmission coefficients K _9p , K _8q and K _4r in _formulas (2), (3) and (4) are given by the capacity value C _the first feedback capacitor 10 to which the relationship applies

2__

A -1

and*

Thus, the odd-phase voltage transfer from the input terminal formed by the first terminal of the input-switch 3 of each p-th directly discharged switched capacitor 9p does not have a time delay and is either positive or negative, depending on whether the upper or lower sign in equation (6) . The voltage transfer from the input wiring terminal formed by the first terminal of the input switch 3 of each q-th inverting switched capacitor 8q is delayed by one switching period, as is the voltage transfer from the input wiring terminal formed by the first terminal of the input switch 3 of each r-th switching capacitor 4r but which always has the opposite sign, which results from equations (3) and (4).

The invention can be advantageously used in the synthesis of more complex switched capacitor circuits, in particular higher order filters and multiphase filters, if their properties are prescribed directly in the z plane.

Claims (1)

SUBJECT Connection of a multi-input building block with capacitors switched by a minimum number of switches, characterized in that it consists of a voltage amplifier (1) connected by its input to the first terminal of the integration capacitor (2), to the second terminal of the input switch (3) a capacitor (4r) where r is a natural number ranging from 1 to R, with the first terminal of the first internal switch (5) and with the second terminal of the second internal switch (6), the common terminal of the second internal switch (6) being connected to the first terminal of the second the feedback terminal (7) and the first terminal of each qth inverting switched capacitor (8qj, where q is a natural number ranging from 1 to Q, the second terminal of each qth inverting switched capacitor (8qj is connected to a common input switch terminal (3) q th Inverting Switching Capacitor (8q), common first MV terminal The first switch of the first-feedback capacitor (10) and the first terminal of each p-th directly discharged switched capacitor (9pj, where p is a natural number ranging from 1 to P, the second pin of each p-th a directly discharged switched capacitor (9pj is connected to the invention by a common input switch terminal (3) of the p-th direct discharged switched capacitor (9p), a common input switch terminal (3) of each r-th switched capacitor (4r) is over the rth switched the second output of the first feedback capacitor (10) is connected to the second output of the second feedback capacitor (7), the common output switch terminal (11) and the first output terminal (12) of the wiring, the first output switch terminal (11) is connected to the output of the voltage amplifier (1) and to the second output terminal (13) of the wiring, the second (3), each q-th inverting switched capacitor (8qj, the first internal switch (5) and the output switch (11), the first terminal of the second-internal switch (6), and the second the terminals of the integrating capacitor (2) are grounded, while the first input switch terminals (3) of each p-th direct-discharge switching capacitor (9p), each q-th inverting switching capacitor (8q) and each r-th switching capacitor (4r) they also form the individual input terminals of the wiring.