CS255003B1 - A peripheral system for controlling a slave processor by a control processor - Google Patents

Abstract

Its control processor (1) is connected by its trigger output to the setting input of the first flip-flop (8), by its release output to the setting input of the second flip-flop (9), by its control transfer request input to the reset input of the first flip-flop (8) and to the output of the second flip-flop (9), and by its reference address outputs to the first inputs of the comparator (10), connected by its output to the reset input of the second flip-flop (9) and to the addressing outputs of the slave processor (3), connected by its blocking input to the output of the first flip-flop (8) and to its gates with the bus (47). The solution can be used in particular in the field of emulation of the operation of various types of processors, especially single-chip ones, in connection with a microcomputer or minicomputer system as a relatively simple addition to it.

Description

BACKGROUND OF THE INVENTION The present invention relates to a circuit system for controlling a slave processor by a control processor, wherein the control processor is connected to a bus through its gates, to which a slave processor, random-access memory and a higher system block are further connected by its gates.

Currently, the emulation processor, in particular in the development work on microprocessor systems, using either circuit emulators ICE or _a simpler single emulators.

The disadvantage of JCE circuit emulators is mainly that it is a very complex single-purpose microcomputer, which usually requires connection to a higher system and is not capable of independent operation. The disadvantage of simpler stand-alone emulators is that they do not allow working at the code level of symbolic addresses, program edition, archiving and reading. from modern, fast recording media, with a relatively large range of hardware.

The aforementioned disadvantages of the prior art are largely eliminated by a circuit system for controlling the slave processor by the control processor, where the control processor is connected to the bus through its gates, to which they are further coupled by steam through arbitrary selections and a higher system block. it is connected with its trigger output to the first flip-flop setting input, its release output to the second flip-flop setting input, and to its request input.

2S5 003 control transfer batch with resetting input of the first flip-flop and outputting of the second flip-flop and its reference address outputs with the first comparator inputs connected with its output with the resetting input of the second flip-flop and its second inputs with addressing outputs of the slave processor connected with its input with output the first flip-flop and its bus gates. It is advantageous in this case if the connection of the slave processor gateways to the bus is carried out via a bus control circuit, which is further connected by its data outputs to the second comparator inputs and its control input to the output of the first flip-flop.

The advantages of a circuit system for controlling the slave processor by the control processor are in particular its simplicity, and the fact that the control processor is part of a higher system allows for high level emulation due to the equipment of the higher system.

The invention will now be described in more detail with reference to the accompanying drawing, in which a block diagram of an exemplary circuit system for controlling a slave processor by a control processor according to the invention is shown.

The circuitry for controlling the slave processor by the control processor comprises, in an exemplary embodiment, a control processor 1, a control circuit 2, a slave processor 3, a bus 4, an arbitrary selection steam 5, a higher system block 6 and a bus control circuit 7.

2SS 003 *

A control processor 1, an arbitrary memory 5, a higher system block 6 and a bus control circuit 7 are connected to the bus 4 via their gates. The control processor 11 is further coupled by its trigger output to the first flip-flop setting input, its release output to the second flip-flop setting input, its control transfer input to the flip-flop 8 reset input and the second flip-flop output, and its reference address outputs. The comparator 10 is coupled by its output to the reset input of the second flip-flop 6 and its second inputs to the addressing outputs of the slave processor 3 and to the gateways of the bus control circuit 7. The slave processor 8 is connected by its blocking input to the output of the first flip-flop 8 and to the input of the bus control circuit 7. The bus control circuit 7 is then connected to the bus 4 via its second ports.

In the operation of the slave processor circuitry by the master processor, the slave processor 3 is stopped by default, the master processor 11 controls the bus 4 and, by means of its master program, prepares in a randomly selected memory 5 a program to control the slave processor. At the point where the slave processor 3 is to be interrupted, a jump to the address corresponding to the first inputs of the comparator 10 is assigned. Then a signal is sent from the release processor 1 to set the second flip-flop 9 '. it unlocks the first flip-flop 8 and at the same time sends to the control processor 1 a signal representing a request to release the bus 4 and pass control to the slave processor 3. The control processor 1 releases the bus 4 and acknowledges the control the slave processor 3 takes over the bus control 4, preferably via the bus control circuit 7, and continues to control its operation by a program stored in the memory 5 of arbitrary selection in that sends 7 rows across the circuit the bus and bus 4 into the arbitrary memory 5, which selects the program data from the memory 5, which are then fed via the bus 4 and the bus control circuit 7 to the slave processor 3 they control. when the slave processor 3 sends to the bus control circuit 7 and to the second inputs of the comparator 10 an address which is identical to the address on the first comparator inputs.

If the addresses at its first and second inputs match, the comparator 10 returns the second flip-flop 9 to its starting state, the second flip-flop 9 flips the first flip-flop 8, and the flip-flop 8 stops the slave processor 3 and releases bus 4. from the output of the second flip-flop 9 a control processor 1, which takes over the control of the bus 4 and hence the control of the memory 5 with any selection.

- 5 255 003

The invention can be used in particular in the field of emulation of various types of processors, in particular single-chip processors, in conjunction with a microcomputer or minicomputer system as a relatively inexpensive and circumferentially undemanding complement thereof,

SUBJECT OF THE INVENTION

Claims (2)

SUBJECT OF THE INVENTION Circuit system for controlling a slave processor by a control processor, wherein the control processor is connected via a gateway to a bus, to which a random-access memory and a higher-level block are further connected to the gateway, characterized in that the control processor (1) is connected by its trigger output to the first flip-flop setting input (8), its release output to the second flip-flop setting input (9), its forwarding request to the first flip-flop (8) reset input, and the second flip-flop (9) output; by its reference address outputs with the first comparator inputs (10) connected by its output to the resetting input of the second flip-flop (9) and by its second inputs to the address outputs of the slave processor (3) connected by its latching input to the output of the first flip-flop (8); with their bus gates (4). Circuit system according to claim 1, characterized in that the gateway of the slave processor (3) to the bus (4) is connected via a bus control circuit (7) which is further connected by its data outputs to the second comparator inputs (10) and its control input with the output of the first flip-flop (8),