CS273970B1 - Connection of dynamic stores' information recovery control in microcomputer systems - Google Patents

Abstract

The connection is intended for systems with the microprocessors 8086/8088. It consists of the processor (1), programmable counter (2), sequential circuit (3), address register (4), dynamic memory (5), multiplexer bus (6) and circuit (7) of logical sum, which are interconnected according to the figure. It is suitable even for small, monoboard microcomputers where it enables to use dynamic memory and hence enhance capacity of the installed memory.<IMAGE>

Description

(57) The wiring is intended for 8086/8088 microprocessor systems. It consists of a processor (1), a programmable counter (2), a sequential circuit (3), and an address register (4). dynamic memory (5) as well as multiplexer bus (8) and logical sum circuit (7) interconnected as shown in Figure · Oe also suitable for small, single-board microcomputers where it allows the use of dynamic memory to increase the installed memory capacity ·

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The invention relates to a circuit for controlling the recovery of dynamic memory information in microcomputer systems.

For dynamic memories in microcomputer systems, it is necessary to periodically recover information. Some microprocessors already have information recovery circuits built in. Another option is to use a direct memory access controller to recover information. · The 8086/8088 microprocessors do not contain information recovery circuits, and ensuring this functionality in small systems without a DMA controller is problematic. Therefore, more expensive static memories are used; which do not require information to be refreshed; however, they have less capacity.

Said drawbacks eliminate the circuitry for controlling the recovery of dynamic memory information in the microcomputer systems of the present invention, which consists of a processor, a counter; a sequential circuit; address register, dynamic memory, bus, and logic sum circuit. Its essence is; The first output of the processor is connected by the ge input of the sequential circuit and at the same time by the input of the counter and by the first input of the logic sum circuit. The third output of the processor is coupled to the second input of the logic sum circuit. The second processor output is connected to the bus; which is simultaneously connected to the address register inputs and counter input / output. The output of the first counter section is connected to the processor input and simultaneously to the input of the second counter section. The sequential circuit output is coupled to the dynamic memory input® The logical sum circuit outputs are coupled to the address register input.

The described circuitry makes it possible to realize circuits for recovering the contents of dynamic memory g by a considerably smaller number of components than hitherto, while the necessary components are commercially available.

This is also possible in small; single board microcomputers use dynamic memory; which allows you to increase the installed memory capacity.

The attached drawing illustrates, in a block diagram, a particular wiring for controlling the recovery of dynamic memory information in microcomputer systems with 8086/8088 microprocessors.

The circuitry consists of a processor JL; a programmable counter 2, a sequential circuit 13; address multiplexer-4 address, dynamic memory 5; multiplexer data / address bus 5 and logic sum circuit 7. Programmable counter 2 has three independent sections. The first one serves for periodically generating a bus lease request 6; the second as an address counter and the third is unused. The first request acknowledgment output 12 of the processor 11 is connected to the input 31 of the sequential circuit 3 and simultaneously to the input 24 of the counter reader 2 and to the first input 71 of the logical sum circuit 7. A third output 14 for writing the address of the processor 1. It is coupled to the second input 72 of the logic sum circuit 7. A second output of the bus signals of the processor 1 is connected to the bus. which is simultaneously connected to the inputs 41 of the address register 4 and the input / output 23 of the bus signals of the counter 2. The output 21 of the first section of the counter 2 is connected to the input 11 of the processor bus 1 and the input 22 of the second section of the counter 2. The output 42 of the address register 4 is connected to the inputs 52 of the dynamic memory 5. The output 73 of the logic sum circuit 7 is connected to the write input 43 of the address register 4.

The processor 1 has a bus rental request input 11. If counter 2 is requesting a bus, the processor 1 will lend it and signal it on the first output 12, which is led to read input 24 of counter 2, thereby releasing the contents of the second section of counter 2 via input / output 23 on bus 5 '. on the other hand, to the input 31 of the sequential circuit 3, the sequential logic circuit 3 generates a pulse at the output 32; At the same time, from the counter 2, the rows of the memory elements being restored are generated on the bus 5 and the address of the memory element being restored. This address comes to the register address. Outputs 42 of the address register 4 track the state of the inputs 41 while the write input 43 is high. The write input 43 of the address register 4 is controlled via the logic sum circuit 7 when the processor is active. A signal at its third output 14 for address writing and recovery of information in the dynamic memory 5 by the acknowledgment, bus request signal at the first output 12 of the processor 1. Thus, the address register 4 is passable and the address passes to the inputs 52 of the dynamic memory 5j. is written by a signal at the input 51 of the dynamic memory 5 «after address entry

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CS 273970 B1 to Dynamic Memory 5 Counter 2, which is programmable, ceases to request bus lending 6. The processor 1 takes over control of the bus 6i and resumes active operation. The first section of the counter 2 measures the programmed time interval, and after that the next cycle of information recovery occurs in the dynamic memory 8, with the difference that the second section of the counter 6 now contains the address of the next line. to write the address of all rows of the dynamic memory 5, for example 128 rows in 2 ms, during the required time.

Claims (1)

OBJECT OF THE INVENTION A circuit for controlling the recovery of dynamic memory information in microcomputer systems, comprising a processor, a counter, a sequential circuit, an adrse register, a dynamic memory, a bus, and a logical sum circuit, characterized in that the first output (12) of the processor (1) is connected. with the input (31) of the sequential circuit (3) and at the same time ee input (24) of the counter (2) and with the first input (71) of the logic sum circuit (7), the third output (14) of the processor (1) is connected to the second input (72) ) a logic sum circuit (7); the second output (13) of the processor (1) is connected to the bus (6); which is simultaneously connected to the inputs (41) of the address register (4) and to the input / output (23) of the counter (2), the output (21) of the first section of the counter (2) Simultaneously by the input (22) of the second section of the counter (2), the output (32) of the sequential circuit (3) is connected to the input (51) of the dynamic memory (5) and the outputs (42) of the address register (4). ) of the dynamic memory (5) and the output (73) of the logic sum circuit (7) is connected to the input (43) of the address register (4). 1 drawing